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Microprogrammed Control

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Overview• Control signals are generated by a program similar to machine

language programs.• Control Word (CW); microroutine; microinstruction

P C i n

P C o u t

M A R

i n

R e a d

M D R o

u t

I R i

n

Y i n

S e l e c t

A d d

Z i n

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t

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u t

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W M F C

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Micro -instruction

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Figure 7.15 An example of microinstructions for Figure 7.6.

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Overview• Control store

Figure 7.16. Basic organization of a microprogrammed control unit.

storeControl

generator

Startingaddress

CW

Clock µ PC

IROne unctioncannot be carried

out by this simpleorgani3ation.

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Overview• 4he previous organi3ation cannot handle the situation when

the control unit is re0uired to chec5 the status o the conditioncodes or e2ternal inputs to choose between alternative courseso action.

• 6se conditional branch microinstruction.Address Microinstruction

7 PC out M!" in "ead #elect$ !dd % in

1 %out PCin ' in WM C

& M*" out +"in8ranchtostartingaddresso appropriate microroutine

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

&, + 9:7 thenbranchtomicroinstruction7

&- O set

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Overview

Figure 7.18. Organization of the control unit to allowconditional branching in the microprogram.

Controlstore

Clock

generator

Starting andbranch address Conditioncodes

inputsExternal

CW

IR

µ PC

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Microinstructions• ! straight orward way to structure

microinstructions is to assign one bitposition to each control signal.

• ?owever this is very ine@cient.• 4he length can be reducedA most

signals are not needed

simultaneously and many signalsare mutually e2clusive.• !ll mutually e2clusive signals are

placed in the same group in binarycoding.

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Partial ormat or theMicroinstructions

F2 (3 bits)

000: No transfer001: PC in010: IR in011: Z in

100: R0 in101: R1 in110: R2 in111: R3 in

F1 F2 F3 F4 F5

F1 (4 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transfer0001: PC out 0010: MDR out 0011: Z out

0100: R0 out 0101: R1 out 0110: R2 out 0111: R3 out 1010: TEMP out 1011: Offset out

000: No transfer001: MAR in010: MDR in011: TEMP in

100: Y in

0000: Add0001: Sub

1111: XOR

16 ALUfunctions

00: No action01: Read10: Write

F6 F7 F8

F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY1: Select4

0: No action1: WMFC

0: Continue1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

Microinstruction

What is the price paid orthis schemeB

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urther +mprovement• /numerate the patterns o re0uired

signals in all possiblemicroinstructions. /ach meaning ulcombination o active control signalscan then be assigned a distinct code.

• ertical organi3ation• ?ori3ontal organi3ation

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Microprogram #e0uencing• + all microprograms re0uire only

straight orward se0uential e2ecution omicroinstructions e2cept or branches lettinga DPC governs the se0uencing would bee@cient.

• ?owever two disadvantagesA?aving a separate microroutine or each machineinstruction results in a large total number omicroinstructions and a large control store.Eonger e2ecution time because it ta5es more time to carryout the re0uired branches.

• /2ampleA !dd src "dst• our addressing modesA register

autoincrement autodecrement and inde2edwith indirect orms .

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Microinstructions with 9e2t

• 4he microprogram we discussed re0uiresseveral branch microinstructions whichper orm no use ul operation in the datapath.

• ! power ul alternative approach is to includean address =eld as a part o everymicroinstruction to indicate the location o thene2t microinstruction to be etched.

• ProsA separate branch microinstructions arevirtually eliminated; ew limitations inassigning addresses to microinstructions.

• ConsA additional bits or the address =eld(around 1F-)

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Microinstructions with 9e2t

Figure 7.22. Microinstruction-sequencing organization.

Conditioncodes

IR

Decoding circuits

Control store

Next address

Microinstruction decoder

Control signals

InputsExternal

µ AR

µ IR

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F1 (3 bits)

000: No transfer001: PC out 010: MDR out 011: Z out 100: Rsrc out 101: Rdst out 110: TEMP out

F0 F1 F2 F3

F0 (8 bits) F2 (3 bits) F3 (3 bits)

000: No transfer001: PC in010: IR in011: Z in100: Rsrc in

000: No transfer001: MAR in

F4 F5 F6 F7

F5 (2 bits)F4 (4 bits) F6 (1 bit)

0000: Add0001: Sub

0: SelectY1: Select4

00: No action01: Read

Microinstruction

Address of nextmicroinstruction

101: Rdst in

010: MDR in011: TEMP in100: Y in

1111: XOR

10: Write

F8 F9 F10

F8 (1 bit)

F7 (1 bit)

F9 (1 bit) F10 (1 bit)

0: No action1: WMFC

0: No action1: OR indsrc

0: No action1: OR mode

0: NextAdrs1: InstDec

Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

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+mplementation o the Microroutine

(See Figure 7.23 for encoded signals.)Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

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next-microinstruction address field.

011000 0 0 0 0 00 00 00000 0 0 0 0 030 0 00 0 0