Transcript
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n3

n2

n1

VDD LED 3

LED 2

LED 1

LED 1LED 2LED 3

Ve

DG

S

B

S i n

n 3 n 2 n1

VD D

M1M2 M3

Fig. 1a

COEN 451

It is required to design a circuit which controls a bar display consisting of three LEDs as shown in Fig.1a. The operation of these LEDs is based on the level of the input signal:LED1 is ON when the input voltage reaches 0.5VLED1 and LED2 are both ON when the input signal reaches1.0 V.All LEDs are ON when the input signal reaches 1.5V.The circuit, which controls the display that consists of three transistors, each of a distinct threshold voltage as shown in Fig.1 bM1 is an NMOS transistor with a VTO=0.5V.M2 is the same type of transistor with a threshold voltage adjusted by an external voltage Ve.M3 is the same type transistor of M1 with a threshold voltage adjusted by an ion implantation process.a. Specify the threshold voltage of each of the transistors to achieve the required operation.b. Determine the value of the external voltage Ve.c. Determine the type and dose of the dopant so that the threshold voltage of M3 is adjusted from 0.5V to the required value.

The transistors have the following parameters: tox =200Ao, = 0.5 V1/2, s = -0.6V

Maxime SCHNEIDER (ID: 6718809)Due date: September 24th 2014

COEN 451 - Assignment 1

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COEN 451

a /According to the wording, we have :

(V t )M 1=V t 0=0.5V

(V t )M 2=1.0V

(V t )M 3=1.5V

b /For transistor M2, we have:

V T=V t 0+γ (√|V SB+φS|– √|φ S|)

V T−V t0

γ=√|V SB+φS|– √|φ S|

V T−V t0

γ+√|−φS|=√|V SB+φ S|

|V SB|¿(V T+V t 0

γ+√φ S)

2

−|φS|

N.A.

VSB = ±( 1−0.50.5

+√0.6)2

−(−0.6)=±2.55 V

Since PN junctions have to be reversed biased, V SB has to be positive to allow drain and source to work correctly. Therefore, V SB = 2.55V.

Finally, we get V e=−2.55V

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COEN 451

c /For transistor M3 we have:

V T=V T 0+q DI

COx

Dopant is of p-type.

Since Cox=εoxt ox

, other formula: Cox=0.345

t ox (Angstrom)

D1=V T−V t0

qCox

D1=0.345(V ¿¿T−V t 0)

q tox¿

N.A.

D I=(1.5−0.5 )∗0.3451.6∗10−19∗200

=0.345320

1 019=1.078 1012atom/cm2

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Figure 1a

COEN 451

Question 1 An nMOS transistor has a physical layout shown in Figure 1a. The transistor has the following device parameters:Cox = 1.5fF/m2 μn= 500cm2/V-sec Φs = -0.6V γ = 0.3V1/2

Cjsw = 0.7fF/m CjB = 0.5fF/m2

λ = 0.015V-1

VTO = 1.0V

Note: 1division=1um

a.Determine the following parasitic resistances and

capacitances:1. The transistor gate capacitance2. The source (drain) capacitance

Note: Neglect the effect of the silicon outside the transistor area and metal line effect.b.The above transistor is connected in a circuit with node

voltages shown in Figure 1b.

Maxime SCHNEIDER (ID: 6718809)Due date: October 1st 2014

COEN 451 - Assignment 2

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COEN 451

Determine the channel resistance.

Question 2 Determine the regime of operation for the transistors shown in Fig.2Assume VT0,N = - VT0,P = 0.8V = 0.5 V1/2

sn = -sp = -0.6V

4V

2V

3V 0V

i.

4V

2V

1.5V 5V

ii.

2V

4V

1V 4V

iii.

1V

5V

2.5V 0.5V

iv.

Question 1a /Transistor gate capacitance is given by:

Cgate=AgateCox

Area of the gate is Agate=W∗L.

Figure 1b

Fig.2

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COEN 451

So,Cgate=W LCox

N. A.Cg=5∗1∗1.5 Cg=7.5 fF

Gate to drain capacitance is:Cgd=CJb∗Adrain+C JSW∗Pdrain

Area of the drain is Adrain=LDW D

Perimeter of drain is Pdrain=2 LD+W D

Thus, Cgd=CJb∗LDW D+CJSW (2LD+W D)

N. A.CD=0.5∗5∗5+0.7∗(2∗5+5) CD=23 fF

b /

This is a N-MOS transistor. To determine the channel resistance, we first have to determine the operation region.

V t=V t 0+γ (√|V SB−ϕS|– √|−ϕS|)N. A.

SOURCE

GATE

DRAIN

BULK

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COEN 451

V t=1+0.3 (√2−(−0.6)−√|−0.6|) = 1.25V

V gs=V GATE−V SOURCE

N. A. V gs=4−2=2V

V gs> V t transistor is ON.V ds=V DRAIN−V SOURCE

N. A. V ds=5−2 = 3V V ds> V gs−V t Transistor is working in Saturation region.

In saturation region, Resistance is calculated as following:R= 2

λ β (V gs−V t )2

with βn=μnCoxn(WL )n

R= 2

λ μnCoxn(WL )n

(V gs−V t )2

N.A.R= 2

0.015∗500∗1.5∗10−2∗10−2∗51

∗(2−1.25 )2

¿ 211.25∗10−4∗0.5625

¿ 2

56.25∗10−4 ¿355 K ΩAs Coxn is per mm2 and μn is expressed in c m2 Question 2

Transistor (i)V SB=V SOURCE−V BULK

V SB=2−0=2V

V t=V t 0+γ (√|V SB−ϕS|– √|−ϕS|)

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COEN 451

V t=0.8+0.5 (√2−(−0.6)−√|−0.6|)=1.218V

V GS=V GATE−V SOURCE

V GS=3−2=1VV gs<V t so Transistor is OFF, in the cut-off region.

Transistor (ii)V SB=V SOURCE−V BULK

V SB=4−5=−1V

V t=V t 0+γ (√|V SB−ϕS|– √|−ϕS|)V t=−0.8+0.5 (√0.6+1−√|−0.6|)=−1.045V

V GS=V GATE−V SOURCE

V GS=1.5−4=−2.5VV gs<V t Transistor is ON.

V DS=V DRAIN−V SOURCE

V DS=2−4=−2V

V GS−V t=−2.5+1.045=−1.455VV DS<V GS−V t Transistor is in saturation mode.

Transistor (iii)V SB=V SOURCE−V BULK

V SB=4−4=0V

V t=V t 0+γ (√|V SB−ϕS|– √|−ϕS|)V t=V t0=−0.8V

V GS=V GATE−V SOURCE

V GS=1−4=−3VV gs<V t Transistor is ON.

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COEN 451

V DS=V DRAIN−V SOURCE

V DS=2−4=−2V

V GS−V t=−3+0.8=−2.2VV DS>V GS−V t Transistor is in linear region.

Transistor (iv)V SB=V SOURCE−V BULK

V SB=1−0.5=0.5V

V t=V t 0+γ (√|V SB−ϕS|– √|−ϕS|)V t=0.8+0.5 (√0.5−(−0.6)−√|−0.6|)=0.937V

V GS=V GATE−V SOURCE

V GS=2.5−1=1.5VV gs>V t Transistor is ON.

V DS=V DRAIN−V SOURCE

V DS=5−1=4 V

V GS−V t=1.5−0.937=0.63VV DS>V GS−V t Transistor is in saturation mode.

ConclusionTransis

torV t V gs V ds V GS−V t state region

1 (NMOS) 1.218 1 OFF Cut-off2 (PMOS) -

1.045-2.5 -2 -1.455 ON Saturatio

n3 (PMOS) -0.8 -3 -2 -2.2 ON Linear4 (NMOS) 0.937 1.5 4 0.63 ON Saturatio

n

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COEN 451

APPENDIX A

Technology parameters of CMOSIS 5B

1. Specification of CMOSIS5, 0.5μm technology

The model parameters of PMOS and NMOS transistor which should be used in your calculation are listed below.

Model cmos NMOS level3:Vto=0.6566V, kn=196.47μA/V2, μn=546.2cm2/V·s,Cox=3.6e-03F/m2, Cj=5.62e-04F/m2, Cjsw=5.0e-12F/m2, Cjgate=5.0e-12F/m2,

Cgbo=4.0239e-10F/m2, Cgdo=3.0515e-10F/m2 Cgso=3.0515e-10F/m2

Model cmosp PMOS level3:Vto=-0.9213V, kp=48.74μA/V2, μp=135.52cm2/V·s,Cox=3.6e-03F/m2, Cj=9.35e-04F/m2,Cjsw=289.00e-12F/m2, Cjgate=289.00e-12F/m2

Cgbo=3.7579e-10F/m2, Cgdo=2.3922e-10F/m2

Cgso=2.3922e-10F/m2

VDD = 3.3 voltage

APPENDIX B

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COEN 451

Cgaten=(W x L)n x CoxCgatep=(W x L)p x CoxCgd= Cgbo * 2L + Cgdo * W + Cgso * W

Cdbn, Cdbp are junction capacitance of present level

Cdb= Cj * Area + Cjsw * (W +2L) + Cjgate * W

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COEN 451

A CMOS inverter shown above was designed using CMOSIS 5B technology. Process parameters are given in the appendix. The following design parameters were used in the design:Ln = Lp = Lmin Wn = 4 Lmin Wp= 2Wn VDD = 3.8 V

Determine, VIL,max, Vth, VOH,min and the Noise Margins high and Low of this inverter.You may assume, LD, ΔW and are all zero. Also you may assume that VOL,min= 0 and VOH,max=VDD.

Maxime SCHNEIDER (ID: 6718809)Due date: October 15th 2014

COEN 451 - Assignment 3

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COEN 451

Determination of V ILMAX

P-MOS is in linear region and N-MOS is saturated. Thus, IDp=−I Dn leads to

kn '2 (V gsn−V tn)2=k p ' [(V gsp−V tp )V dsp−

V dsp2

2 ] (1)

For P-MOS: V gsp=V ¿−V DDand V dsp=V 0−V DD

For N-MOS: V gsn=V ¿ and V dsn=V 0

Substituting in (1),W n

Ln

kn '2 (V ¿−V tn )2=

W p

Lpk p ' ¿ (2)

W n

Ln

kn '2

(V ¿−V tn)=W p

Lpk p ' ¿ (3)

In this region II of inverter VTC: V ¿=V ILMAX and dV 0

d V ¿=−1

And from design parameters: Lp=Ln=L

Substituting in (3),W n

Lk n ' (V ILMAX−V tn)=

W p

Lk p ' (2V 0−V ILMAX+V tp−V DD ) (4)

From design parameters: W P=2∗W n and V DD=3.8VAnd from CMOS 5B Datasheet,N-MOS:k n '=1.964∗10−4 and V tn=0.656 6 V P-MOS:k p '=4.874∗10−5 and V tp=−0.921 3 V

Substituting in (2),1.964∗10−4(V ¿¿ ILMAX−0.6566)=4∗4.874∗10−5¿¿−0.5∗V 0

2+(V ILMAX−6.67 )V 0−4.8V ILMAX+4.33=0 (5)

Substituting in (4),1.964∗10−4 (V ILMAX−0.656 6 )=2∗4.874∗10−5 (2V 0−V ILMAX−0.9213−3.8 )V 0=1.5∗V ILMAX+1.7 (6)

Back-substituting (6) in (5),V ILMAX=1.84 V

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COEN 451

Determination of V TH

P-MOS and N-MOS are both saturated. Thus, IDp=−I Dn leads to kn

2 (V gsn−V tn)2=k p

2 (V gsp−V tp)2 (7)

For P-MOS: V gsp=V ¿−V DDand V dsp=V 0−V DD

For N-MOS: V gsn=V ¿ and V dsn=V 0

Substituting in (7), and solving for V ¿,k n (V ¿−V tn )2=k p (V ¿−V DD−V tp)2 (8)k n [ (V ¿ )2−2∗V ¿V tn+(V tn )2 ]=k p (V ¿−V DD−V tp )2

Since (a+b+c )2=a2+b2+c2+2(ab+bc+ca)

V ¿(1+√ k p

kn)=V tn+√ k p

kn(V DD−V tp)

V ¿(1+√W p

Lpk p '

W n

Lnk n ' )=V tn+√

W p

Lpk p '

W n

Lnkn '

(V DD−V tp)

From design parameters: W P=2∗W n

V ¿(1+√ 2∗W n∗k p 'W n∗kn ' )=V tn+√ 2∗W n∗k p '

W n∗kn '(V DD−V tp)

V ¿(1+√ 2∗k p 'kn ' )=V tn+√ 2∗k p '

kn '(V DD−V tp)

In our case (region III of VTC), V TH is V ¿ as it is where V out=V ¿

Thus,

V TH=V tn+√ 2∗k p '

k n '(V DD−V tp)

1+√ 2∗k p 'kn '

(9)

N.A.

V TH=0.656 6+√ 2∗4.874∗10−5

1.964∗10−4 (3.8−0.921)

1+√ 2∗4.874∗10−5

1.964∗10−4

Finally, V TH=1.96V

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COEN 451

Determination of V IHMIN

P-MOS is saturated and N-MOS is in linear region. Thus, IDp=−I Dn leads tokn

2 [ 2 (V gsn−V tn)V dsn−V dsn2 ]= k p

2 (V gsp−V tp )2 (10)

For P-MOS: V gsp=V ¿−V DDand V dsp=V 0−V DD

For N-MOS: V gsn=V ¿ and V dsn=V 0

Substituting in (10),kn

2 [ 2 (V ¿−V tn )V 0−V 02 ]= k p

2 (V ¿−V DD−V tp )2 (11)kn2 [ (V ¿−V tn)

dV 0

d V ¿+V 0−V 0

dV 0

d V ¿]=k p (V ¿−V DD−V tp ) (12)

In this region IV of inverter VTC: V ¿=V IH MIN and dV 0

d V ¿=−1

Substituting in (12),k n (−V IHMIN+V tn+2V 0 )=k p (V ¿−V DD−V tp ) (13)

From design parameters: W P=2∗W n and V DD=3.8VAnd from CMOS 5B Datasheet,N-MOS:k n '=1.964∗10−4 and V tn=0.656 6 V P-MOS:k p '=4.874∗10−5 and V tp=−0.921 3 V

Substituting in (13),2 (−V IHMIN+0.656+2V 0 )=V IHMIN−2.9 −2V IH MIN+1.312+4V 0=V IHMIN−2.9 V 0=

3¿V IH MIN−4.2124

(14)

Substituting in (11),4 (V IH MIN−0.656 6 )V 0−2V 0

2= (V IH MIN−3.8+0.921 3 )2 4∗V IH MINV 0−2.626 4∗V 0−2¿V 0

2=(V IHMIN−2.878 7 )2 4∗V IH MINV 0−2.626 4∗V 0−2¿V 0

2=¿ V IHMIN2−5.757 4+8.286 9

4∗V IH MINV 0−2.626 4∗V 0−2¿V 02=¿ V IHMIN

2−2.529 5−2¿V 0

2+ (4∗V IHMIN−2.626 4 )V 0 −V IHMIN2+2.5295=0 (15)

Back-substituting (14) in (15),V IHMAX=2.16V

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COEN 451

Noise Margins High and Low

Noise Margin LowN M L=V ILMAX−V OLMAX =1.84 V

Noise Margin HighN MH=V IHMAX−V OH MIN=V DD−V OHMIN=3.8−2.16=1.64V

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COEN 451

APPENDIX : CMOSIS 5 SPICE Parameters

*CMOSIS5 Design Kit V2.1 for Cadence Analog Artist

*MOS3 models for use in spectre

#ifdef n5bo .MODEL CMOSN mos3 type=n +PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 +VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E –04 +UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976 +NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 ETA=3.7180E-02 +KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10 +CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11 +MJSW=0.521 PB=0.99 +XW=4.108E-07 +CAPMOD=bsim XQC=0.5 XPART=0.5 *Weff = Wdrawn - Delta_W*The suggested Delta_W is 4.1080E-07

.MODEL CMOSP mos3 type=p+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10MJSW=0.505 PB=0.99+XW=3.622E-07+CAPMOD=bsim XQC=0.5 XPART=0.5*Weff = Wdrawn –Delta_W*The suggested Delta_W is 3.220E-07#endif

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COEN 451

A CMOS inverter (INV1), with a physical layout shown in Fig.1, drives a similar inverter, and operates at a supply voltage of 3.3V.a. Determine the delay of the inverter INV1.b. What will be the maximum speed of operation of INV1 if it drives ten similar inverters?c. One of the methods to speed up the operation is to increase the size of the driver. Determine the W/Ls of the PMOS and the NMOS transistors of INV1 so that the speed in part (b) is doubled, assuming that the supply voltage has been reduced by 10%. (Hint: Use twice the diffusion capacitance of Fig.1).d. Determine the dynamic power dissipation of the inverter (INV1) for part c.Use CMC technology parameters CMOSIS5B

Fig. 1 Inverter for design

Maxime SCHNEIDER (ID: 6718809)Due date: October 22nd 2014

COEN 451 - Assignment 4

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COEN 451

a/ Delay of inverter ¿V 1

We have:

t p=t phl−t plh

2

t phl=AnC L

βnV DD

t plh=

A pCL

β pV DD

As a first step, we have to determine the Total Load Capacitance (CL), that is computed summing the Gate Capacitances, the Diffusion Capacitances and the Wire Capacitance:

CL=Cgn+Cgp+C dn+Cdp+Cw

Assumption: We ignore Cw, the capacitance of the wire.

Diffusion CapacitancesCd=C J∗Adrain+C JSW∗Pdrain

Area of the drain is Adrain=LDW D

Perimeter of drain is Pdrain=2 LD+2W D=2∗(LD+W D)Thus,

Cd=C J∗LD∗W D+2∗C JSW∗(LD+WD)N.A.For P-MOS, W dp=2.0μmand Ldp=3.0 μmCdp=9.35∗10−4 F m−2∗3.0∗10−6∗2.0∗10−6m2+2∗2.89∗10−10Fm−1 (3.0+2.0 )∗10−6m¿5.61∗10−16F+28.9∗10−16F¿5.61 fF+2.89 fF¿8.50 fF

For N-MOS, W dn=3.0μmand Ldn=2.5 μmCdn=5.62∗10−4 Fm−2∗2.5∗10−6∗3.0∗10−6m2+2∗5∗10−11Fm−1 (2.5+3.0 )∗10−6m¿42.15∗10−16 F+55∗10−17F¿4.215 fF+0.55 fF¿4.77 fFGate Capacitances

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COEN 451

Cg=Cox (W+ΔW )(L+δL)Assumption: We ignore ΔW n and δ Ln

As Cox=0.345

t (Angstrom )( fFm−2), we get:

Cg=0.345∗W∗L

tN.A.For P-MOS, W p=0.5μmand Lp=5.5 μm

Cgp=0.345∗0.5∗5.5

96 ¿9.87 fF

For N-MOS, W n=2.5μmand Ln=0.5 μm

Cgn=0.345∗2.5∗0.5

96 ¿4.49 fF

Total Load CapacitanceCL=C gn+Cgp+Cdn+C dp

N.A.CL=(8.50+4.77+9.87+4.49) fF¿27.63 fF

As a second step, we have to determine An and Ap coefficients. In most cases, it is done doing SPICE simulations. Another way to calculate t phl and t plhcan be done using the following formula for t phl:

t phl=CL

β p(V DD−|V tp|)¿

Knowing that β p=K p

' W p

Lp, we get:

t phl=LpCL

K p' W p(V DD−|V tp|)

¿

N.A.

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COEN 451

t phl=5.5∗10−6∗27.63∗10−15

4.8740∗10−5∗0.5∗10−6 (3.3−0.9213 ) [ 2∗0.92133.3−0.9213

+ ln( 4 (3.3−0.9213)3.3

−1)]¿ 151.965∗10−21

5.79689∗10−11 [0.77462+ ln (1.88327 ) ]

¿26.2149∗10−10∗[ 0.77462+0.633009 ]¿37 ps

And this formula for t plh:t plh=

CL

βn(V DD−|V tn|)¿

Knowing that βn=Kn

' W n

Ln, we get:

t plh=LnCL

Kn' W n(V DD−|V tn|)

¿

N.A.t plh=

0.5∗10−6∗23.63∗10−15

1.9647∗10−4∗2.5∗10−6∗(3.3−0.6566) [ 2∗0.65663.3−0.6566

+ ln( 4∗(3.3−0.6566)3.3

−1)]¿ 11.815∗10−21

12.98372∗10−10 [0.4968+ ln (2.2041 ) ]

¿0.90999∗10−11∗(0.4968+0.79032)¿1.8 ps

Finally, we can calculate t p that is given by:t p=

t phl−t plh2

N.A.t p=

37+1.82

¿ 38.82

¿19.4 ps

b/

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COEN 451

The maximum speed of operation is given by:f max=

1t r+t f

t r=KnCL

βnV DD

t f=K pCL

β pV DD

Since the circuits changes while using 10 inverters, CL changes: we now have to pass through 10 inverters and therefore Diffusion capacitances have to be taken into account ten times. This leads to:

CL' =C gn+Cgp+10∗C ' dn+10∗C ' dp

So,CL

' =C gn+Cgp+10∗(C ' dn+C 'dp )N.A.CL

' =[8.50+4.77+10∗(9.87+4.49)] fF¿156.87 fF

K n and K p are computed using the following formulas:Kn=

11−n (2(n−0.1)

1−n+ ln (19−20n )) where n= V tn

V DD

K p=1

1+ p ( 2(− p−0.1)1+ p

+ ln (19+20 p )) where p= V tp

V DD

N.A.For rising time,n=0.6566

3.3¿0.1986

K n=1

1−0.1986 ( 2(0.1986−0.1)1−0.1986

+ ln (19−20∗0.1986 ))¿1.2478∗(0.2461+ln (15.028 ) )¿3.6886

t r=156.87∗1O−15∗3.6886

980∗10−6∗3.3¿178.92 ps

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COEN 451

for falling time,p=−0.9213

3.3¿−0.2792

K p=1

1−0.2792 ( 2(0.2792−0.1)1−0.2792

+ln (19−20∗0.2792 ))¿1.3873 (0.4972+ln (13.416 ) )¿4.2918

t f=156.87∗1O−15∗4.2918

535.7∗10−6∗3.3¿380.84 ps

And finally,f max=

1t r+t f

¿ 1(178.92+380.84 )∗10−12

¿1.7864GHz

c/ The maximum speed of operation is given by:

f max=1

t r+t fHence, f 'max=2∗1.785GHz¿3.57GHz

τ min=t f+ tr ¿

CL βn

α (W n

Ln )K nV DD

+CL β p

α (W p

Lp )K pV DD

¿CL

α V DD ( βn

(W n

Ln)K n

+β p

(W p

Lp)K p )

α=CL

τminV DD ( βn

(W n

Ln)K n

+βp

(W p

Lp)K p )

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COEN 451

The new Load Capacitance isCL=2∗(8.5+4.76 )+143.6¿170.12 fF

Let’s calculate α.α= 170∗10−15

280∗10−12∗2.97 ( 3.75∗196∗10−6 +

4.311∗48.7∗10−6 )

¿ 170280∗2.97 ( 3.7

0.98+ 4.3

0.535 ) ¿ 170∗11.8

280∗2.97 ¿2.4

Finally, (WL )

n=2.4∗5

¿12

(WL )p=2.3∗11

¿26

d/ Dynamic Power Dissipation is given by:

P=f CLV DD2

N.A.P=170∗10−15∗2.972∗3.57∗109

¿3.35mW

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COEN 451

Appendix B: SPICE Parameters

.MODEL CMOSN mos3 type=n

+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 +VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E –04 +UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976 +NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 ETA=3.7180E-02 +KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10 +CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11 +MJSW=0.521 PB=0.99 +XW=4.108E-07 +CAPMOD=bsim XQC=0.5 XPART=0.5 *Weff = Wdrawn - Delta_W*The suggested Delta_W is 4.1080E-07

.MODEL CMOSP mos3 type=p

+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10MJSW=0.505 PB=0.99+XW=3.622E-07+CAPMOD=bsim XQC=0.5 XPART=0.5

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COEN 451

*Weff = Wdrawn –Delta_W

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COEN 451

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COEN 451

1. Design a 3 input CMOS static NAND gate for: a) Minimum area; b) Minimum propagation delay; c) Equal rise and fall time; d) Determine the worst-case rise and fall time if the NAND

gate is driving a 0.1 pF load.

2. Design a gate to implement the function F (A, B, C, D) = (AB + CD)’ in Pseudo NMOS. Analyze the circuit for valid operation at logic high and logic

Problem 1a/ 3 input CMOS NAND for minimum area.

Parameters of Minimum Area CMOS are:W p=W n=3 μm

Lp=Ln=3μm

Thus, for a 3 input CMOS NAND with minimum area, we have:

W pA=W nA=W pB=W nB=W pC=W nC=3 μmLpA=LnA=LpB=LnB=LpC=LnC=3 μm

b/ 3 input CMOS NAND for minimum propagation delay.

Maxime SCHNEIDER (ID: 6718809)Due date: November 5th 2014

COEN 451 - Assignment 5

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COEN 451

We have:W p=√μr∗W n=√ μn

μ pW n=√ 775

250W n=√3.1W n=1.7W n

Equivalent inverter 3 input NAND

Thus, for a 3 input CMOS NAND with minimum area, we have:W pA=W pB=W pC=W p=1.7Wmin=1.7∗3∗10−6=5.1 μmW nA=W nB=W nC=3Wmin=9μm

Length is kept unchanged:LpA=LnA=LpB=LnB=LpC=LnC=3 μm

c/ 3 input CMOS NAND for equal rise and fall times.

To get equal t r and t f we need to have equal β p and βn.We have:

W p=3W n

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COEN 451

Equivalent inverter 3 input NAND

Thus, for a 3 input CMOS NAND with equal rise and fall times, we have:W pA=W pB=W pC=3Wmin=9 μmW nA=W nB=W nC=3Wmin=9μm

Length is kept unchanged:LpA=LnA=LpB=LnB=LpC=LnC=3 μm

d/ Worst-case rise time and fall time with a 0.1 pF Load Capacitance.

Rise timeWorst-case rise time occurs when one input is LOW and the two others are HIGH, with top two NMOS at HIGH state. Thus, to study worst-case rise time, we have:

A B C OUT1 1 0 1

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COEN 451

We have:t r=2.2 τ charge

Assuming that - Cd=C s=C- W p=Lp=3 μm

τ charge=R p [3CdP+3CdN+2C sN+CL ] ¿Rp [8C+CL ] Rp=

1β p (|V GS−V t|)

¿ 1

K p' W p

Lp(|V GS−V t|)

¿ 112∗10−6∗4.2

¿19.8 kΩ

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COEN 451

Cd=C j∗Ad+C jsw∗Pd+CGSO∗W Assuming that Cd=40 fF,C=40 fF

Then, we have:t r=2.2 Rp [8C+CL ]¿2.2∗19.8∗103∗[8∗40∗10−15+0.1∗10−12 ]t r=18.3ns

Fall timeWorst-case fall time occurs when the three inputs are HIGH, leading to LOW output state. Thus, to study worst-case fall time, we have:

A B C OUT1 1 1 0

We have:t f=2.2 τdischarge

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COEN 451

Assuming that - Cd=C s=C- W n=Ln=3 μm

τ charge=3Rn [3CdP+3CdN+2C sN+CL ] ¿3 Rn [8C+CL ] Rn=

1β p (|V GS−V t|)

¿ 1

K p' W p

Lp(|V GS−V t|)

¿ 140∗10−6∗4.3

¿5.8k Ω

Cd=C j∗Ad+C jsw∗Pd+CGSO∗W Assuming that Cd=40 fF,C=40 fF

Then, we have:t r=2.2 Rmin [8C+CL ]¿2.2∗3∗5.8∗103∗[8∗40∗10−15+0.1∗10−12 ]t r=16.1ns

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COEN 451

Problem 2F(A, B, C, D) = (AB + CD)’

Pseudo NMOS circuit Equivalent inverter

Assuming:- V GS=5V- |V tp|=V tn=1V- we neglect V DSn

2

- Lp=Ln=3μm

PMOS is saturated: I p=βp

2 (V GSp−V tp )2

NMOS is linear: I n=βn (V GSn−V tn)V DSn−V DSn

2

2

I p=I n

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COEN 451

βp

2 (V GSp−V tp )2¿ βn (V GSn−V tn )V DSn−V DSn

2

2-

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COEN 451

As V DSn=V OL, we have, βp

2 (V GSp−V tp )2¿ βn (V GSn−V tn )V OL

βp

2(5−1 )2 ¿ βn (5−1 )V OL

16∗β p

2¿4∗βnV OL

V OL=2∗β p

βn

¿2∗K p '

W p

Lp

Kn 'W n

Ln

¿2∗K p

' W p

K n' W n

We have:K p

' =12∗10−6 K n

' =40∗10−6

Then, V OL=2 1240

W p

W n

V OL=0.6W p

W n

Assuming V OL=0.5V ,W p

W n=0.6

0.5 W p=0.83W n

Smallest Width is 3 μm. So we choose W p=3μm

And then W n=3

0.83=3.6μm

3.63

=1.2 W n=1.2W min

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COEN 451

Finally, we getW n=Wmin=3 μmW nA=W nB=W nC=W nD=2∗1.2W min=2∗3.6=7.2μm

Length is kept unchanged:LpA=LnA=LpB=LnB=LpC=LnC¿ LpD=LnD=3 μm

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COEN 451

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COEN 451

Use the following SPICE parameters for this assignment.

SPICE Transistor ParametersParameter NMOS PMOS Units Source Description

VTOKPGAMMAPHILAMBDARDRSCBDCBSISPBCGSOCGDOCGBORSHCJMJCJSWMJSWJSTOXNSUBNSSNFSTPGXJLDUOVMAX

0.740E-61.10.60.01(40)(40)

0.73.0E-103.0E-105.0E-10254.4E-100.54.0E-100.31.0E-55.0E-81.7E160016.0E-73.5E-77751.0E5

-0.812E-60.60.60.03(100)(100)

0.62.5E-102.5E-105.0E-10801.5E-40.64.0E-100.61.0E-55.0E-85.0E150015.0E-72.5E-72500.7E5

V(A/V2)(V0.5)V1/VohmsohmsFFAVF/mF/mF/mOhms/sq.(F/m2)-F/m-(A/m2)m(1/cm3)(1/cm2)(1/cm2)-mm(cm2/Vs)

(1)(5)(1)(3)(5)(2)(2)(2)(2)(2)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(3)(3)(3)(1)(1)(1)(1)

-zero bias threshold voltage-transconductance parameter-bulk threshold parameter-surface potential-channel-length modulation-drain ohmic resistance (w=6)-source ohmic resistance()-zero bias B-D juction cap.-zero bias B-S juction cap.-bulk junction sat.current-bulk junction potential;-G-S overlap capacitance-G-D overlap capacitance-G-bulk overlap capacitance-diffusion sheet resistance-zero bias bulk junction cap.-bulk junction grading coef.-bulk junction sidewall cap.-sidewall cap. Grading coef.-bulk jinction sat.current-oxide thickness-substrate doping-surface state density-fast surface state density-type of gate material-metallurgical junction depth-lateral diffusion-surface mobility-maximum drift velocity m/s

SPICE Level 3 ParametersParameter NMOS PMOS Units Source Description

THETAKAPPAETA

0.111.00.05

0.131.00.3

1/V--

(1)(1)(1)

-mobility modulation-saturation field factor-static feedback

Other Electrical ParametersCapacitance Edge Component Source

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COEN 451

(pF/m2) (pF/m)Gate (Cox)Metal1 – FieldMetal1 – PolyMetal1 – DiffusionPoly – FieldMetal2 – FieldMetal2 – DiffusionMetal2 – PolyMetal2 – Metal1Capacitor P + - Poly(0.1%/V linearity)

6.9E-42.7E-55.0E-55.0E-56.0E-51.4E-51.6E-52.0E-52.5E-56.9E-4

0.5E-40.4E-4

0.2E-42.0E-5

0.5E-4

(1)(1)(1)(1)(1)(4)(4)(4)(4)(*)(1)

Resistance (ohms/sq.) Source

N+ DiffusionP+ DiffusionN+ PolyCapacitor P+P-wellMetal1Metal23 3 metal1 – P + Diffusion Contact3 3 metal1 – N + Diffusion Contact3 3 metal1 – N + Poly Contact

2580183004K0.0350.0301214425

(1)(1)(5)(1)(1)(4)(4)(5)(5)(5)

Maximum operating voltage: 5 volts.

Sources: (1) D. Smith of NTE, presented at CMC Workshop June 6-7, 1985.

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COEN 451

1. The CMOS inverter shown in Figure 1a consists of two PMOS transistors connected in parallel and one NMOS transistor. All transistors (PMOS and NMOS) have the same dimensions with a layout shown in Figure 1b.(Note: the transistors are connected so that the output capacitance is minimized)

a. Determine the inverter’s switching voltage (Vx) and the supply current at Vo=Vx

b. Calculate the output capacitance.c. If the inverter is driving a load equivalent to10 similar inverters,

what will be the rise delay (tPLH)of the driving inverter?d. During the implementation of the circuit, one of the PMOS

transistors was accidentally disconnected, what will be the impact on the dc behavior of the circuit. In your analysis you need to address all critical parameters (VOH, VOL, VIH, VIL, Vx) and noise margin of the circuit. (Note: no calculations are required)

The transistors have the following parameters:NMOS: VTO=0.75V, Cox = 1.5fF/m2, Cjsw = 0.7fF/m, Cj=0.5fF/m2, n=500cm2/V-sec, =0. 0PMOS: VTO=-0.75V, Cox = 1.5fF/m2, Cjsw = 0.7fF/m, Cj=0.5fF/m2, p=250cm2/V-sec, =0. 0

Vin

Vin Vin

Vo

2.5

Diffusion

Diffusion

Diffusion

5V

0.5

0.5

(n+ or p+)

(n+ or p+)

0.5

0.5

Polysilicon

Fig. 12. An engineer wishes to submit the layout shown in Fig. 2 for fabrication using N-well three- layer metal process:

Maxime SCHNEIDER (ID: 6718809)Due date: November 19th 2014

COEN 451 - Assignment 6

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COEN 451

a. Draw the vertical cross section B-B’ showing all layers and material involved.b. List the sequence of steps up the formation of metal contacts

required to fabricate the PMOS transistor in the targeted technology. c. How many layers of metal appear in the layout of Fig. 2?d. The engineer made four layout errors. Identify these errors

Fig. 2

VDD

VSS

Active

Active+

N-well

Active

Metal 2

Metal 1

ActiveContact

Via

Poly

B’

B

P+ Layer

P+ Layer

N+ Layer

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COEN 451

Question 1a/ Inverter’s switching voltage is given by:

V x=√βrV tn+V tp+V DD

1+√βr

From the layout, − Ln=Lp=0.5μm − Two PMOS are in parallel so W p=2W n

W p=W 1+W 2

2=

[ (2.5−0.5 )+ (3−0.5 ) ]+[ (2.5−0.5−0.5 )+(3−0.5−0.5 ) ]2

=4.5+3.52

=4

then W p=8 μm and W n=4 μm

- βr=

W n

Ln

W p

Lp

μnμ p

=

40.54∗20.5

500250

=12∗2=1

N.A.V x=

√1∗0.75−0.75+52

=2.5V

Supply current at V 0=V x

At V x both NMOS and PMOS currents are opposite and in their saturation region. We have:

I dsn=βn

2 (V gsn−V tn)2=K p

' W n

Ln

2 (V gsn−V tn )2

i.e. we have:

I dsn=μnCoxn

W n

Ln

2 (V gsn−V tn )2

N.A.

I dsn=

500∗1.5∗10−15

10−84

0.52

(2.5−0.75 )2=525 μA

b/ Output capacitance is calculated as following:

Cout=2∗Cdp+Cdn

Assuming that Cdp=C dn

And knowing that Cd=Ad∗C j+Pd∗C jsw

We finally get:

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COEN 451

Cout=3∗(A ¿¿d∗C j+Pd∗C jsw)¿N.A.Cout=3∗(2.0∗1.5∗0.5+ (2+1.5 )∗2∗0.7 )=3∗6.4=19.2 fF

c/ If the inverter is driving a load equivalent to10 similar inverters, load capacitance would be:

CL=C out+10∗C¿

Since- C ¿=Cgn+Cgp and as Cgp=2∗Cgn we get C ¿=3∗Cgn

- Cout=19.2 fF from previous questionWe have:

CL=Cout+30∗Cgn

N.A.CL=19.2+30∗(0.5∗2+0.5∗2 )∗1.5=19.2+30∗3=109.2 fF

Rise delay is calculated as follows: t plh=

CL

βn(V DD−|V tn|)¿

N.AtPLH=

109.2∗10−15

500∗1.5∗10−15

10−84

0.5(2.5−0.75 )

[ 2∗0.752.5−0.75 +ln( 4∗(2.5−0.75 )

2.5 −1)] ¿ 109.2∗10−15

10500∗10−7 [ 1.51.75

+ln ( 72.5

+1)] ¿0.0104∗10−8 [0.8571+ ln (3.8)] ¿0.0104∗10−8∗2.1921 ¿0.0228∗10−8 ¿2.28ns

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COEN 451

Question 2a/The vertical cross section B-B’ is the following:

As a reminder, classical inverted is as follows:

b/Steps involved in the fabrication of a pMOS are:

1- Photolithography step to create N-well2- Photolithography step to create thin oxide3- Photolithography step to deposit Poly4- Photolithography step to diffuse P+ Silicon creating active area5- Photolithography step to deposit SiO26- Photolithography step to remove SiO2 where contacts are made

“open contact area”

c/There are two metal layers appearing in the layout of Fig. 2.

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COEN 451

d/Errors the engineer has made are:1- Via should be entirely on Metal 22- contact for nMOS bulk is missing3- Gate extension for P transistor is missing4- substrate connection to VDD should be n+

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COEN 451

For the following exercises use CMOSIS5 parameters given in the class. Use AS=AD=4; PD=PS= (2W=8). 2=0.6

Exercise 1 Determine the capacitance of a 1mm metal1 wire with width of 0.6. Determine the ratio of the fringing capacitance to the parallel plate capacitance. Using the same process parameters determine the same ratio if the width was reduced to 0.3

Excersie 2Determine the capacitance between 100 m length of metal_1 wire, width 4m and an equal dimension metal_2 wire placed directly above it.

Exercise 3Estimate the delay of metal_1 wire having length of 1000m and width of 2 a) Use distributed rc method.b) Use lumped RC methodc) Determine a relation between a & b above.

Exercise 4Estimate the minimum width of metal_1 wire that can supply 30 mA of current. How many vias are required to connect this metal wire to metal_2 wire? What is the resistance presented by the via? You may assume Jm = 05mA/µm2 , M_1 thickness is 0.5µm and metal_2 thickness is o.6µm. Assume each contact of 1um * 1um can carry 0.5mA safely or 0.1mA/um of periphery.

Exercise 5A buffer Wn = 2 and Wp=6 is driving 100 long wire of metal_2, 4µ wide. The metal_2 wire is feeding 8 Flip flops through 20 long metal_1 wire, width = 2µ. Each metal_1 wire is feeding gates of the flip flops through 10 long poly wire, 1µ wide. Each flip flop gate has 10 fFcapacitance. Use CMOSIS5B parameters if needed. a) Determine Cinterconnect, b) Determine the rise and fall times if the input pulse has tr=tf= 0.05ns

Maxime SCHNEIDER (ID: 6718809)Due date: November 26th 2014

COEN 451 - Assignment 7

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COEN 451

Assume k=3.4 and area of drain =3W and perimeter of drain is 2W+6

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COEN 451

Exercise 1

From the manual, CB0=0.0411 fFμm−2±0.0102 fF CP0=0.0177 fFμm−2±0.0044 fF

Since this is a single line, there is no line-to-line capacitance.Wire’s capacitance is the sum of Fringing capacitance and Parallel plate capacitance:

CW=CB+CP

Since CB=CB 0∗A CP=CP0∗P

We have:CW=CB0∗A+CP0∗P

N.A.CW=0.0411∗0.6∗1000+0.0177∗2∗(1000+0.6 )=24.66+8.8=33.46 fF

Ratio is calculated as follows:Ratio=

CP

CB

N.A.Ratio= 8.8

24.66=35.7 %

If width is reduced to 0.3m, new ratio isRatio '=

CP 'CB '

N.A.Rati o'= 0.0411∗0.3∗1000

0.0177∗2∗(1000+0.3 )= 12.33

35.5062=34,7 %

Conclusion: the thiner the wire, the lower the ratio.

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COEN 451

Exercise 2

From the manual, C Area−Bottom ¿0.0444 fFμm−2±0.0115 fF CFringe−Bottom=0.0189 fFμ m−2±0.0049 fF C Area−Top=0.0392 fFμm−2±0.0092 fF CFringe−Top=0.0169 fFμm−2±0.0042 fF CLine=0.0527 fFμm−2±0.0069 fF

Capacitance between the two metals is:CTotal=Cbotd+C topd

+2∗(Cbotp+C topp+Cline )

Since: Cbotd=A∗C Area−Bottom

C topd=A∗C Area−Top

Cbotp=P∗CFringe−Bottom

C topp=P∗CFringe−Top

C line=0We have:

CTotal=A∗(C¿¿ Area−Bottom+C Area−Top)+2∗P∗(CFringe−Bottom+CFringe−Top)¿

N.A.CTotal=4∗100∗(0.0444+0.0392 )+2∗208∗(0.0189+0.0169 )=53.60 fF

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COEN 451

Exercise 3

From CMOSIS5 parameters, C Area=0.0411 fFμm−2 CFringing=0.0177 fFμm−1 Rmetal1

=0.06 Ω /¿□

Since the wire is 1000 m long and 2m large, one square is 2 x 2m N=1000

2=500 □

r=0.06Ω /□ c=C Area∗Asquare=0.0411∗22=0.2 fF /□

a/Distributed RC method Formula is

t ddistributed=r∗c∗N∗(N−1)

2N.A.t ddistributed

=0.06∗0.2∗10−15∗50∗492

=14.7∗10−15=1.47 ps

b/ Lumped RC method Formula is:

t dlumped=RC

Since R=N∗r C=A∗CArea+P∗CFringing

We have:t dlumped

=N∗r ( A∗C Area+P∗CFringing )N.A.t dlumped

=500∗0.06∗(1000∗2∗0.0411+2008∗0.0177 )=3.53 ps

c/ We have:t ddistributed

=1.47 ps t dlumped

=3.53 ps

So, the ratio between these two values is:td distributed

td lumped

=1.473.53

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COEN 451

Then, t dlumped=2.40∗t d distributed

Exercise 4

We have A=0.5∗W

However Imax=Jm∗A A=ImaxJm

Then,W=

2∗ImaxJm

N.A.W=2∗30

0.5=120 μm

Furthermore, since each contact can carry 0.5mA, we need at least 300.5

=¿60 contacts of 1μm x1μm.

With 60 contact with a sheet resistance of 1.5Ω for contact, we have 1.560

=0.025Ω

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COEN 451

Exercise 5

a/Interconnect Capacitances are the following:Metal 1L=100mW= 4mCBottom=¿ 0.0152 fFμ m−2

CFringing=¿ 0.0072 fFμ m−2

Cb=¿ 100∗4∗0.0152=6.08 fFC f=¿ 2∗(100+4 )∗0.0152=3.16 fF Cmetal1=6.08+3.16=¿9.24 𝑓𝐹Metal 2L=8∗20=160mW=2mCBottom=¿ 0.0411 fFμm−2

CFringing=¿ 0.0177 fFμm−2

Cb=¿ 160∗2∗0.0411=13.15 fFC f=¿ 2∗(160+2 )∗0.0177=5.73 fF Cmetal2=13.15+5.73=¿18.88 𝑓𝐹

PolyL=8∗10=80mW= 1mCBottom=¿ 0.104 fFμm−2

CFringing=¿ 0.03 fFμm−2

Cb=¿ 80∗1∗0.104=8.32 fFC f=¿ 2∗(80+1 )∗0.03=4.86 fF CPoly=8.32+4.86=13.18 fF

GatesCgates=8∗10=80 fF

b/ Load Capacitance is:

CL=Cdn+Cdp+Cw

Since: Cdn=C jn∗An+C jswn∗Pn Cdp=C jp∗Ap+C jswp∗Pp Cw=Cmetal1+Cmetal2+CPoly+CGates

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COEN 451

We have:CL=C jn∗An+C jswn∗Pn+C jp∗A p+C jswp∗Pp+Cmetal1+Cmetal2

+CPoly+CGates

From the manual, C jn=5.62∗10−4 Fμm−2

C jp=9.35∗10−4Fμm−2

C jswn=5∗10−11 Fμm−1

C jswp=2.89∗10−11Fμm−1

N.A.CL=5.62∗10−4∗3∗2+5∗10−11∗2∗(3+2 )+9.35∗10−4∗3∗6+2.89∗10−11∗2∗(3+6 )+9.24+18.88+13.18+80 ¿3.37+6+16.83+5.2+9.24+18.88+13.18+80=152.7 fF

Rise time Formula is:t r=

K CL

β pV DD

Since β p=kP 'W p

Lp

We have:t r=

KC L

k P 'W p

LpV DD

From the manual, k P

' =48.7 μAV−2

K=3.4

N.A.t r=

3.4∗152.7∗10−15

48.7∗10−6∗60.5

∗3.3= 519.18

1928.5210−9=0.269ns

Fall time Formula is:t f=

KC L

βnV DD

Since βn=kn 'W n

Ln

We have:t f=

KC L

kn 'W n

LnV DD

From the manual,

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COEN 451

k n' =196 μAV−2

K=3.4

N.A.t f=

3.4∗152.7∗10−15

196∗10−6∗20.5

∗3.3=519.18

2587.2∗10−9=0.201ns

For rise time and fall time:t dr=t drstep+

t i/ pfall

6(1−2 p)

t df=t drstep+t i/ prise

6(1−2n)

Since: p=

V tp

V DD

n=V tn

V DD

t dr=t r2

t df=t f2

t d=

t dr+t df2

=

t r2+t f2

2

We have:

t dr=

t r2

+t f2

2+t f6(1−2

V tp

V DD)

t df=

t r2

+t f2

2+tr6

(1−2V tn

V DD)

N.A.

t dr=

0.2692

+ 0.2012

2+ 0.201

6 (1−2∗0.6563.3 )=0.1176+0.0335∗0.6024=0.1378ns

t df=

0.2692

+ 0.2012

2+ 0.269

6 (1−2∗0.9213.3 )=0.1176+0.0448∗0.4418=0.1374 ns

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COEN 451


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