Project coordination:Robert Bosch GmbH
Peter Joresfon +49 7121 35-2982
email [email protected]
Project management:edacentrum GmbH
Ralf Poppfon +49 511 762-19697
email [email protected]
Runtime: 06/01/2006 – 05/31/2009Homepage: www.edacentrum.de/verona/
Verification
of Analog Circuits
The VeronA project (01 M 3079 ) is supported in
accordance with the BMBF "Nanoelectronics“
sponsorship scheme within the scope of the
Ekompass sponsorship complex of the Federal
Ministry of Education and Research (BMBF).
Verification of Analog Circuits- Project Overview -
• Motivation• Up to 70 % of the design time is taken by verification issues
• Verification of analog signals (continuous in time and value) is very time consuming
• Goal• Development of basic elements of an integrated methodology for verification of analog circuits
• To verify the applicability of the methods for an industrial assignment
• Scientific and technical goals
• Development of methods and rules for the creation of models which can be simulated quickly and also sufficiently describe many physical effects (e.g. mixed discipline or temperature).
• Investigation and development of formal verification methods for analog circuits, i.e. model checking + equivalence checking.
• Development of methods for assertion-based verification, and of formal procedures for performance and tolerance verification.
• Implementation of an integrated methodology for multilevel verification of analog systems considering mixed-signal/ mixed-domain aspects and using the aforementioned points.
• Expected economical benefit• Increase the verification efficiency by minimum 30 %
• Reduce the number of redesigns by 20 %
• Improve the product quality
WP 3Multi levelverification
Specification
Implementation
Verification
Manufacturing and Test
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WP 2Formalizedverification
WP 1Verification oriented
modeling
Multi level verification
• Development of efficient task and application specific verification strategies on block level and for complete ICs� As possible a complete verification
coverage
Application-oriented verification of complete ICs
• Development of methods to accelerate the verification on system level by co-simulation
- Consideration of different abstraction levels
- Application of different languages/
simulators - Mapping of analog circuit parts in
programmable hardware and coupling of this hardware with AMS simulators
System levelco-simulation
• Development of methods for functional circuit
test across all abstraction levels• Consideration of process and operational
tolerances on different abstraction levels
Application of models across abstraction levels
Formalized verification
• Development of an efficient assertion-based
verification methods for error recognition and
localization in analog circuits and systems• Development of a formal method for
simulation based determination of a valid workspace on block level� Inclusion of process fluctuation
in the verification
Simulation based methods
• Investigation and development of equivalence checking algorithms for two
analog circuits and models respectively• Definition of requirements for behavioral
modeling
Equivalence checking
• Investigation and development of
model checking algorithms for analog
circuits• Development of a suitable specification
language for analog circuits
Model checking
Verification oriented
modeling
• Determination of the behavior of power transistors at very high temperatures (300°C)
• Adoption of the transistor model for the
verification at very high temperatures
Verification oriented modeling
for very high temperatures
• Examination of modeling approaches and simulation algorithms� Reduction of simulation time by
optimized behavioral models with sufficient accuracy
Simulation performance
