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VLSI DESIGN ,TEST ANDMANUFACTURABILITY
4/12/161Kalasalinga A!a"#$ %& R#s#a'!( an"E")!a*i%n
KALASALINGAM UNIVERSITY- TESSOLVE
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VLSI Design, Test & Manufacturai!it" #!$%Behavioural
Description
BehavioralDFT
Synthesis
RTLDescription
Logic
DFT
Synthesis
Gate Des cription
Test Pattern
Generation
Fault
Coverage?
Manufacturing
Good Product
Test pplication
Product
TechnologyMapping
Layout
Para!eter
"#traction
Gate
Li$raries
Li$raries
lo% high
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Introduction
&ntegrated Circuits '&Cs( havegro%n in si)e and co!ple#ity
since the late *+,-.sS!all Scale &ntegration 'SS&(
Mediu! Scale &ntegration 'MS&(
Large Scale &ntegration 'LS&(
/ery Large Scale &ntegration '/LS&(
Moore’s Law0 scale of &Cs
dou$les every *1 !onths
Gro%ing si)e and co!ple#ity poses!any and ne% testing challenges
VLSI
LSI M
S
I
SS
I
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I'$rtance $f Testing
Moore.s La% results fro! decreasing feature si)e'di!ensions(
fro! *-s of µ! to *-s of n! for transistors and
interconnecting %ires
2perating fre3uencies have increased fro! *--45) toseveral G5)
Decreasing feature si)e increases pro$a$ility of defects
during !anufacturing process
single faulty transistor or %ire results in faulty &CTesting re3uired to guarantee fault6free products
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(asic )$nce't $f Testing
Re!ate* fie!*s
Verificati$n+ T$ erif" te c$rrectness $f a *esign
Diagn$sis+ T$ te!! te fau!t" site.
Re!iai!it"+ T$ te!! %eter a g$$* s"ste %i!! %$r/c$rrect!" $r n$t after s$e tie.
Deug+ T$ fin* te fau!t" site an* tr" t$ e!iinate te fau!t.
VDD
0/
1
0 00
00
Testing+ T$ te!! %eter a circuit is g$$* $r a*
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Why Testing?
E!%n%i!s-R#")!# *#s* !%s* .#n(an!# '%0*A)*%a*i! *#s* #)i#n* .ATE is #3*'##l$
#3#nsi#
S(%'*#n *i#5*%5a'#*Ma'#* "%ina*ing %' s(a'ing
G)a'an*## IC )ali*$ an" '#lia7ili*$
D#!*s "#*#!*#" in C%s*8a' 9:91 ; 9:1
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0rinci'!e $f Testing
Testing typically consists of
pplying set of test sti!uli 'input patterns7 test vectors( toinputs of circuit under test 'C8T(7 andnaly)ing output responses
Te 1ua!it" $f te teste* circuits %i!! *e'en* u'$n tet$r$ugness $f te test ect$rs
Ci'!)i*
)n"#' T#s*.CUT
51911
11599595159155995191
15991
99115511911991591511
C%a'a*%'S*%'#"
C%''#!*R#s%ns#
T#s* R#s)l*
In)*
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T"'es $f Testing
/erification testing7 characteri)ation testing/erifies correctness of design and correctness of test procedureMay re3uire correction of either or $oth
Manufacturing testingFactory testing of all !anufactured chips for para!etric
and logic faults7 and analog specificationsBurn6in or stress testing
cceptance testing 'inco!ing inspection(8ser 'custo!er( tests purchased parts to ensure 3uality
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2$% t$ *$ testing
• )ircuit $*e!ing• #au!t $*e!ing
• L$gic siu!ati$n• #au!t siu!ati$n• Test generati$n
•Design f$r test• (ui!t-in se!f test
• S"ntesis f$r testai!it"
M$*e!ing
Aut$atic Test 0atternGenerat$r3AT0G4
Testa!e *esign
#r$ *esigner5s '$int $f ie%+
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6afer Yie!* 3)i' Yie!*, Yie!*4
a' $i#l" 12/22 9: 8a' $i#l" 1=/22 9:=
8a'
D#!*s
G%%" C(i
Fa)l*$ C(i
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Testing an* 7ua!it"
9uality of shipped parts is a function of yield : and
the test 'fault( coverage T
Defect level 'DL7 re;ect rate in te#t$oo
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6afer Testing
6afer testing is a step perfor!ed during se!iconductor device
fa$rication= The %afer testing is perfor!ed $y a piece of test e3uip!ent called a
%afer pro$er= The process of %afer testing can $e referred to in several
%ays0 >afer Final Test '>FT(7 "lectronic Die Sort '"DS( and Circuit
Pro$e 'CP( are pro$a$ly the !ost co!!on=
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&n6line Para!etric Test 'a="T( &n6line test structure
&n6line test type
&n6line test data e#plain
&n6line test e3uip!ent
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0r$e Testing
6afer 'r$es+ Most !anufacturers provide %afers already pro$ed to a set of DC para!eters at roo! te!perature to ensure they !eet a $asic su$set of the pac
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Die Testing
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ASSEMBLY AND
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Ka!asa!inga Uniersit"3KLU4- Tess$!e
4/12/16
Kalasalinga A!a"#$ %& R#s#a'!( an"
E")!a*i%n1@
M.Tec. VLSI Design, Testing & Manufacturai!it"3VDTM4
• & && Se!ester 4L8
• &&& Se!ester0 First 5alf6 4L8 Second 5alf6 Tessolve
• &/ Se!ester Tessolve
2n successful co!pletion of all the se!esters7 Tessolve
%ill recruit candidates $ased on acade!ic perfor!ance and
perfor!ance in the TechnicalEPersonal intervie%=
• Candidates with valid GATE score- Given preference towards Admission
• While studying the programme !tipend will "e provided for the meritious students
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UERIES
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T(an $%)
KALASALINGAMUNIVERSITY
KALASALINGAM UNIV!SIT" TSS#LV SMI$#NDU$T#!%VT<D
4/12/1621
Kalasalinga A!a"#$ %& R#s#a'!( an"
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