dqsb chirashi05 omote mkol - …cache. dqsb_chirashi05_omote_mkol created date: 3/5/2018 6:32:11 pm

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Page 1: DQSB CHIRASHI05 omote mkol - …cache. DQSB_CHIRASHI05_omote_mkol Created Date: 3/5/2018 6:32:11 PM

SHARC+ Dual-Core DSP with ARM Cortex-A5 - Mixed-signal and ... · 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache ... members

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