Paper Title (use style: paper title)

Identification Of Optimal SVPWM Technique For MLI Fed Induction Motor Drive

Chobris C Benny, ManuThomas, Chitra ASchool of Electrical Engineering, VIT University, Vellore-632014

Abstract The increasing need for high power and distortion less operation of industrial motor drives require the use of higher level multilevel inverters (MLI) with effective modulation techniques for controlling the inverter switching. This demands MLI topologies with reduced number of switches and highly effective SVPWM techniques. This paper identifies a Carrier based SVPWM (CBSVPWM) for switching a seven level reduced switch multilevel inverter. This technique possesses all the inherent qualities of the conventional SVPWM techniques and implementation easiness of the carrier based PWM technique. The proposed technique has been simulated in MATLAB/SIMULINK and results were validated.

Keywordsreduced swich MLI, carrier based SVPWM, common mode voltage, triplen harmonic injection

I. Introduction Nowadays industries are looking for high power AC drives to control the speed and torque of industrial motors. With the advent of power electronic converter the speed and torque control of induction motors are easier than never before. Conventionally the control of induction machines are carried out by two level inverters. But there is a call for high performance and highly reliable motor drive circuits. Multilevel inverters have inherent advantages of high voltage handling and good harmonic rejection capabilities than conventionally used two level inverters. As the levels goes on increasing the voltage handling capability and power rating increases. These are achieved at the cost of increased number of switches and thereby increased switching losses. The commonly used MLI topologies are diode clamped, flying capacitor, cascaded H-bridge inverters. There are many derived topologies like modular multilevel inverters, hybrid inverter, Generalized P2-Cell multilevel inverter and so on.[1-2] The paper examines a Reduced Switch Multilevel Inverter topology capable of producing a seven level voltage output.

There are various modulation techniques to achieve the switching sequence for controlling the multilevel inverters. Most widely used are the PWM techniques and their variants. There is an increasing trend of using Space Vector Pulse Width Modulation (SVPWM) technique because of their easier digital realization. Moreover it can obtain higher output voltage for the same DC bus voltage, lower switching losses and better harmonic reduction when compared to other PWM techniques.[3-6] SVPWM techniques includes:a) Sector selection based space Vector Modulation.b) Reduced switching Space Vector Modulationc) Carrier based Space Vector Modulationd) Reduced switching carrier based Space Vector ModulationAny balanced three-phase voltage reference signal can be represented by a rotating space vector , whose tip gives the voltage magnitude for a particular time instant. A conventional SVPWM technique uses the nearest three states (nodes of the triangle containing the vector) to approximate the desired voltage vector. During each switching period, the triangle is traversed back and forth once. The switching sequence and dwell times in each state are determined using volt-seconds comparison produced by switching state vectors equal to that of the reference vector [2]. For higher level MLIs this computation is complex and associates approximation errors.This paper focuses on a Carrier based SVPWM technique to run a reduced switched multilevel inverter which can be effectively implemented as an induction motor drive control circuit. This proposed scheme combines all the qualities of SVPWM along with the simplicity in the implementation level.

proposed seven level mli topologyThe total number of switches in a MLI is a major concern when going for higher orders and power ratings. Reducing the number of switches in turn reduces the complexity of control circuits as well as switching losses. The other factors of concern are the reliability and cost of the driving circuits. This paper proposes a compact MLI topology to achieve a seven level output with reduced number of switches. The reduced MLI topology has only five switches viz. Sw1, Sw2, Sw3, Sw4 and Sw5 where two switches are bidirectional. Here Sw2 and Sw3 are bidirectional as shown in fig. 1 Let n total number of voltage steps in the inverter output.Maximum output voltage Vo=(n-1)Vdc. The various voltage levels are generated by the given switching sequence as in table 1.

TABLE 1 SWITCHING SEQUENCE FOR MLIVoltage LevelSwitchesVoltage LevelSwitches

3 VdcSW1 & SW5-3 VdcSW3 & SW4

2 VdcSW2 & SW5-2 VdcSW2 &SW4

1 VdcSW3 & SW5-1 VdcSW1 & SW4

0 VdcAll OFFAll OFFAll OFF

FIG. 1: MLI TOPOLOGY

Carrier based svpwm techniqueIn case of multi-level system, there are many output vectors and as the voltage level increases, the complexity of conventional SVPWM increases. Therefore, the Carrier based SVPWM(CSVPWM) with triangular intersection technique is necessary for multi-level applications. When we adopt the conventional Carrier based SVPWM for multi-level system, it shows good characteristics in linear modulation range.

Third Harmonic Injection technique injects a triplen harmonic voltage to the reference signal. But determination of third harmonic is difficult as the output inverter phase-voltage may abruptly change from cycle to cycle. Hence, it is difficult to add specific third harmonic voltage[8]. So, for the electric drives applications third harmonic injection method may not be suitable. In proposed Carrier based SVPWM method a a common mode voltage is added to the reference phase voltage. This common mode voltage has an inherent third harmonic effect. There wont be any difficulties arising here as the calculation of Common mode offset voltage is done based on the switching states of the inverter, hence it can be updated in every computational cycle.

Implementation of csvpwm techniqueThe section explains the steps to generate modulating signals for all the three phases (a,b,c). These reference phase voltages are obtained from the reference voltage vector Vd and Vq of the stationary reference frame d-q axis. The imaginary phase voltages have the information of line-to-line voltages as being seen by the load. The reference modulating signal, , for all the three phases are produced by adding a corresponding common mode offset voltage to three individual reference phases.This will centralize the space-vectors in the corresponding switching periods and thereby match the carrier modulation to get optimized space vector modulation. The centralized space-vector modulation thereby injects a particular common-mode harmonic function into the reference three phase voltages [2]. This is obtained by:

where is 1 p.u. The modulated phase voltage is obtained by adding .

For an n-level Carrier based SVPWM, [n-1] carriers are required. The carriers have the same frequency and magnitude to occupy the continuous band. The sampled space vector is used to generate the switching pulses for the corresponding switches of the MLI.

simulation resultsSimulation has been carried out for the proposed CSVPWM and Multi-Carrier PWM (MC-PWM) with an open-loop control scheme. Simulation is done in MATLAB/SIMULINK platform. The tables 3 and 4 shows the performance analysis and effect of switching frequencies for CBSVPWM and CB-PWM modulation strategies respectively. THD analysis is given in figure 2. The corresponding voltage and current waveforms are given as figures 3, 4 and 5. TABLE 2: SIMULATION PARAMETERS

ParameterValue

Max. DC link voltage 400V

Common mode voltage level100%

Switching Frequency1 KHz

PWM TechniqueCSPWM/MC-PWM

Modulation Index0 to 1

TABLE 3: PERFORMANCE ANALYSIS WITH TWO MODUTATION STRATEGIES

TABLE 4: EFFECT OF FC ON THE TWO MODULATION STRATEGIES

FIG. 2: THD ANALYSIS FOR OUTPUT PHASE VOLTAGE Va

FIG 3: CURRENT WAVEFORM FOR R-L LOAD FOR 1 KHz [CBSVPWM]

FIG 4:OUTPUT VOLTAGE WAVEFORM FOR R-L LOAD (1 KHz) [CBSVPWM]

FIG 5: OUTPUT THREE PHASE VOLTAGE WAVEFORM FOR R-load (1 KHz) [MC-PWM]

conclusionsHighly efficient and easy to implement carrier based SVPWM technique is simulated and compared with the conventional multicarrier SVPWM technique for a reduced switch seven level MLI topology. The result shows that the DC bus utilization factor has increased with reduced number of switching. The THD has also reduced comparably. The best case is produced at a unity power factor and a modulation index (M=1). The results shows that the better harmonic performance of proposed PWM strategy compared to itsCBSVM exists in the entire range of the modulation index..

References

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[9] Jesmin. F. Khan, Sharif M.A Bhuiyan, Kazi. M. Rahman, Gregory .V. Murphy, Space vetor PWM for a two phase VSI, Science direct, Electrical power and energy system, 51 (2013) 265-277. [10] Shieheng Zheng, Taotao Cui, Mu-Tian Cheng, Long Chen, Research on variable frequency with three level topology and SVPWM control, IEEE conference paper June 2012,978-1-4577-2088-8/11[11] C.Bharatiraja, Dr.S.Jeevananthan, R. Latha, Dr. S.S. Dash, A Space vector pulse width modulation approach for DC link voltage balancing in diode clamped multilevel inverter, Science direct AASRI Procedia 3- 2012,133-140

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