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MOTOROLA.COM/SEMICONDUCTORS

M68HC08Microcontrollers

DRM040/DRev. 0, 4/2003

Designer ReferenceManual

Single Phase DigitalPower MeterReference Design

DRM040 — Rev 0 Designer Reference Manual

MOTOROLA 3

Single Phase Digital Power MeterReference DesignDesigner Reference Manual — Rev 0

by: Alan Devine Motorola Ltd East Kilbride

and Prof. Dr. Omer Cerid Istanbul

Designer Reference Manual DRM040 — Rev 0

4 MOTOROLA


MOTOROLA List of Paragraphs 5

Designer Reference Manual — DRM040

List of Paragraphs

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Section 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Section 2. Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Section 3. Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Section 4. Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Section 5. Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

List of Paragraphs


6 List of Paragraphs MOTOROLA


MOTOROLA Table of Contents 7


Table of Contents

Section 1. Introduction

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.2 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Section 2. Hardware

2.1 Main Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.2 Measurement transformers and shunt . . . . . . . . . . . . . . . . . . .21

2.3 Baseline (Vrefh/2) and Vrefh voltage generation . . . . . . . . . . .22

2.4 Supply transformer, rectifier-filter, voltage regulator. . . . . . . . .22

2.5 Power failure detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.6 SuperCap and Li-Ion Battery . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.7 Trimmable 32768 Hertz crystal oscillator . . . . . . . . . . . . . . . . .23

2.8 LCD display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.9 Serial communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.10 MON08 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Section 3. Software

3.1 Software Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Section 4. Results

Section 5. Conclusions

Appendix A — Schematics

Table of Contents


8 Table of Contents MOTOROLA

Appendix B — Calibration Coefficient

Appendix C — Mixing assembly and ‘C’ code

C.1 Generating Assembler Include files (Option -La) . . . . . . . . . . .65

C.2 Header file example:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

C.3 Calling functions and Variables . . . . . . . . . . . . . . . . . . . . . . . .66

Glossary


MOTOROLA List of Figures 9


List of Figures

Figure Title Page

1-1 AC input signals to A/D converter. . . . . . . . . . . . . . . . . . . . . . .121-2 Instantaneous power for in-phase voltage and current. . . . . . .131-3 Instantaneous power for current lagging voltage by 60º. . . . . .131-4 Current measuring circuit and attenuator . . . . . . . . . . . . . . . . .172-1 Power Meter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .193-1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273-2 Main Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293-3 Tim2_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313-4 smpy16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333-5 mpy16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343-6 meansq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353-7 Div48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373-8 Sdiv48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383-9 Disp_Result (Part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403-10 BINDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443-11 SwitchDecode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .463-12 Emulated EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .483-13 ProgEeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493-14 RTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523-15 Keyboard Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

List of Figures


10 List of Figures MOTOROLA


MOTOROLA Introduction 11


Section 1. Introduction

The accurate measurement of the electricity supply and subsequent billing to residential properties has traditionally been achieved through electro-mechanical meters. Although widely used this solution has several disadvantages including long-term accuracy, cost of calibration and limited communications. These issues can be overcome using digital power meters, where it is possible to achieve long term accuracy by removing analogue components which are prone to drift over temperature and time. Additionally, value added features for both consumer and supplier can be incorporated. These include multiple tariff rates that offer incentives to use electricity at off peak times and improved communications, which make meter reading less time consuming and more accurate.

1.1 Overview

This modular reference design is a low cost implementation of a single phase, digital power meter that uses a 68HC908LJ12 (LJ12) MCU, with on board 10-Bit ADC, to perform all measurements and power calculations. This technique known as 'software metrology' keeps the costs to a minimum, while still meeting the IEC61036, accuracy limits. A general introduction to power meter theory and, in particular a description of the measurement circuit and algorithm are discussed. A system level block diagram is described giving specific details of each hardware block. A detailed description of the software is provided to show that all metering features can be implemented in a small 8Bit MCU. Finally, the test results obtained are discussed to demonstrate the accuracy limits achievable with this specific implementation.

Introduction


12 Introduction MOTOROLA

1.2 Theory of Operation

The main objective of this project was to demonstrate that a low cost power meter could be implemented without the use of an external measurement device, by utilising the onchip 10bit A/D to perform the current and voltage measurements. The A/D converter on the LJ12 accepts input voltages in the range between Vrefl to Vrefh and since the A/D is unipolar, operating from a +5Vdc supply, Vrefl is limited to Vss and Vrefh is limited to Vdd.(+5V). Thus, the AC input signals of voltage and current have to shifted up and centered around 2,5 volts. This is achieved by biasing one end of the secondaries of the voltage and current transformers (See schematics in Appendix A for details). The resulting waveform is shown in Figure 1-1.

Figure 1-1. AC input signals to A/D converter

All six channels of the A/D converter are used and sampled at a rate of 32 x 50 = 1600 Hertz. This high rate is necessary to quantize up to the 15th harmonic of the 50 Hertz input signal. The oversampling of the AC inputs also increases accuracy since the quantization noise is reduced by the averaging process.

The active (real) power calculation is derived from the instantaneous power signal. Every 625 microseconds an input voltage, load current or one quarter load current are sampled by the A/D converter and multiplied to form an instantaneous power sample. The reconstructed power waveform for voltage and current is shown in Figure 1-2.

IntroductionTheory of Operation



Figure 1-2. Instantaneous power for in-phase voltage and current

This produces the maximum instantaneous power as the voltage and current are in phase, however, if the current lags the voltage, the resulting power is reduced. Figure 1-3 shows the example when current lags by 60º.

Figure 1-3. Instantaneous power for current lagging voltage by 60º

Mathematically the instantaneous power signal p(t) is the product of the voltage v(t) and current i(t).

t

Instantaneous Power Signal

Voltage & Current

p(t) = v(t ) × i(t)

Introduction



Where:

and

By substitution and trigonometric identity the resultant equation can be derived for instantaneous power:

Instantaneous Power:

The active (real) power is equal to the time integral (continuous summation of the individual voltage and current product terms) of this instantaneous power signal and since integration is similar to low-pass filtering or averaging, the active power can be described by the equation below, as the average value of the time varying quantity sin(2wt+ ) = 0. This active power equation is valid for all sinusoidal waveforms.

Active Power:

However, it should be noted that all voltage and especially current waveforms in practical applications will have some harmonic content. This active (real) power calculation also holds true for waveforms that contain harmonics, as explained below:

Using Fourier series expansion, instantaneous voltage and current waveforms can be expressed as follows:

where:

is the instantaneous voltage

is the average value or DC component

is the rms value of voltage harmonic h

is the phase angle of the voltage harmonic.

v(t) = Vsin(ωt) i(t) = I sin(ωt + θ)

( ))2sin(cos2

)( θωθ ++×= tIV

tp

θ

( )θcos2

)(IV

tp×=

v(t) = Vo + 2 × Vh × sin(hωt + αh)

h=1

∞

v(t)

V0

Vh

αh




where:

is the instantaneous current

is the average value or DC component

is the rms value of current harmonic h

is the phase angle of the current harmonic.

Using the above equations, the active power P can be expressed in terms of its fundamental (P1) and harmonic (PH) component.

where:

and

As can be seen from the above equation a harmonic active component is generated by every harmonic within the signal, as long as the harmonic is present in both voltage and current waveforms. As the active power calculation is valid for sinusoidal waveforms and since a distorted waveform is a summation of its sinusoidal Fourier components, the original active power calculation is valid.

i(t) = Io + 2 × Ih × sin(hωt + βh)

h=1

∞

i(t)

I0

Ih

βh

P = P1 + PH

P1 = V1 × I1 cos φ1

φ1 = α1 − β1

PH = Vh

h= 2

∞

× Ihcos(φh)

φh = αh − βh

Introduction



In software the instantaneous power is calculated by summing up each product of voltage and current for a total of 256 samples. After 256 samples the result is divided by a scaling coefficient, called the calibration coefficient. The coefficient is a scaling factor which also takes into account analog circuit tolerances. Its nominal value is 8114 (see Appendix B for an explanation).

The resulting represents the average energy over a 160 millisecond time interval. This value is added to the active tariff to calculate the accumulated energy and divided by 22500 to convert to watt-hours. See software section for detailed implementation.

1.2.1 ADC Range

In order to comply with the requirements imposed by the IEC 61036 standard, the current ranges must be measured within the defined error:

+-1%

+-1.5%

The 1,5% error in the lowest current range imposes a dynamic range of

which is between 12 and 13Bits. The A/D converter of the LJ12 has only a 10-bit resolution, but oversampling and averaging the instantaneous power over 8 cycles of the input signal, increases the effective resolution of the converter. To cover the additional current range from to two more bits are required. This is accomplished by attenuating the current signal by a factor of four before application to the A/D converter inputs as shown in Figure 1-4.

p(t) =

1calibration_coefficient

× Vnn =0

255

In

p(t)

0,05 In < In < 4In

0,02 In < In < 0,05In

n = 2 ×

1001, 5

×In

0,02 In

= 6666 ,66

In 4In




Figure 1-4. Current measuring circuit and attenuator

The Timer2 interrupt service routine runs A/D conversions every 625 microseconds. Current samples are taken from either the non-attenuated or attenuated A/D conversion according to a range selection byte called “attenflag”. These samples are also used to calculate the mean square current to determine whether the unattenuated or attenuated current should be used in the power calculation. The mean square current value obtained from 256 samples is compared against two limit values “hilimit” and “lolimit” to determine the operating range. The two values create hysteresis in the system that avoid range switching oscillations. A time delay between voltage and current samples adjustable by a value in memory “measdelay” is used to equalize the phase shift between voltage and current transformers.

Phase out to load

Phase in Shu

nt

Current Transformer

3000R%1

1000R%1

10R

R

CC

R

unattenuated current

current attenuated by 4

Vrefh/2 or baseline

LPF

Introduction




MOTOROLA Hardware 19


Section 2. Hardware

This section describes the power meter’s hardware. The block diagram of the hardware is shown below with detailed description of each block.

Figure 2-1. Power Meter Block Diagram

Phase out to load

Phase in

Neutral

Shu

nt

Current Transformer

Voltage Transformer

Current attenuator, low-pass filters,

1/2 Vrefh & Vrefh reference generator

Supply Transformer

Rectifier-Filter, Regulator, SuperCap,

Power Failure Detector, Li-Ion Battery Switcher

32768 Hertz

908LJ12

LCD display

Push buttons, MON08

interface, infrared comm.,

RS-232D interface

BattSel1

BattSel2

PowerFail

Vss

+5 Vdd

Current

Current/4

Voltage

Baseline

Vrefh

Vrefl

Vbatt1

Vbatt2

Hardware


20 Hardware MOTOROLA

2.1 Main Blocks

Signal acquisition and conditioning:

• Current transformer & Voltage transformer

• Current attenuator & low-pass filters for both currents and voltage signal

• Baseline (Vrefh/2) voltage generation

• Vrefh generation

Power supply and battery backup:

• Supply transformer, rectifier-filter, voltage regulator

• AC power failure detector

• Short term power backup by SuperCap

• Long term power backup by MCU controlled Li-Ion battery(ies)

MCU and all other I/O:

• Trimmable 32768 Hertz crystal oscillator

• LCD display

• Infrared communication (IEC 61107) interface

• RS-232D serial communication interface

• MON08 programming interface

HardwareMeasurement transformers and shunt



2.2 Measurement transformers and shunt

The rated current( ) equals 15 amperes. The current transformer used has a step down ratio of 2500 and a maximum primary current handling capacity of 100A. As seen from the circuit diagram the rms voltage is developed across two shunt resistors of 626 ohms in parallel to reduce self-heating. Together with the shunting 1/4 attenuator, the total shunt resistance is equal to:

Multiplying the secondary current at with the total shunt resistance the rms voltage across the total shunt resistance is obtained:

giving a peak value of

The peak-to-peak AC voltage signal is 4928 mV. This voltage has been designed to be slightly less than Vrefh as not to saturate the A/D converter. Similarly the voltage input has been designed, such that the voltage transformer delivers less than 5 volts peak-to-peak at the highest line voltage. The voltage transformer is a 270 volt input to 1750 mV output device. The voltage transformer has been designed to operate at a maximum magnetic induction of 0,5 Tesla to improve linearity. The peak voltage at the A/D is:

Giving a peak to peak value of 4850mV

In

Rshunt =

313 × 4010313 + 4010

=1255130

4323= 290, 33Ω

In

Vshunt =

In

2500× Rshunt =

152500

× 290, 33 = 1742mV

Vmax = 1742 × 2 = 2464mV

mVV 247521750max =×=

Hardware



2.3 Baseline (Vrefh/2) and Vrefh voltage generation

A precision reference of type TL431ACLP is used to generate the nominal 2495mV Vrefh/2 voltage for the baseline (AC voltage shifting) voltage. This voltage is scaled up by a factor of 2 using an MC33501SNT1 opamp. This opamp has been selected as it has a very low offset voltage, operates at low supply voltages and delivers high output current at output voltages close to the positive supply. To guarantee a precise step up by two, the feedback divider resistors (R6 and R7) have been selected such that they are equal in value. Their absolute value is not important. Vrefh obtained at the opamp’s output, supplies both the MCU’s Vrefh and Vdda pins. The opamp is supplied from +5,7 volts in order to guarantee an output of +4990 millivolts under loaded condition.

2.4 Supply transformer, rectifier-filter, voltage regulator

The supply transformers secondary voltage determines the lowest possible line voltage for correct operation. The given transformer operates down to a guaranteed 160 volts. The diode bootstrapped MC78L05 regulator delivers approximately 5,7 volts to supply the reference, the opamp and the RS-232D level shifter. The regulator output feeds the MCU over the diode D3 to reduce the voltage back to +5 volts, and to avoid backward supply of the regulator from the SuperCap or Li-Ion battery in case of power failure.

2.5 Power failure detector

The power failure detector is designed to detect the absence of full-wave sinusoids. If more that one half-cycle is missing, capacitor C2 can charge up over R17 sufficiently to turn on transistor Q2 to pull the IRQ pin of the MCU low. The power fail detection time can be changed by scaling the value of C2.

HardwareSuperCap and Li-Ion Battery



2.6 SuperCap and Li-Ion Battery

The SuperCap (0,47 farad) bridges short term power failures by supplying the MCU in stop mode until it is discharged to a level where the Li-Ion batteries will take over. Both the SuperCap and the Li-Ion batteries feed the MCU via low forward voltage drop schottky barrier diodes of type MBRM120E. The SuperCap is charged up by a current limiting resistor of 470 ohms. The two Li-Ion batteries can be selectively turned off by the MCU via the dual P-channel MOSFETs.

2.7 Trimmable 32768 Hertz crystal oscillator

The timebase of the MCU is a 32768 Hertz tuning fork type crystal. This crystal as in the case of a watch has to be trimmed precisely to 32768 Hertz for low time drift RTC operation over extended periods of time. Together with the trimmer capacitor C10 and the 100 kHz output waveform at Timer1 output pin, the frequency of oscillation can be trimmed. The 100 kHz signal is generated only in calibration mode.

2.8 LCD display

A 5 volt, four backplane LCD that provides the appropriate metering symbols has been used.

2.9 Serial communication

Serial communication can be selected via jumpers J5 and J6 to route the signals of the SCI either to the infrared LED & phototransistor to comply with the IEC 61107 standard, or via the built in RS-232D level shifter to the 9-pin D-Sub connector.

Hardware



2.10 MON08 interface

A MON08 interface has been provided to ease software development and in-circuit programming of the MCU. Note that a necessary addition to the MON08 interface has been made by routing the 4,9152 MHz clock signal from the LJ12 ICS to enable programming of the MCU. For this purpose jumper J1 has to be moved to bridge pin 1 with pin 2. Also power to the MCU has to be applied from the ICS by moving the bridge on jumper J3 to short pin 1 with pin 2. Under normal metering operation jumpers J1 and J3’s bridges should short pins 2 and 3.

Calibration mode is enabled when the MCU detects a high logic level on PTA0 coming out of reset. For this purpose a shorting bridge between pins 10 and 8 on the MON08 header J2 has to be installed.

NOTE: The ICS clock signal must be routed to the MON08 connector to allow programming. This is implemented by routing a wire from the clock signal of jumper J2 pin 2, to the MON08 header J12, pin 7.


MOTOROLA Software 25


Section 3. Software

This section describes the power meters application software. The meter can be operated in normal mode, which is conceptually split into 2 main sections: measurement algorithm and user interface or calibration mode where a 100Khz signal is output to allow trimming of the crystal. The source code comprises of both assembly and C code. The majority of the assembly code has been written for the measurement algorithm, mathematical functions and LCD display. The C code has been used for the main loop, Real Time Clock and the user interface. These modules are compiled separately and linked together using the Metrowerks tools. Refer to Appendix C for details of how to mix assembly and ‘C’ source code using Metrowerks code-warrior tools for HC08.

The measurement algorithm is the most critical section of code, as it performs the active power calculation as defined in Section 1.2, Theory of Operation. The instantaneous power is calculated by taking samples of the line voltage and load current and by multiplying them together. This power is integrated over time (continuous summation of individual voltage and current product terms) to calculate the active (real) power, which is effectively the average of the instantaneous power. Samples are taken every 625us (1600Hz), which corresponds to 32 samples per power cycle (50Hz). The majority of the calculation is performed in the timer2 interrupt service routine. See Tim2_ISR for details.

The second main code section is the user interface. This comprises of the LCD display, the Real Time Clock (RTC) and the Switch Interface. The LCD displays the energy for tariffs T1, T2, T3, T4 and the time and date at 5s intervals. The energy is a scaled version of the instantaneous power accumulated over time. The active tariff is determined from a simple routine that changes the tariff every 3 mins or at pre-determined days and times stored in EEPROM. The mode executed is determined at compile time with the inclusion or otherwise of the TARIFF_TEST_UPDATE macro. The switch interface consists of two

Software


26 Software MOTOROLA

push button switches. The first is the Display button which, when pressed, toggles the display to the next position in the predefined sequence. The display then remains active for 30secs with the new data before reverting back to the original sequence that toggles every 5secs. The second switch simulates opening the meter (tamper condition). When open, a warning flag is displayed on the LCD and a time stamp is calculated and stored in EEPROM. Additionally, a count is incremented each time the meter is open and the value is stored in EEPROM. See switch interface for additional details.

3.1 Software Routines

This section describes each function contained within the application code. A general description and flow diagram are provided for each routine.

3.1.1 Initialization

Individual routines are used to initialize the assembly and the ‘C’ code. Both initialization routines, Asm_init and C_Init, primarily initialize the variables and peripherals that are defined within the assembly and ‘C’ code respectively. However, C_Init is more complicated as it checks the reset source, and if POR or LVI are set, assumes the initial power up sequence (invalid RTC) as the backup batteries should prevent power loss during normal operation. The RTC is initialized with default values and the tariff switching times are stored in the Emulated EEPROM. If the reset source was not POR or LVI the routine copies the saved RTC registers (CopyRTC buffer) to the actual RTC modules registers. This is necessary on the MC68HC908LJ12 as the reset signal resets all RTC registers.

The last instruction within the function enables the global interrupt to allow interrupts to occur within the application. The initialization flow diagrams are shown in Figure 3-1.

SoftwareSoftware Routines



Figure 3-1. Initialization

Asm_Init

Return

CLRHCLRACLRX

Disable COPEnableLVI

Init PLLInit SCIInit ADCInit LCDInit TIM2

Clear Sum of Powers bufferClear Sum of Squares buffer

Clear attenFlag - LOWClear SymbolFlag - T1

Clear Display_buf

C_Init

Unprotect Flash

InitiliseCopyRTC_ptr = &CopyRTC

SecrReg_ptr=&SECRR

Initilise PortsPortD input

InitiliseKeyboard Interrupts (6&7)

Get Reset source and clearresets

POR || LVIreset

Write Default tariff switchingtimes to EEPROM

Set RTC registers to defaultvalues

Clear tariff buffers

Set T1 as active buffer

Copy Update RTC withcopy of RTC values

Latency=1s

Turn On RTCChronograph Off

Clock Divide for 32.768KHz

Clear Interrupt source andenable RTC interrupt

Enable Global InterruptsCLI

Initialise timestamp andwarning flag EEPROM page

return

Y

N

Software



3.1.2 main loop

The main routine is implemented in ‘C’ code. The function is called from the Start08 routine and immediately calls the assembly initialization code, Asm_Init(), and then the C initialization code, C_Init(). After execution of the initialization code the routine checks PTA0 and enters calibration mode if set to logic 1. In calibration mode Timer1 is set to output a 100KHz reference signal to enable the clock to be tuned with the trim cap mounted on the board. The code remains in calibration mode until PTA0 is reset to locic0. The code then enters an infinite loop and waits for a new sample to be completed (every 625us), which is indicated by the NEW_SAMPLE_FLAG set in the ApplicationFlags buffer. If all 256 samples are completed (8 cycles of mains input) the code scales the new instant power calculation before saving the value in InstantPower buffer. This power value is also added to the active tariff to calculate the accumulated power before the code checks if time or date is to be displayed and updates the Display_Buf with the latest real time clock information. Finally, the display result function is called to display the new data on the LCD and loops back and waits for the next sample. If the 256 samples were not complete the code checks the SwitchDecode function to see if any switches were pushed since last poll. The code then loops back to the start and waits for the next new sample. Figure 4.2 shows main loop flow diagram




Figure 3-2. Main Loop

Initialise Assembly codeAsm_Init()

Initialise 'C' codeC_Init()

main

256 samples complete?

Update TIME

Update DATE

Display result on LCDDisp_result()

Clear Display Buffer

Check switch StatusSwitchDecode()

ClearNEW_SAMPLE_FLAG

N

Y

Time data copied todisplay buffer

(i=3)

seiGet Binary TIME value

cli

Convert binary TIME data to 2nibbles and store in

display_buf[]

next buffer location(increment i)

Y

N

Date data copied todisplay buffer

(i=3)

seiGet Binary DATE value

cli

Convert binary DATE data to 2nibbles and store in

display_buf[]

next buffer location(increment i)

N

Y

Initialise Timer1 togenerate 100KHz

Set CAL_FLAGReset to active tariff 1

Clear Low Bytes of DivisorLoad scalefactor into High

Bytes of divisor

Scale resultSDiv48()

Accumulate appropriatetariff

add2tar()

new samplecomplete?

Clear Tariff Buffers

Copy instant power toInstPower Buffer

Enter calibration mode?PTA0=1

Y

Y

N

Y

N

Calibration mode disabled &&CAL_FLAG set

Disable Timer1Clear CAL_FLAG

N

Y

N

N

Y

ClearNEW_SAMPLE_FLAG

Software



3.1.3 Timer2 ISR

The Tim2_ISR service routine services the periodic interrupt generated by Timer2 overflow. A Timer2 overflow occurs every 2500 bus clock cycles which is equal to 1600 Hertz. This rate assures that 32 samples of voltage and current are taken for each complete period of the 50 Hertz sinewave power signal. A programmable delay between acquisition of line voltage and line currents compensates for the unequal phase shifts introduced by the voltage and current transformers. Each A/D conversion is stored in its associated memory locations. Additionally line voltage and current samples are subtracted from the “baseline” (one-half fullscale value) to obtain unshifted signed waveform samples. The current samples are squared and accumulated to form the mean squared value used for current range switching. The memory location “samplecount” is decremented by one during each pass through the interrupt service routine. When “samplecount” has been decremented from 256 to zero, eight complete sinewave cycles have been sampled, converted and added up to form the total real power contained in eight cycles. This sum of powers (instantaneous power) is prepared for scaling by the calibration coefficient using the signed 48-bit division routine “SDiv48”. The actual division is performed in the main loop. Finally, the accumulated mean square current value is compared against a high-limit “hilimit” and low-limit “lolimit” value in the “attenflag” register to determine the range setting. Tim2_ISR is shown in Figure 3-3.




Figure 3-3. Tim2_ISR

Timer2 interrupt

Y

A/D convert baseline & line voltages

A/D convert line current & current/4

A/D convert battery1 & 2 voltagesubtract line voltage

from baseline

attenflag = 0

subtract line current from baseline

subtract line current/4 from baseline

multiply by four

build meansquare of current

multiply line voltage and current

add product to previous ones

decrement samplecount

samplecount = 0

return from interrupt

Y

Ncopy instantaneous power to dividend

clear instantaneous power

compare meansquare agaist high limit

lower or same

compare meansquare agaist low limit

higher

set attenflag = 1

set attenflag = 0Y

Y

clear sum of squares

Delay proportional to measdelay

Software



3.1.4 smpy16

Subroutine “smpy16” multiplies two 16-bit signed numbers producing a 32-bit signed product. On entry the H:X register points to a 4-byte data array holding the multiplier and multiplicand. Subroutine “smpy16” checks for the signs of multiplier and multiplicand and after converting into positive numbers, calls subroutine “mpy16” which does the multiplication before the products sign is corrected. The product overwrites the multiplier and multiplicand. This routine is used to calculate the instantaneous power from the voltage and current samples obtained by the A/D converter and also to calculate the mean square value of the current for range switching. Figures 3-4 and 3-5 show the smpy16 and mpy16 flow diagrams.




Figure 3-4. smpy16

smpy16

clear sign flag

test sign of multiplier

negate multiplier

set sign flag = 1

Y

positive

test sign of multiplicant

Y

positive

call mpy16 unsigned multiply

negate multiplicant

flip sign flag

test sign flag

Y

zero

return

negate product (32-bit)

Software



Figure 3-5. mpy16

mpy16

save pointer H:X on stack

allocate 6 bytes on stack as work areapush multiplier & multiplicant onto

stack

disable interrupts if enabled

recall H:X from stack

return

multiply multiplier low with multiplicant low

save product on stack

multiply multilier low with multiplicant high

add products low byte to previous prod. high add possible carry to

high bytesave product on

stackmultiply multiplier high

with multiplicant lowadd products low byte to previous prod. high add possible carry to


stackmultiply multiplier high with multiplicant high

add products low byte to previous prod. high add possible carry to


stack

store 32-bit product over original multiplier

and multiplicant

restore original interrupt flag status

correct stack




3.1.5 Meansq

This Subroutine is used to calculate the mean squared current. The measured current is copied and multiplied with itself using the “smpy16” routine. The squared current value is then added to the previous squares to build up a mean value composed of 256 samples. Figure 3-6 shows meansq flow diagram.

Figure 3-6. meansq

3.1.6 Add2tar

Subroutine “add2tar” adds the scaled instantaneous power to the active tariff buffer and checks whether the value in the active tariff buffer (48-bit) fits into the 8-digit LCD display. If the result (in decimal) is greater than 99999999 it is made to rollover to 00000000. If the meter is recording power delivered to the utility, the display displays decrementing numbers and a rollover from all zero to all nines is performed.

meansq

copy temp_long+2 to rms_long (16-bit)copy temp_long+2

to rms_long+2 (16-bit)call smpy16

16x16 signed multiplyadd 32-bit result to previous squares

return

Software



3.1.7 Div48

Subroutine “Div48” is an unsigned 48-bit by 48-bit division routine. The 6-byte numerator (dividend) and the 6-byte denominator (divisor) are stored in 12 consecutive memory locations. This routine uses 21 bytes of stack, as all data and temporaries are placed on the stack. At exit, if the divisor was non-zero, the quotient replaces the dividend and the remainder replaces the divisor and the carry flag is cleared to indicate a successful division. Else the carry bit is set, and both dividend and divisor are not modified. This processing time of this routine is data dependent. Figure 3-7 shows Div48 flow diagram.




Figure 3-7. Div48

save H:X on stack

Yzero

Div48

allocate six bytes on stack and clear

push dividend & divisor onto stackpreset justification count to 1 & savelet H:X point to items on stackcheck divisor

(48-bit)

set carry to indicate error

flush stack

return

bit48 = 1

increment justify count

N

justify divisor (shift left)

Y

make trial subtraction dividend - divisor

carry = 0

divisor too large, restore dividend

clear carry bit set carry bit

adjust quotient (rotate left)

adjust divisor (shift right)decrement justify count

zeroN

clear carry bit to indicate no error

save remainder in place of divisor

save quotient in place of dividend

recall H:X

N

Y

Y

Software



3.1.8 SDiv48

Subroutine “SDiv48” divides a signed 48-bit number in the numerator by an unsigned 48-bit number in the denominator. This is done by checking first the most significant bit of the numerator and if set, negating the numerator before calling the unsigned division subroutine “Div48”. At return of subroutine “Div48” the quotient is negated again if the numerator was originally negative. The resulting sign of the remainder is ignored. This subroutine is used to scale the instantaneous power by the calibration coefficient and also to scale the content of the tariff buffer by 22500 before display. Figure 3-8 shows Sdiv48 flow diagram

Figure 3-8. Sdiv48

test sign of dividend

negate 48-bit dividendY

positive

call Div48 unsigned divide

return

SDiv48

call Div48 unsigned divide

negate 48-bit quotient




3.1.9 Disp_Result

Subroutine “Disp_Result” is used to display all data in decimal format acquired by the meter. This includes accumulated kWh in each tariff buffer, time and date information, battery status and tamper attempts. Subroutine “Disp_Result” displays the instantaneous power in Watts when the meter is in calibration mode. Flag bits in memory locations “ApplicationFlags” and “SymbolFlags” are used to control the data that is written to the Display_buf and displayed on the LCD. In calibration mode the instantaneous power is sent out via the on-chip SCI and RS-232 level shifter. Figure 3-9 shows Disp_Result flow diagram.

Software



Figure 3-9. Disp_Result (Part 1)

call clear_sym

Nzero

Disp_result

test attenflag

prepare an "H" to display

save in LDAT12

prepare an "L" to display

move instantaneous power to display

buffer

check for calibration mode in ApplFlags

clear to LDAT13 to clear "-"

check instantaneous powers sign

save in LDAT13

send out a "-" via SCI

Nbit4 = 0

Ynegative

prepare a "-" to display

clear LDAT10; tariff mode & kWh

clear tariff "T": bit4 of LDAT12

get tariff number from SymbolFlag

mask high bits and add a one

copy A to X and clear H

do LCD lookup

save tariff number in LDAT10

turn on "T" and "kWh" symbols

turn on "T" and "kWh" symbols

get tariff number, multiply by 6 and add

to tariff pointercopy data from tariff buffer to divide buffer

(48-bit)prepare divisor to

energy scaling coeff.

call Div48

copy scaled energy to display buffer

call BINDEC to convert hex data to

packed BCD

point to display buffer display_buffer

A

clear_sym

clear dots P1, P2, P3, P4 and P5

clear segments S1 & S2

clear m3 & kWh symbols

clear arrow symbol

clear "T1" and "T2" symbols

clear clock, com, dots P6 and P7 symbolsclear warning and battery symbols

return





clear H

save digits on stack

shift right by 4 to get most significant digitcheck for calibration

mode

Ybit4 = 0

lookup LCD segment and save in LDAT2

recall digits from stack and mask high

copy A to X

A

get most significant 2 decimal digits into X

copy X to A

make ASCII and send out via SCI

check for calibration mode

Y

bit4 = 0

copy X to A





mode

Y

bit4 = 0


get next significant 2 decimal digits into X

copy X to A



copy A to X


Y

bit4 = 0

copy X to A





mode

Y

bit4 = 0



copy A to X

get next significant 2 decimal digits into X

copy X to A



Ybit4 = 0

set bit4 of LDAT6 to lit up kWh point

B

Software




return




mode

Ybit4 = 0



copy A to X

get least significant 2 decimal digits into X

copy X to A



Ybit4 = 0

copy X to A



B

copy A to X


Ybit4 = 0

copy X to A



Y

bit4 = 0

load a carriage return and send out via SCI

Y

bit4 = 0

lit up clock symbol

lit up colons for minutes & seconds

check for time display mode in SymbolFlag

Y

bit5 = 0

lit up clock symbol

check for date display mode in SymbolFlag

lit up lower dots for months & years

Y

bit6 = 0

lit up warning symbol

check for warning mode in SymbolFlag

Y

bit7 = 0

lit up battery symbol

check for battery mode in SymbolFlag




3.1.10 BINDEC

Subroutine “BINDEC” converts a signed 32-bit binary number to packed BCD format. On entry the index register H:X has to point to the 32-bit binary data. At exit, memory locations pointed to H:X plus four up to and including H:X plus nine, contain the signed 10-digit BCD number in packed format. This subroutine is called by the LCD display routine “Disp_Result” to convert all binary data before display on the LCD. Figure 3-10 shows BINDEC flow diagram.

Software



Figure 3-10. BINDEC

clear sign flag

Ynegative

BINDEC

test sign of 32-bit input data

negate 32-bit input data

preset loop count to 32

return

clear result area (5 bytes)

zeroN

shift input data one bit to left

rotate result area one bit left

save loop count on stack

get LSB of result & call cvdec2save LSB of

resultget NSB of result &

call cvdec2save NSB of

resultget NSB of result &

call cvdec2save NSB of

resultget MSB of result &

call cvdec2save MSB of

result

recall loop counter and decrement

Y

cvdec2

save H:X on stack

copy A to X

mask high nibble

compare against 5

add 3 to X

copy X to A

Ynegative

mask low nibble

compare against $50

add $30 to X

Ynegative

copy X to A

restore H:X from stack

return




3.1.11 Switch Decode

The function is polled every new sample complete (625us) and checks the status of the Tamper key and the Display key. The key pressed results in an associated flag being set in the ApplicationFlags buffer. The flags are checked within the Switch Decode function to determine the source of interrupt. If the Tamper key was pressed and the key press signaled an open position (i.e. tamper condition) the open count is incremented and is stored in EEPROM with the timestamp. Alternatively, if the key press signaled a closed position the warning flag is switched off and the open duration is calculated and stored in EEPROM. Details of the EEPROM location used are described in Section 3.1.12, ProgEeprom.

If the DisplayKey was pressed the display sequence is toggled to show the next data in the sequence and the time that this information is displayed on the LCD is increased to 30Secs. After the 30seconds has elapsed the next data is displayed and the time reverts back to the original 5Secs.

Finally, the keyboard interrupts are re-enabled if the keyboard input is detected to be logic ‘1’. See Figure 3-11 for SwitchDecode flow diagram.

Software



Figure 3-11. SwitchDecode

SwitchDecode

TamperKey flag set?

Y

Get timestamp data fromEeprom

ProgEeprom()

Newstate = OPEN?

Increment open count

Copy timestamp data toEeprom Buffer

Set Warning Flagmake oldSwitchState =

OPEN

Y

N

SEIStore timestamp and count

back to EepromCLI

Clear tamper key flag

Calculate openduration

Clear Warning Flagmake oldSwitchState

= CLOSED

Display Keyflag set

Update Symbol flags count

Clear TimeCountSet LCD_UpdateTime = 30s

Indicate new LCD updateClear Display key flag

Is Tamper Key still low?

Is Display Key still low?

Enable Tamper keyinterrupt

Enable Display keyinterrupt

return

N

N

Y

N

Y

Y

N




3.1.12 ProgEeprom

The ProgEeprom function is used to write to and read from the emulated Eeprom. Eeprom emulation is achieved using the ROM resident EE_WRITE and EE_READ routines that are available on the LJ12 MCU. The function has been written in ‘C’ and uses the inline assembler to access the ROM resident routines. A summary of how the routines are used is described below. However, for further information refer to section 10.6 ROM Resident Routines the MC68HC908LJ12 data book.

FLASH memory differs from EEEPROM in the number of bytes that can be written or erased at a time. In true EEPROM, write and erase operations can be performed on a byte-by-byte basis. However, FLASH only allows page erase, which is 128 bytes on the LJ12. The EE_WRITE and EE_READ routines have been designed to emulate the properties of true EEPROM, thus allowing more efficient use of the FLASH array for NVM storage. If the user dedicates a page of FLASH for data storage, each call of the EE_WRITE routine shall copy the data stored in the RAM data array to the next blank block of locations within the FLASH page. Once a page is filled up the routine automatically erases the page and starts reusing the page from the original start location. For example, when the routine is used to store 2 bytes of data array, the flash page can be programmed 60 times before it is erased, subsequently increasing the write/erase endurance by 60. Two flash pages have been used in the design. Flash Page 0 (C000 – C07F) is used to store the tariff switch times and Flash page 1 (C080 – C0FF) is used to store timestamp and duration information. Figure 3-12 shows the NVM bytes stored in the emulated EEPROM.

Software



Figure 3-12. Emulated EEPROM

It should be noted that only 120 bytes are available in each page as the EE_WRITE routine uses an 8-byte control block. The ProgEeprom function flow diagram is shown in Figure 3-13.

Control Bytes

NVM Data 0

NVM Data 1

NVM Data 2

NVM Data 3

NVM Data 9

T1_Min

T1_Hour

T1_Day

T2_MinT2_Hour

T2_Day

T3_Min

T3_Hour

T3_Day

T4_Min

T4_Hour

T4_Day

Control Bytes

NVM Data 11

OpenCount

Second

Minute

HourDay

Month

Year

Second

Minute

Hour

NVM Data 0

NVM Data 1

NVM Data 2

NVM Data 3Time

Stamp

Duration

Tariff1

Tariff2

Tariff3

Tariff4

C000

C008

C014

xx00

xx0B

C014

C07F

C080

C0FF

xx00

xx09

Page0 EEPROM Page1 EEPROM




Figure 3-13. ProgEeprom

3.1.13 EE_WRITE:

This routine is used to write a set of data from a RAM data array to Flash. The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes in the data array is specified by DATASIZE. The minimum number of bytes that can be programmed in a data array is 2 bytes and the maximum number is 15Bytes. ADDRH:ADDRL must always be the start of the boundary address (the page address $xx00 or $xx80) and data size must be the same size when accessing the same page. The API for the EE_WRITE routine is shown below:

ProgEeprom

Load address of DataBuffer

Is it READ operation?Y

Call Write Eeprom monitorroutines

JSR EE_WRITE

Call Read Eeprom monitorroutines

JSR EE_READ

Return

N

Software



EE_READ:

This routine is used to read the data stored by the EE_WRITE routine. The routine copies the data set stored in FLASH to a user defined RAM array. Each call shall return the last data written by the EE_WRITE routine. The API for the EE_READ routine is shown below:

Name EE_WRITE

Description Emulated EEPROM write. Data size ranges from 2 to 15 bytes

Calling Address $FC00

Stack used 17 Bytes

Data Block Format

Bus speed (BUS_SPD)Data size (DATASIZE)Starting address (ADDRH)Starting address (ADDRL)Data1 :Data N

Name EE_READ

Description Emulated EEPROM read. Data size ranges from 2 to 15 bytes

Calling Address $FC03

Stack used 15 Bytes

Data Block Format

Bus speed (BUS_SPD)Data size (DATASIZE)Starting address (ADDRH)Starting address (ADDRL)Data1 :Data N




3.1.14 Real Time Clock ISR

The real time clock (RTC) module provides real time clock and calendar functions with automatic leap year adjustment. The module provides flags (and interrupts when enabled) for seconds, minutes, hours, days, days-of-the-week, months and years. In addition it also provides chronological, periodic and alarm interrupts.

The RTC_ISR is entered after each second and/or minute elapses. If a second interrupt is detected the function copies the RTC registers to the CopyRTC RAM buffer before checking if the 5 sec display count has timed out. If a timeout has occurred the display sequence count (SymbolFlags) is incremented to display the next data in the predefined sequence (T1, T2, T3, etc).

If the minute interrupt is also detected one of two possible algorithms are executed depending on the conditional compilation. If the TARRIF_TEST_UPDATE macro is included the tariff to be accumulated is changed every 3mins. The sequence is as follows T1, T2, T3, T4, T1, repeated. If the macro is not included the routine activates the tariffs depending on the time of day and day of week. The sequence is shown below:

T1: Monday – Friday, 08:00Hrs – 17:00HrsT2: Monday – Friday, 17:00Hrs – 23:00HrsT3: Monday – Friday, 23:00Hrs – 08:00HrsT4: Saturday or Sunday

The second and minute interrupt flags are cleared before exiting the ISR. Figure 3-14 shows the RTC_ISR flow diagram

Software



Figure 3-14. RTC_ISR

RTC_ISR

Get copy of RTC Statusregister

Second Interrupt?

Y

N

Incremet TimeCountMiniute Interrupt?

N

YCopy RTC Register toCopyRTC buffer

Reset CopyRTC and SecrRegpointers

TimeCount >=Timeoutlimit?

Update SymbolFlag count

Reset TimeCount = 0Reset Timeout to 5s

TARIFF_TEST_UPDATE?

TariffTimeoutCount >=Timeout limit

Set next tariff to be updated

Clear TariffTimeoutCount fornext update

Y

Y IncrementTariffTimeoutCount

Get tariff Switching timesfrom Eeprom

Current Day = Mondayto Friday?

Current Time =T1

Current Time =T2

Current Time =T3

Make T1_ACTIVE

Make T2_ACTIVE

Make T4_ACTIVE

Make T4_ACTIVE

Y

N

Clear Second InterruptClear Minute Interrupt

return

N

N

Y

N

Y

Y

Y

N

N

N




3.1.15 Keyboard ISR

The keyboard interrupt ISR is very simple. It is entered immediately a key is pressed. The key that initiated the interrupt is decoded and the appropriate flag is set in the ApplicationFlags buffer. The interrupt is also disabled to prevent the ISR being re-entered immediately after the ISR is exited. This is a possibility as the input could still be logic low after the interrupt has been serviced. The interrupts are enabled in the switch decode function. Figure 3-15 shows the KBD_ISR flow diagram.

Figure 3-15. Keyboard Interrupt

KBD_ISR

Get source of Interrupt and setflag in ApplicationFlags. Only

interested in upper 2 bits

DISPLAY_KEYPressed (Bit6)

Y

Return

N

Disable Display Key Interrupt

TAMPER_KEY Pressed(Bit7)

Disable Tamper key Interrupt

Clear Keyboard Interrupt flag

N

Y

Software




MOTOROLA Results 55


Section 4. Results

This section presents the results obtained for the reference design. These results were obtained at a test house using recognized ZERA test equipment. Each test was performed at 50Hz, unity power factor. The average power was calculated over a minimum of 280 samples.

The % error is within the +-1% error for the range and +-1.5% for the range, as required for a class1 meter. Additionally, the power meter operates in the voltage range of 160 to 270 volts, with error less than 0.2% and a startup current less than 10mA, which is within the IEC specification.

Power meter test house

Voltage Load CurrentAverage Power

Std Dev %Error

220 60 (4In) 13077.37 20.88 –0.93

220 50 (3.33In) 10968.66 12.63 –0.28

220 10 (0.66In) 2202.05 2.63 0.09

220 5 (0.33In) 1100.86 1.36 0.09

220 1 (0.06In) 219.85 0.55 –0.07

220 0.5 (0.033In) 109.72 0.53 –0.25

220 0.1 (0.0067In) 21.01 0.38 –4.48

220 0.03 (0.002In) 5.89 0.44 –10.74

0,05 In < In < 4I n

0,02 In < In < 0,05In

Results


56 Results MOTOROLA


MOTOROLA Conclusions 57


Section 5. Conclusions

The project has demonstrated that a modular low cost, single chip, digital power meter can be implemented with the 68HC908LJ12 and a minimum of external components, mainly discretes. The on-chip 10bit A/D is used with additional range extension circuits instead of an external measurement IC, to perform all voltage and current measurements. The resultant energy calculation is within the performance specification outlined in IEC61036 specification.

The LJ12 MCU provides a very cost effective solution for a power meter, as it enables the removal of the energy measurement device and has a rich set of on chip peripherals that are necessary for metering applications. The RTC, LCD, ADC, TIM, IRSCI and the EEPROM emulation routines reduce the external components required and the software overhead.

The modular design approach enables the hardware and software to be reused and thus speed up the design cycle for a power meter development. The schematics, Bill of Material, gerber files and software are all available to be downloaded from the Motorola website.

Conclusions


58 Conclusions MOTOROLA


MOTOROLA 59


Appendix A — Schematic

See over.


60 MOTOROLA


MOTOROLA 61


62 MOTOROLA


MOTOROLA 63


Appendix B — Calibration Coefficient

Step Angle [rad] Sine270 Volts

Input 220 V Input15 Amps

load 220*15 power Integer power

0 0.000 0.000 0.000 0.000 0.000 0.000 0

1 0.196 0.195 98.984 80.653 98.984 7983.376 7983

2 0.393 0.383 194.164 158.207 194.164 30718.109 30718

3 0.589 0.556 281.882 229.681 281.882 64743.041 64743

4 0.785 0.707 358.768 292.329 358.768 104878.185 104878

5 0.982 0.831 421.866 343.743 421.866 145013.331 145013

6 1.178 0.924 468.752 381.946 468.752 179038.265 179038

7 1.374 0.981 497.625 405.472 497.625 201773.002 201773

8 1.571 1.000 507.374 413.416 507.374 209756.383 209756

9 1.767 0.981 497.625 405.472 497.625 201773.011 201773

10 1.963 0.924 468.752 381.946 468.752 179038.283 179038

11 2.160 0.831 421.866 343.743 421.866 145013.354 145013

12 2.356 0.707 358.768 292.329 358.768 104878.210 104878

13 2.553 0.556 281.882 229.682 281.882 64743.064 64743

14 2.749 0.383 194.164 158.207 194.164 30718.126 30718

15 2.945 0.195 98.984 80.653 98.984 7983.386 7983

16 3.142 0.000 0.000 0.000 0.000 0.000 0

17 3.338 -0.195 -98.984 -80.653 -98.984 7983.367 7983

18 3.534 -0.383 -194.164 -158.207 -194.164 30718.091 30718

19 3.731 -0.556 -281.882 -229.681 -281.882 64743.018 64743

20 3.927 -0.707 -358.767 -292.329 -358.767 104878.161 104878

21 4.123 -0.831 -421.866 -343.743 -421.866 145013.308 145013


64 MOTOROLA

22 4.320 -0.924 -468.752 -381.946 -468.752 179038.248 179038

23 4.516 -0.981 -497.625 -405.472 -497.625 201772.993 201772

24 4.712 -1.000 -507.374 -413.416 -507.374 209756.383 209756

25 4.909 -0.981 -497.625 -405.472 -497.625 201773.021 201773

26 5.105 -0.924 -468.752 -381.946 -468.752 179038.300 179038

27 5.301 -0.831 -421.866 -343.743 -421.866 145013.376 145013

28 5.498 -0.707 -358.768 -292.329 -358.768 104878.235 104878

29 5.694 -0.556 -281.882 -229.682 -281.882 64743.087 64743

30 5.890 -0.383 -194.164 -158.207 -194.164 30718.144 30718

31 6.087 -0.195 -98.984 -80.654 -98.984 7983.395 7983

SUM = 3356102.254 3356095

8*SUM = 26848818.04 26848760

SUM/8 = 104878.195 104878

calib.coeff 8136.005 8136


MOTOROLA 65


Appendix C — Mixing assembly and ‘C’ code

C.1 Generating Assembler Include files (Option -La)

This option allows both compiler and assembler to use a single common file to share constants, variables/labels and even structure fields. The basic concept is that the compiler writes an output file in the format of the assembler, which contains all required information of the C header file. The method of enabling this option and a summary of the mappings supported is shown below. Refer to the appendix and the ANSI-C front-end section of the HC08 compiler manual for further details:

C.1.1 General use:

Two specific actions are required to output the assembly file. The first is to select the compilers –La option and the second is to include the #pragma CREATE_ASM_LISTING ON in the header file that is to be mapped and emitted. All macro definitions and declarations that appear after the #pragma shall be emitted (assuming compiler –La option has been selected). The compiler stops emitting after the #pragma CREATE_ASM_LISTING OFF. It should be noted that not all entries in a header file generate legal assembly constructs and the compiler does not check for legal assembly syntax when translating.

C.2 Header file example:

test.h

#pragma CREATE_ASM_LISTING ONtypedef struct

short i;short j;

Struct;Struct Var;


66 MOTOROLA

Void f(void)#pragma CREATE_ASM_LISTING OFF

If the –La option is selected the compiler generates the following test.inc file

Struct_SIZE EQU $4Struct_i EQU $0Struct_j EQU $2

XREF VarVar_i EQU Var + $0Var_j EQU Var + $2

XREF f

C.3 Calling functions and Variables

The ‘C’ functions and variables can simply be called, from the assembly code, using specific functions/Variables address or symbolic names, if the function does not require any parameters passed by the calling program. If the function requires parameters to be passed the parameters must be pushed on the stack and loaded into the Accumulator and X registers before the JSR or BSR are executed. Calling functions/variables from the C code that are declared in the assembly code is just as easy. Assuming they have been declared as extern, the C code calls the function/variables as if it was declared in C code (i.e samplecount, Disp_result() and T1_buffer[]). See appendix for further details

The mappings that the compiler uses when emitting the assembly include file are shown below. Further details can be found in the compiler manual.


MOTOROLA 67

• Macros

C #defines are translated to assembler EQU directives

‘C’ example:#pragma CREATE_ASM_LISTING ON#define Constant 1#define Sum Constant + 0x1000

Creates:Constant EQU 1Sum EQU Constant + $1000

NOTE: Macros with parameters, predefined macros and macros with no defined value are not emitted.

• enum values

C enum values are translated to assembler EQU directives

‘C’ example:#pragma CREATE_ASM_LISTING ONenum E1=4, E2=47;Creates:E1 EQU $4E2 EQU $2F

NOTE: Negative numbers are emitted as 32 bit hex numbers


68 MOTOROLA

• C types

The size of any type and the offset of structure fields are emitted for all typedefs. Additionally, the bit offset and the bit size are emitted for bit field structures

‘C’ example:#pragma CREATE_ASM_LISTING ONtypedef long LONGstruct tagA

char a;short b;

;typedef struct long d;struct tagA e;int f:2;int g:1; str;

Creates:LONG_SIZE EQU$4Str_SIZE EQU$8Str_d EQU$0Str_e EQU$4Str_e_a EQU$4Str_e_b EQU$5Str_f EQU$7Str_f_BIT_WIDTH EQU$2Str_f_BIT_OFFSET EQU$0Str_g EQU$7Str_g_BIT_WIDTH EQU$1Str_g_BIT_OFFSET EQU$2

NOTE: For all typedefs the size of the newly defined type is specified and the name is identical with SIZE appended. For structures the offset of all structure fields relative to the start are emitted. The name of the structure offset is built using the typedef name and the structure field name after the underline ‘_’. It should also be noted that the bit field members, are for example only, as the structure alignment and bit field allocation is compiler specific (not ANSI C).


MOTOROLA 69

• Functions

An XREF entry is emitted for each function

‘C’ example:#pragma CREATE_ASM_LISTING ONvoid main (void);void f_C (int i, long l);

Creates:XREF mainXREF f_C

• Variables

An XREF entry is emitted for each variable. Additionally, all fields for unions and structures are defined with EQU

‘C’ example:#pragma CREATE_ASM_LISTING ONstruct A

char a;int i:2;

;struct A VarA;#pragma DATA_SEG __SHORT_SEG ShortSegint VarA

Creates:

XREF VarAVarA_a EQU VarA + $0VarA_i EQU VarA + $1VarA_i_BIT_WIDTH EQU $2VarA_i_BIT_OFFSET EQU $0

XREF.B VarInt

NOTE: The size of the variable is not emitted.


70 MOTOROLA

• C style comments are mapped to assembly comments

‘C’ example:#pragma CREATE_ASM_LISTING ON/* This example showshow ‘C’ style comments aretranslated to assembly comments */

Creates:; This example shows; how ‘C’ style comments are; translated to assembly comments

NOTE: Comments inside the region emitted with #pragma CREATE_ASM_LISTING ON are also written into the assembler include file on a single line. However, comments inside of a typedef, structure or variable declaration are either before or after the declaration.

DRMxxx — Rev 0.0 Designer Reference Manual

MOTOROLA Glossary 71

Designer Reference Manual — DRMxxx

Section 6. Glossary

A — See “accumulator (A).”

accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations.

acquisition mode — A mode of PLL operation during startup before the PLL locks on a frequency. Also see “tracking mode.”

address bus — The set of wires that the CPU or DMA uses to read and write memory locations.

addressing mode — The way that the CPU determines the operand address for an instruction. The M68HC08 CPU has 16 addressing modes.

ALU — See “arithmetic logic unit (ALU).”

arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands.

asynchronous — Refers to logic circuits and operations that are not synchronized by a common reference signal.

baud rate — The total number of bits transmitted per unit of time.

BCD — See “binary-coded decimal (BCD).”

binary — Relating to the base 2 number system.

binary number system — The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels.

binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example, 234 (decimal) = 0010 0011 0100 (BCD)

bit — A binary digit. A bit has a value of either logic 0 or logic 1.

branch instruction — An instruction that causes the CPU to continue processing at a memory location other than the next sequential address.

break module — A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine.

breakpoint — A number written into the break address registers of the break module. When a number appears on the internal address bus that is the same as the number in the break address registers, the CPU executes the software interrupt instruction (SWI).

Glossary

Designer Reference Manual DRMxxx — Rev 0.0

72 Glossary MOTOROLA

break interrupt — A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers.

bus — A set of wires that transfers logic signals.

bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by four.

byte — A set of eight bits.

C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates).

CCR — See “condition code register.”

central processor unit (CPU) — The primary functioning unit of any computer system. The CPU controls the execution of instructions.

CGM — See “clock generator module (CGM).”

clear — To change a bit from logic 1 to logic 0; the opposite of set.

clock — A square wave signal used to synchronize events in a computer.

clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and or phase-locked loop (PLL) circuit.

comparator — A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers.

computer operating properly module (COP) — A counter module in the M68HC08 Family that resets the MCU if allowed to overflow.

condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed.

control bit — One bit of a register manipulated by software to control the operation of the module.

control unit — One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface.

COP — See “computer operating properly module (COP).”

counter clock — The input clock to the TIM counter. This clock is the output of the TIM prescaler.

CPU — See “central processor unit (CPU).”

CPU08 — The central processor unit of the M68HC08 Family.

CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by four.

Glossary



CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles.

CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are:

• A (8-bit accumulator)

• H:X (16-bit index register)

• SP (16-bit stack pointer)

• PC (16-bit program counter)

• CCR (condition code register containing the V, H, I, N, Z, and C bits)CSIC — customer-specified integrated circuit

cycle time — The period of the operating frequency: tCYC = 1/fOP.

decimal number system — Base 10 numbering system that uses the digits zero through nine.

direct memory access module (DMA) — A M68HC08 Family module that can perform data transfers between any two CPU-addressable locations without CPU intervention. For transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster and more code-efficient than CPU interrupts.

DMA — See “direct memory access module (DMA).”

DMA service request — A signal from a peripheral to the DMA module that enables the DMA module to transfer data.

duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually represented by a percentage.

EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that can be electrically reprogrammed.

EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed.

exception — An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program.

external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins.

fetch — To copy data from a memory location into the accumulator.

firmware — Instructions and data programmed into nonvolatile memory.

free-running counter — A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again.

full-duplex transmission — Communication on a channel in which data can be sent and received simultaneously.

Glossary



H — The upper byte of the 16-bit index register (H:X) in the CPU08.

H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction uses the state of the H and C bits to determine the appropriate correction factor.

hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A through F.

high byte — The most significant eight bits of a word.

illegal address — An address not within the memory map

illegal opcode — A nonexistent opcode.

I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled.

index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand. H:X can also serve as a temporary data storage location.

input/output (I/O) — Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal.

instructions — Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction.

interrupt — A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine.

interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine.

I/O — See “input/output (I/0).”

IRQ — See “external interrupt module (IRQ).”

jitter — Short-term signal instability.

latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit.

latency — The time lag between instruction completion and data movement.

least significant bit (LSB) — The rightmost digit of a binary number.

logic 1 — A voltage level approximately equal to the input power voltage (VDD).

logic 0 — A voltage level approximately equal to the ground voltage (VSS).

low byte — The least significant eight bits of a word.

low voltage inhibit module (LVI) — A module that monitors power supply voltage.

LVI — See “low voltage inhibit module (LVI).”

Glossary



M68HC08 — A Motorola family of 8-bit MCUs.

mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.

mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon.

mask option — A optional microcontroller feature that the customer chooses to enable or disable.

mask option register (MOR) — An EPROM location containing bits that enable or disable certain MCU features.

MCU — Microcontroller unit. See “microcontroller.”

memory location — Each M68HC08 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus.

memory map — A pictorial representation of all memory locations in a computer system.

microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.

modulo counter — A counter that can be programmed to count to any number from zero to its maximum possible modulus.

monitor ROM — A section of ROM that can execute commands from a host computer for testing purposes.

MOR — See “mask option register (MOR).”

most significant bit (MSB) — The leftmost digit of a binary number.

multiplexer — A device that can select one of a number of inputs and pass the logic level of that input on to the output.

N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result.

nibble — A set of four bits (half of a byte).

object code — The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code.

opcode — A binary code that instructs the CPU to perform an operation.

open-drain — An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage.

operand — Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added.

oscillator — A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference.

Glossary



OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed.

overflow — A quantity that is too large to be contained in one byte or one word.

page zero — The first 256 bytes of memory (addresses $0000–$00FF).

parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s.

PC — See “program counter (PC).”

peripheral — A circuit not under direct CPU control.

phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal.

PLL — See “phase-locked loop (PLL).”

pointer — Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand.

polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, VDD and VSS.

polling — Periodically reading a status bit to monitor the condition of a peripheral device.

port — A set of wires for communicating with off-chip devices.

prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc.

program — A set of computer instructions that cause a computer to perform a desired operation or operations.

program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of the next instruction or operand that the CPU will use.

pull — An instruction that copies into the accumulator the contents of a stack RAM location. The stack RAM address is in the stack pointer.

pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply.

pulse-width — The amount of time a signal is on as opposed to being in its off state.

pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a signal with a constant frequency.

push — An instruction that copies the contents of the accumulator to the stack RAM. The stack RAM address is in the stack pointer.

PWM period — The time required for one complete cycle of a PWM waveform.

Glossary



RAM — Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off.

RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.

read — To copy the contents of a memory location to the accumulator.

register — A circuit that stores a group of bits.

reserved memory location — A memory location that is used only in special factory test modes. Writing to a reserved location has no effect. Reading a reserved location returns an unpredictable value.

reset — To force a device to a known condition.

ROM — Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU.

SCI — See “serial communication interface module (SCI).”

serial — Pertaining to sequential transmission over a single line.

serial communications interface module (SCI) — A module in the M68HC08 Family that supports asynchronous communication.

serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports synchronous communication.

set — To change a bit from logic 0 to logic 1; opposite of clear.

shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain.

signed — A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number.

software — Instructions and data that control the operation of a microcontroller.

software interrupt (SWI) — An instruction that causes an interrupt and its associated vector fetch.

SPI — See “serial peripheral interface module (SPI).”

stack — A portion of RAM reserved for storage of CPU register contents and subroutine return addresses.

stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available storage location on the stack.

start bit — A bit that signals the beginning of an asynchronous serial transmission.

status bit — A register bit that indicates the condition of a device.

stop bit — A bit that signals the end of an asynchronous serial transmission.

Glossary



subroutine — A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off.

synchronous — Refers to logic circuits and operations that are synchronized by a common reference signal.

TIM — See “timer interface module (TIM).”

timer interface module (TIM) — A module used to relate events in a system to a point in time.

timer — A module used to relate events in a system to a point in time.

toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.

tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also see “acquisition mode.”

two’s complement — A means of performing binary subtraction using addition techniques. The most significant bit of a two’s complement number indicates the sign of the number (1 indicates negative). The two’s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result.

unbuffered — Utilizes only one register for data; new data overwrites current data.

unimplemented memory location — A memory location that is not used. Writing to an unimplemented location has no effect. Reading an unimplemented location returns an unpredictable value. Executing an opcode at an unimplemented location causes an illegal address reset.

V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow bit.

variable — A value that changes during the course of program execution.

VCO — See “voltage-controlled oscillator.”

vector — A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset.

voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input.

waveform — A graphical representation in which the amplitude of a wave is plotted against time.

wired-OR — Connection of circuit outputs so that if any output is high, the connection point is high.

word — A set of two bytes (16 bits).

write — The transfer of a byte of data from the CPU to a memory location.

X — The lower byte of the index register (H:X) in the CPU08.

Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00.

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