DRRADynamically Reconfigurable Resource Array

Ahmed HemaniDept. Of ES, School of ICT, KTH Kista

Email: hemani@kth.seWebsite: www.it.kth.se/~hemani

• ASIC like arbitrary parallelism, local and hierarchical control

• Software like flexibility• Regular, seamless topology

– Easy mapping– Perfect energy and performance prediction– Full custom will compensate the reconfiguration

overheads • Private execution environments• Minimal movement of data

– Move Logic Not Data• Vectorising, Symbolic Assembler under development• C/Matlab compiler to be developed

DRRADynamically Reconfigurable Resource Array

DRRA System Concept

+ + + + + + + + + + + +Reconfigurable Arithmetic Resource Pool

. . .Reconfigurable Control Logic Resource Pool

. . .Register File Pool

. . .Protocol Processor Pool

. . .3D Distributed Memory Pool

Application Processor - RISC

Run

Tim

e M

anag

emen

t Sys

tem

Pro

cess

or -R

ISC

External Data Exchange Interconnect

Control and Configuration Interconnect

External IFManager

ResourceManager

ApplicationManager

Runtime Management System PowerManagement

Application Controller (SW)

Protocol Processing LayersController (SW+CW)

Algo

rithm

D

atap

ath

Algo

rithm

D

atap

ath

Algo

rithm

D

atap

ath

. . .

Physical Layer Controllers (HW)Modem/Codec etc. Controller

Tx/Encode etc. Ctrlr Rx/Decode etc. Ctrlr

Applications run concurrently in theirprivate execution environments in DRRA

Application 1 Application 2 Application 3Private execution environments for three applications

look at http://web.it.kth.se/~hemani/DRRA%20Summary.pdf3. DRRA System Architecture

Regiser File16b X 64

2 Read , 2 Write PortsBurst Mode,

Shift and Circular Buffer Mode

Addrs Gen. UnitContext Memory

Morphable DPU16 bit, 32 bit accumulator

4 Inputs, 2 OutputsMAC, Butterfly, 5 stage pipeline

ADD/SUB treeSum of Difference, Difference of Sum

LFSR, Counter, ComparatorsWindowed Truncation, Saturation

Context Memory

Interconnect3 hop, Sliding window Fully

connectedSegmented 7 hop WiresCircuit Switchd Network

Local Config Memory

FabricScalabe, Regular Topology

Interfaces to Distributed Memory and Central Controller

SequencerSimple sequential flow

Conditional and Counter based Loop and branching

Controls Register File, mDPU and Interconnect switches

DRRA PHY Layer Fabric

7 X 216b

buses

1216b

buses

Initial Results

90 nm, 720 MHz64 point FFT – radix -2 DIT

~50 nJ, ~300 ns. UnoptimisedN.B. 4 mDPUs and 4 Regfiles used

90 nm, 720 MHz11 tap FIR– Symmetric

~300 pJ, ~6 ns. UnoptimisedN.B. 1 mDPU and 1 Regfile used

Layout of 7X2 mDPUs, Regfiles and Sequencers, Corresponding to the fabric shown on the previous slide

Long term goal is to come very close to ASIC with full custom datapath

Vectorising Symbolic Assembler

N is the order of the filter. M is the degree of parallelismAll serial parallel solutions are concisely captured by this pattern

The mapping for N=101, M = 7

x0

x6

x100

x94

x7

x13

x93

x87

x14

x20

x86

x80

x21

x27

x79

x73

x28

x34

x72

x66

x35

x42

x65

x58

x43

x49

x57

x50

x51

+×+

+×+

+×+

+×+

+×+

+×+

+×+

+ ++

C7-C13

+ ++

+ ++

00

0

C0-C6 C14-C20 C21-C27 C28-C34 C35-C42 C43-C50

refi_0_0 refi_0_1 refi_0_2 refi_0_3 refi_0_4 refi_0_5 refi_0_6

refi_1_0 refi_1_1 refi_1_2 refi_1_3 refi_1_4 refi_1_5 refi_1_6

p0 p1 p2 p3 p4 p5 p6

adderTree4

newSample

convSum

Protocol Processor Concept

API To Higher Layer

API To Lower Layer

Cont

rol a

nd T

imin

g

Frag

/D

efra

g

Erro

r Chk

Encr

yp/

Dec

ryp

Bit F

ield

An

alys

is

Mem

ory

Constants

Registers

For explaination look at http://web.it.kth.se/~hemani/DRRA%20Summary.pdf

Go to section 5: Protocol Processor Architecture

REXAPPRadio Experimentation & Prototyping Platform

Baseband Rx ProtocolProcessing

Layers

ApplicationLayerBaseband TxRF/Analog Tx

RF/Analog Rx

Confi

gura

ble

Chan

el M

odel

Baseband Rx ProtocolProcessing

Layers

ApplicationLayerBaseband TxRF/Analog Tx

RF/Analog Rx

Control, Configuration, Debug and Monitoring

Control, Configuration, Debug and Monitoring Resources

Hos

t Int

erfa

ce

Configurable RF/Analog Impairment Models

High Capacity, High Bandwidth Storage

Vision for the future

Non-Volatile Memory - TeraBytes

Volatile Memory - GigaBytes

Logic Tile - Giga Gates

RF/Analog/Sensors/peripherals

Don’t stop dreaming !