drv601evm2 user's guideuser's guide slou217–march 2008 drv601evm2 this user’s guide describes...

User's GuideSLOU217–March 2008

DRV601EVM2

This user’s guide describes the operation of the DRV601EVM2 stereo line driver evaluation module andprovides measurement data and design information such as the schematic, bill of materials, andprinted-circuit board layout.

Contents1 Overview ...................................................................................................................... 22 Quick Setup Guide........................................................................................................... 43 Shutdown ..................................................................................................................... 54 Component Selection ....................................................................................................... 55 Layout Recommendations .................................................................................................. 76 DRV601EVM2 Performance ............................................................................................... 87 Related Documentation from Texas Instruments ...................................................................... 198 Design Documentation .................................................................................................... 19

List of Figures

1 DRV601EVM2................................................................................................................ 22 DRV601EVM2 Functional Block Diagram ................................................................................ 33 DRV601EVM2 Physical Structure ......................................................................................... 34 Power-Up/Down Sequence................................................................................................. 55 Second-Order, Active Low-Pass Filter .................................................................................... 66 THD+N vs Voltage (Analog Input) ....................................................................................... 107 THD+N vs Voltage (Analog Input) Linear Scale........................................................................ 108 THD+N vs Voltage (Digital Input) ........................................................................................ 119 THD+N vs Voltage (Digital Input) Linear Scale ........................................................................ 1110 THD+N vs Frequency (Analog Input).................................................................................... 1211 THD+N vs Frequency (Digital Input)..................................................................................... 1212 FFT Spectrum With –60-dBFS Tone (Analog Input)................................................................... 1313 FFT Spectrum With –60-dBFS Tone (Digital Input) ................................................................... 1314 Idle Noise FFT Spectrum (Analog Input)................................................................................ 1415 Idle Noise FFT Spectrum (Digital Input)................................................................................. 1416 Channel Separation (Analog Input) ...................................................................................... 1517 Channel Separation (Digital Input) ....................................................................................... 1518 Frequency Response (Analog Input) .................................................................................... 1619 Frequency Response (Digital Input) ..................................................................................... 1620 Pop/Click (Enable) ......................................................................................................... 1721 Pop/Click (Disable)......................................................................................................... 1822 DRV601EVM2 PCB Component Placement Top ...................................................................... 2323 DRV601EVM2 PCB Top and Bottom Layers ........................................................................... 23

List of Tables

1 DRV601EVM2 Specifications .............................................................................................. 22 Recommended Supply Voltage ............................................................................................ 53 DRV601EVM2 Specification................................................................................................ 64 General Test Specifications ................................................................................................ 8

PurePath Digital, DirectPath, FilterPro are trademarks of Texas Instruments.TOSLINK is a trademark of Toshiba Corp..

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1 Overview

Overview

5 Electrical Data................................................................................................................ 86 Audio Performance Analog Input .......................................................................................... 87 Audio Performance Digital Input ........................................................................................... 88 Physical Specifications...................................................................................................... 99 DRV601EVM2 Parts List .................................................................................................. 2110 PCB Specifications......................................................................................................... 22

The DRV601EVM2 customer evaluation module (EVM) demonstrates the integrated circuits DRV601RTJfrom Texas Instruments (TI).

The DRV601 is a stereo line driver designed to allow the removal of the DC-blocking capacitors forreduced component count and cost. The DRV601 is ideal for single-supply electronics where size andcost are critical design parameters.

The DRV601 is capable of driving 2 Vrms into a 600-Ω load at 3.3-V supply. The DRV601 has externalgain-setting resistors that support a gain range of -1 V/V to -10 V/V and line outputs that have ±8 kV IECESD protection. The DRV601 has independent shutdown control for the left and right audio channels.

This EVM is configured with one TOSLINK™digital audio S/PDIF connector, two RCA phono inputconnectors, and two RCA phono output connectors. Power supply is connected via a two-pin 2,54-mm pinheader.

Table 1. DRV601EVM2 SpecificationsKEY PARAMETERS

Supply Voltage 5 VNumber of Channels 2Load Impedance Minimum 600 ΩOutput Voltage 2 VrmsDYR > 105 dB analog in, 98 dB digital in

This EVM is designed for evaluating applications such as set-top boxes and PDP/LCD televisions.

This document covers EVM specifications, audio performance measurements graphs, and designdocumentation that includes schematics, parts list, and layout design.

Figure 1. DRV601EVM2

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1.1 DRV601EVM2 Features

1.2 PCB Key Map

Overview

Gerber (layout) files are available at the TI Web site.

• Two-channel evaluation module [a double-sided, plated-through printed-circuit board (PCB) layout]• 2-Vrms line output• Digital S/PDIF TOSLINK™ input• Output capacitor-less.• Shutdown button

Figure 2. DRV601EVM2 Functional Block Diagram

The physical structure of the DRV601EVM2 is shown in Figure 3.

Figure 3. DRV601EVM2 Physical Structure


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2 Quick Setup Guide

2.1 Electrostatic Discharge Warning

2.2 Unpacking the EVM

Quick Setup Guide

This section describes the DRV601EVM2 board in regards to power supply and system interfaces. Itprovides information regarding handling and unpacking, absolute operating conditions, and a descriptionof the factory default switch and jumper configuration.

The following is a step–by–step guide to configuring the DRV601EVM2 for device evaluation.

Many of the components on the DRV601EVM2 are susceptible to damage by electrostatic discharge(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handlingthe EVM, including the use of a grounded wrist strap at an approved ESD workstation.

CAUTIONFailure to observe ESD handling procedures may result in damage to EVMcomponents.

On opening the DRV601EVM2 package, ensure that the following items are included:• 1 pc. DRV601EVM2 board with one DRV601RTJ• 1 pc. PurePath Digital™ CD-ROM

If either of these items is missing, contact the Texas Instruments Product Information Center nearest youto inquire about a replacement.

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2.3 Power Supply Setup

3 Shutdown

DVDD

SHUTDOWN

> 50 sm > 50 sm

4 Component Selection

4.1 Charge Pump

Shutdown

To power up the EVM, one power supply is needed. The power supply is connected to the EVM using a2-pin, 2,54-mm pin header, J10.

Table 2. Recommended Supply VoltageDescription Voltage Limitations Current Requirement Cable

Power supply 5 V 0.25 A

CAUTIONApplying voltages above the limitations given in Table 2 may cause permanentdamage to your hardware.

For minimum click and pop during power on and power off, the shutdown pin should be kept low. Thepreferred power-up/down sequence is shown in Figure 4.

Figure 4. Power-Up/Down Sequence

On the DRV601EVM2, the correct shutdown signal is provided by U95, a TPS3825-33 supply monitor.

The charge pump flying capacitor, C13, serves to transfer charge during the generation of the negativesupply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allowmaximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.Capacitor values smaller than 1 µF can be used, but the maximum output can be reduced. It is thereforerecommended to validate the design with thorough testing.



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4.2 Decoupling Capacitors

4.3 Using the DRV601 as a Second-Order Low-Pass Filter

C2

R1 R3

R2

C1

+

-

C3

Component Selection

The DRV601 is a DirectPath™ line driver amplifier that requires adequate power supply decoupling toensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance(ESR) ceramic capacitor, C12, typical 1 µF, placed as close as possible to the device VDD leads worksbest. Placing this decoupling capacitor close to the DRV601 is important for the performance of theamplifier. For filtering lower frequency noise signals, a 10-µF or greater capacitor placed near the audioamplifier also helps, but is not required in most applications because of the high PSRR of this device.

The charge pump circuit does apply ripple current on the VDD line, and a LC or RC filter may be needed ifnoise-sensitive audio devices share the VDD supply.

Many of the audio DACs used today require an external low-pass filter, to remove band noise. This ispossible with the DRV601, and the EVM is configured as a 40-kHz, second-order, active Butterworth filter.The topology chosen is the MFB Single-Ended. Further, the DRV601 needs a ac-coupling capacitor toremove dc-content from the source.

Figure 5. Second-Order, Active Low-Pass Filter

The component values can be calculated with the help of the TI FilterPro™ program available on:http://focus.ti.com/docs/toolsw/folders/print/filterpro.html

In Table 3, various proposals for the filter and gain settings can be found.

Table 3. DRV601EVM2 SpecificationGain High Pass Low Pass C1 C2 C3 R1 R2 R3

–1 V/V 16 Hz 40 kHz 100 pF 680 pF 1 µF 10 kR 10 kR 24 kR-1.5 V/V 19 Hz 40 kHz 68 pF 680 pF 1 µF 8.2 kR 12 kR 30 kR-2 V/V 11 Hz 40 kHz 33 pF 330 pF 1 µF 15 kR 30 kR 47 kR–2 V/V 11 Hz 30 kHz 47 pF 470 pF 1 µF 15 kR 30 kR 43 kR

–3.33 V/V 12 Hz 40 kHz 33 pF 470 pF 1 µF 13 kR 43 kR 43 kR-10 V/V 15 Hz 30 kHz 22 pF 1 nF 2.2 µF 4.7 kR 47 kR 27 kR

The resistor values should be low value to get low noise, but should be high value to get a small sizeac-coupling capacitor. With the proposed values, 15k, 30k, and47k, a DYR of 105 dB can be achievedwith a small 1-µF input ac-coupling capacitor.


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5 Layout Recommendations

5.1 Exposed Pad on the DRV601RJT Package

5.2 SGND and PGND Connections

Layout Recommendations

The exposed metal pad on the DRV601RTJ package can be soldered to a pad on the PCB in order toimprove reliability. The pad on the PCB should be allowed to float and not be connected to ground orpower. Connecting this pad to power or ground prevents the device from working properly because it isconnected internally to PVSS.

The SGND and PGND pins of the DRV601 must be routed separately back to the decoupling capacitor inorder to provide proper device operation. If the SGND pins are connected directly to each other, the partfunctions without risk of failure, but the noise and THD performance can be reduced.



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6 DRV601EVM2 PerformanceDRV601EVM2 Performance

This section provides general test specifications, electrical data, audio performance data, and physicalspecifications.

Table 4. General Test Specifications (1)

GENERAL TEST SPECIFICATIONS NOTESSupply Voltage 5 VLoad Impedance 600 ΩInput Signal 1-kHz Sine Digital audio TOSLINK™ S/PDIFMeasurement Filter AES17

(1) These test conditions are used for all tests, unless otherwise specified.

Table 5. Electrical Data (1)

ELECTRICAL DATA SPECIFICATIONS NOTES/CONDITIONSOutput Voltage, 600 Ω 2 Vrms 1 kHz, unclipped (< 1% THD), TA = 25°COutput Voltage, 100 kΩ 2.1 Vrms 1 kHz, unclipped (< 1% THD), TA = 25°CSupply Current < 10 mA 1 kHz, 2 m Vrms output voltageSupply Current < 20 mA 1 kHz, 2 m Vrms output voltage into 600 Ω

(1) All electrical and audio specifications are typical values.

Table 6. Audio Performance Analog InputAUDIO PERFORMANCE ANALOG INPUT NOTES/CONDITIONS

THD+N, 600 Ω 0.02 Vrms < 0.099 % 1 kHz (Noise-limited)THD+N, 600 Ω 0.2 Vrms < 0.009 % 1 kHz (Noise-limited)THD+N, 600 Ω 2 Vrms < 0.006 % 1 kHzTHD+N, 100 kΩ 0.02 Vrms < 0.099 % 1 kHz (Noise-limited)THD+N, 100 kΩ 0.2 Vrms < 0.009 % 1 kHz (Noise- limited)THD+N, 100 kΩ 2 Vrms < 0.003 % 1 kHzDynamic Range > 105 dB Ref: 2 Vrms, A-weighted, AES17 filterNoise Voltage < 12 µVrms A-weighted, AES17 filterDC Offset < 5 mV No signal, 600-Ω loadChannel Separation > 97 dB 1 kHz, 2 VrmsFrequency Response: 20 Hz to 20 kHz ±1 dB 2 Vrms/600 Ω

Table 7. Audio Performance Digital InputAUDIO PERFORMANCE DIGITAL INPUT NOTES/CONDITIONS

THD+N, 600 Ω 0.02 Vrms < 0.2 % 1 kHz (Noise-limited)THD+N, 600 Ω 0.2 Vrms < 0.02 % 1 kHz (Noise-limited)THD+N, 600 Ω 2 Vrms < 0.04 % 1 kHzTHD+N, 100 kΩ 0.02 Vrms < 0.2 % 1 kHz (Noise-limited)THD+N, 100 kΩ 0.2 Vrms < 0.02 % 1 kHz (Noise- limited)THD+N, 100 kΩ 2 Vrms < 0.04 % 1 kHzDynamic Range > 98 dB Ref: 2 Vrms, A-weighted, AES17 filterNoise Voltage < 25 µVrms A-weighted, AES17 filterDC Offset < 5 mV No signal, 600-Ω loadChannel Separation > 75 dB 1 kHz, 2 VrmsFrequency Response: 20 Hz to 20 kHz ±1 dB 2 Vrms/600 Ω



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DRV601EVM2 Performance

Table 8. Physical Specifications (1)

PHYSICAL SPECIFICATIONS NOTES/CONDITIONSPCB Dimensions 70 x 70 x 25 Width x Length x Height (mm)Total Weight 40 g Components + PCB + Mechanics

(1) All electrical and audio specifications are typical values.



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6.1 THD+N vs Voltage (Analog Input)

0.001

10

0.002

0.005

0.01

0.02

0.05

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2

5

3m 45m 10m 20m 50m 100m 200m 500m 1 2

Voltage - V

600 W

100 kW

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tort

ion

+ N

ois

e -

%

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200m 2.4400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2

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D+

N -

To

tal

Ha

rmo

nic

Dis

tort

ion

+ N

ois

e -

%

Voltage - V

600 W

100 kW


Figure 6. THD+N vs Voltage (Analog Input)

The THD+N from 10 mVrms to approximately 0.5 Vrms is dominated by noise.

Figure 7. THD+N vs Voltage (Analog Input) Linear Scale

Here the THD+N versus output voltage is shown with linear scale. This makes it easier to see whereclipping occurs. Clipping is often defines as THD+N=1%.



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6.2 THD+N vs Voltage (Digital Input)

0.001

10

0.002

0.005

0.01

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ois

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%

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Voltage - V

Input = 1 kHz

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D+

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tal

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rmo

nic

Dis

tort

ion

+ N

ois

e -

%

Voltage - V

600 W

100 kW

Input = 1 kHz


Figure 8. THD+N vs Voltage (Digital Input)

The THD+N in the range from 10 mVrms to 1 Vrms is completely dominated by noise. The THD+N isindependent of the load impedances and is set by the PCM1772 DAC.

Figure 9. THD+N vs Voltage (Digital Input) Linear Scale

Here the THD+N versus output voltage is shown with linear scale. This makes it easier to see whereclipping occurs. Clipping is often defined as THD+N = 1%.



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6.3 THD+N vs Frequency

0.001

10

0.002

0.005

0.01

0.02

0.05

0.1

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0.5

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20 20k50 100 200 500 1k 2k 5k 10k

f - Frequency - Hz

TH

D+

N -

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tal

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rmo

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Dis

tort

ion

+ N

ois

e -

%

Input = 2 Vrms

600 W

100 kW

20 20k50 100 200 500 1k 2k 5k 10k0.001

10

0.002

0.005

0.01

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0.05

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1

2

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TH

D+

N -

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tal

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rmo

nic

Dis

tort

ion

+ N

ois

e -

%

600 W

100 kW

Input = 0 dBFs

f - Frequency - Hz


Figure 10. THD+N vs Frequency (Analog Input)

Figure 11. THD+N vs Frequency (Digital Input)



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6.4 FFT Spectrum With –60 dBFS Tone

-150

0

-140

-130

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0 22k2k 4k 6k 8k 10k 12k 14k 16k 18k 20k

f - Frequency - Hz

Am

pli

tud

e -

dB

0 22k2k 4k 6k 8k 10k 12k 14k 16k 18k 20k-150

0

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Am

pli

tud

e -

dB

r


Reference voltage is 2 V rms. FFT size is 16k.

Figure 12. FFT Spectrum With –60-dBFS Tone (Analog Input)

Figure 13. FFT Spectrum With –60-dBFS Tone (Digital Input)



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6.5 Idle Noise FFT Spectrum

0 90k10k 20k 30k 40k 50k 60k 70k 80k-150

0

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r

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0

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Am

pli

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dB

r


Reference voltage is 2 Vrms. FFT size is 16k.

Figure 14. Idle Noise FFT Spectrum (Analog Input)

Figure 15. Idle Noise FFT Spectrum (Digital Input)



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6.6 Channel Separation

10 20k20 50 100 200 500 1k 2k 5k 10k-120

10

-110

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r

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0 dB

Left to Right

Right to Left

10 20k20 50 100 200 500 1k 2k 5k 10k-120

10

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r

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0 dB

Right to Left

Left to Right


Output signal is 2 Vrms. Reference voltage is 2 Vrms. Load is 600R.

Figure 16. Channel Separation (Analog Input)

Figure 17. Channel Separation (Digital Input)



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6.7 Frequency Response

-20

2

-19

-18-17-16-15

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-13-12-11

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Am

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r

f - Frequency - Hz

10 200k20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k-20

2

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1

Am

pli

tud

e -

dB

r

f - Frequency - Hz


Measurement bandwidth filter is set to 500 kHz. Load is 600R.

Figure 18. Frequency Response (Analog Input)

Figure 19. Frequency Response (Digital Input)

The low-frequency cutoff of 10 Hz (–3 dB) is determined by the input ac-coupling capacitor, 1 µF, togetherwith the feedback network input impedance of 15kR.

The low-pass, second-order filter implemented gives a –3 dB approximately at 35 kHz, and the responseis 13 dB down at 80 kHz.



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6.8 Pop/Click (Enable)

-100m

100m

-80m

-60m

-40m

-20m

0

20m

40m

60m

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Vo

lta

ge

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t - Time - sec

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+0

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300 30k500 1k 2k 5k 10k 20kf - Frequency - Hz

Am

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dB

r

6.9 Pop/Click (Disable)


No input signal is applied. The measurement results are presented both in a time domain and in afrequency domain. The resistor load is 600 Ω.

The power supply is applied, and then the shutdown signal is released. The shutdown signal is used totrigger the measuring system. For a description of the measuring technique, see the application reportPop and Click Measuring Technique (SLEA044).

Figure 20. Pop/Click (Enable)

The DRV601 shows low pop during enable; only two small high-frequency spikes can be seen. Themeasurements are made with reference to 2 Vrms = 0 dB, 2 mV=-60 dBr.

No input signal is applied. The measurement results are presented both in a time domain and in afrequency domain.

No input signal applied. Load: 600 Ω.


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-100m

100m

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0

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Vo

lta

ge

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t - Time - sec

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300 30k500 1k 2k 5k 10k 20k

Am

pli

tud

e -

dB

f - Frequency - Hz


Figure 21. Pop/Click (Disable)

During power down, the click is even lower than during power on (enable). A small click is seen.



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7 Related Documentation from Texas Instruments

8 Design Documentation

Related Documentation from Texas Instruments

The following is a list of documents containing detailed descriptions of the integrated circuits used in thedesign of the DRV601EVM2.1. DRV601, DirectPath™ Stereo Line Driver, Adjustable Gain data sheet (SLOS553)2. DIR9001, 96-kHz, 24-Bit Digital Audio Interface Receiver data sheet (SLES198)3. PCM1772, PCM1773, Low-Voltage and Low-Power Stereo Audio Digital-to-Analog Converter With

Lineout Amplifier data sheet (SLES010)

This section includes a schematic for the DRV601EVM2, the bill of materials, and the PCB designspecifications.


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8.1 DRV601EVM2 Schematic

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2

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Design Documentation



www.ti.com

8.2 Parts ListDesign Documentation

Table 9. DRV601EVM2 Parts ListQty Part Description Manufacture First Mfr P/N

Reference1 R90 10.0R / 250mW / 1% / 1206 Thick Film Resistor Yageo RC1206FR-0710RL1 R55 1.0k / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-071KL2 R54 R96 10k / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-0710KL2 R18 R19 10R / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-0710RL2 R11 R12 15k / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-0715KL2 R56 R95 220R / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-

07220RL2 R16 R17 33k / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-0733KL2 R14 R15 47k / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-0747KL5 R50 R52 R53 4.7R / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-074R7L

R58 R601 R51 680R / 100mW / 5% / 0603 Thick Film Resistor Yageo RC0603JR-

07680RL3 C12 C13 C14 Ceramic 1µF / 16V / 20% X7R 0805 Capacitor BC Components 0805B105M160NT3 C59 C91 C92 Ceramic 100nF / 16V / 20% X7R 0603 Capacitor Vishay VJ0603Y104MXJ3 C51 C55 C61 Ceramic 100nF / 50V / 20% X7R 0603 Capacitor Vishay VJ0603Y104MXA1 C53 Ceramic 4.7nF / 50V / 20% X7R 0603 Capacitor BC Components 0603B472M500NT1 C52 Ceramic 68nF / 16V / 20% X7R 0603 Capacitor BC Components 0603B683M160NT1 C95 Ceramic 1nF / 50V / 10% NP0 0603 Capacitor BC Components 0603N102K500NT2 C19 C20 Ceramic 33pF / 50V / 10% NP0 0603 Capacitor BC Components 0603N330K500NT2 C17 C18 Ceramic 330pF / 50V / 10% NP0 0603 Capacitor BC Components 0603N331K500NT8 C50 C54 C58 Electrolytic 10µF / 16V / 20% Aluminum 1.5mm x 4mm KG Series Panasonic ECEA1CKG100

C60 C90 C93 – General Purpose, Miniature CapacitorC96

1 C62 Electrolytic 47µF / 6.3V / 20% Aluminum 1.5mm x 4mm ML Series Rubycon 6.3ML47M4X7– Miniature Capacitor

2 C15 C16 Metal Film 1µF / 16V / 20% Polyester 1210 Capacitor Panasonic ECPU1C105MA51 D50 Light Emitting Red LED (0603) Toshiba TLSU10081 D95 Light Emitting Green LED (0603) Toshiba TLGU10082 Q50 Q95 600mA / 40V NPN Small signal PMBT2222 Transistor (SOT-23) Philips PMBT22221 U50 DIR9001 / 96kHz Digital Audio Receiver (TSSOP28) Texas DIR9001PW

Instruments1 U60 PCM1773 / Low-Power Stereo DAC with line-out (H/W Control) Texas PCM1773PW

(TSSOP16-PW) Instruments1 U1 DRV601 / DirectPath(TM) Audio Line Driver with external gain Texas DRV601RTJT

setting. (QFN-20) Instruments1 U95 TPS3825-33 / 3.3V Supply Voltage Supervisor (SOP5-DBV) Texas TPS3825-33DBVT

Instruments1 U90 TLV1117-33C / 3.3V/800mA Positive Voltage Regulator Texas TLV1117-33CDCYR

(SOT4-DCY) Instruments1 J50 Toslink Optical Receiver Toslink Receiver, 3.3V Special func. Toshiba TORX141P4 SCREW11 M3x6 Pan Head, Pozidriv, A2 Screw Bossard BN 81882 M3x6

SCREW12SCREW13SCREW14

4 WASHER11 M3 Stainless Steel Washer Bossard BN 670 M3WASHER12WASHER13WASHER14



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8.3 PCB Specifications

Design Documentation

Table 9. DRV601EVM2 Parts List (continued)Qty Part Description Manufacture First Mfr P/N

Reference4 STANDOFF1 M3x10 Aluminum Stand-off Ettinger 05.03.108

1STANDOFF12STANDOFF13STANDOFF14

1 J10 2 pins / 1 row / 2,54mm Pitch Vertical Male Friction lock Pin Molex 22-27-2021Header

4 J11 J12 J21 Horizontal Female w. Switch Coax Phono socket Chunfeng RJ843-4WJ22

2 J13 J14 3 pins / 1 row / 2,00mm Pitch Vertical Male Gold Shunt Header Harwin M22-2010305Shunt Header

1 SW90 Switch DPDT PCB Mount Switch NKK-Nikkai G-22-AP1 PCB11 A838-PCB-001(2.00) / DRV601EVM2 Printed Circuit Board (2.00) Printline A838-PCB-

001(2.00)

Table 10. PCB SpecificationsBoard identification A838-PCB-001(2.00)Board type Double-sided plated-through boardLaminate type FR4Laminate thickness 1,6 mmCopper thickness 35 µm (Include plating exterior layer)Copper plating of holes > 25 µmMinimum hole diameter 0,3 mmSilkscreen component side White—Remove silkscreen from solder area and pre-tinned areasSilkscreen solder side NoneSolder mask component side GreenSolder mask solder side GreenProtective coating Solder coating and chemical silver on free copperElectrical tests PCB must be electrically testedManufactured to PERFAG 2E (www.perfag.dk)Aperture table PERFAG 10A (www.perfag.dk)Board size 60 mm × 50 mmComments See drill information file (A838-PCB-001 (DrillDrawing).pdf)

22 DRV601EVM2 SLOU217–March 2008Submit Documentation Feedback


www.ti.com

8.4 PCB LayoutDesign Documentation

Gerber files are available on the EVM page for download.

Figure 22. DRV601EVM2 PCB Component Placement Top

Figure 23. DRV601EVM2 PCB Top and Bottom Layers



EVALUATION BOARD/KIT IMPORTANT NOTICETexas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. Thisnotice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/orsafety programs, please contact the TI application engineer or visit www.ti.com/esh.No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.

FCC WarningThis evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.

EVM WARNINGS AND RESTRICTIONSIt is important to operate this EVM within the input voltage range of 1.8 V to 4.5 V and the output voltage range of 2 Vrms.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 85°C. The EVM is designed to operateproperly with certain components above 85°C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright 2008, Texas Instruments Incorporated

http://www.ti.com/esh

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. 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Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers amplifier.ti.com Audio www.ti.com/audioData Converters dataconverter.ti.com Automotive www.ti.com/automotiveDSP dsp.ti.com Broadband www.ti.com/broadbandClocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrolInterface interface.ti.com Medical www.ti.com/medicalLogic logic.ti.com Military www.ti.com/militaryPower Mgmt power.ti.com Optical Networking www.ti.com/opticalnetworkMicrocontrollers microcontroller.ti.com Security www.ti.com/securityRFID www.ti-rfid.com Telephony www.ti.com/telephonyRF/IF and ZigBee® Solutions www.ti.com/lprf Video & Imaging www.ti.com/video

Wireless www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2008, Texas Instruments Incorporated

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1 Overview1.1 DRV601EVM2 Features1.2 PCB Key Map

2 Quick Setup Guide2.1 Electrostatic Discharge Warning2.2 Unpacking the EVM2.3 Power Supply Setup

3 Shutdown4 Component Selection4.1 Charge Pump4.2 Decoupling Capacitors4.3 Using the DRV601 as a Second-Order Low-Pass Filter

5 Layout Recommendations5.1 Exposed Pad on the DRV601RJT Package5.2 SGND and PGND Connections

6 DRV601EVM2 Performance6.1 THD+N vs Voltage (Analog Input)6.2 THD+N vs Voltage (Digital Input)6.3 THD+N vs Frequency6.4 FFT Spectrum With –60 dBFS Tone6.5 Idle Noise FFT Spectrum6.6 Channel Separation6.7 Frequency Response6.8 Pop/Click (Enable)6.9 Pop/Click (Disable)

7 Related Documentation from Texas Instruments8 Design Documentation8.1 DRV601EVM2 Schematic8.2 Parts List8.3 PCB Specifications8.4 PCB Layout

Important Notices

drv601evm2 user's guideuser's guide slou217–march 2008 drv601evm2 this user’s guide describes...

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