dsd lab manual aitd

7/28/2019 DSD Lab Manual Aitd

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Expt No 1

Aim - The purpose of this experiment is to introduce you to the basics of circuit wiring,troubleshooting, positive/negative logic, threshold voltages, clock, delay concepts, and gate

behavior. In this lab, you will test the behavior of several of the basic logic gates and you willconnect several logic gates to create simple circuits and verify their truth table.

Requirements:

Power Supply (Figure L1.1a): All active electronic devices such as the integrated circuitsused in digital electronics require a stable source of DC voltage to function properly. The

power supply provides the proper level of dc voltage. It is very important that the correctvoltage be set before connecting it to the ICs on your board or permanent damage can result.The power supply at your bench may have

more than one output and normally will have a built in meter to help you set the voltage.Usually for all circuits power supply should be set to +5.0 V.Digital Multimeter (Figure L1.1b): the DMM is a multipurpose measuring instrument thatcombines in one instrument the characteristics of a dc and ac voltmeter, a ac and dc ammeter and ohmmeter. The DMM indicates the measured quantity as a digital number, avoiding thenecessity to interpret the scales as was necessary on older instruments. You need to select thedesired function by the switch provided. For current measurements a separate set of leadconnections are made to the meter. The ohmmeter function of a DMM is used only in circuitsthat are not powered.Function Generator (Figure L1.1c): A function generator is used to produce signals requiredfor testing various kinds of circuits. For digital circuits, a periodic rectangular pulse is the

basic signal used for testing logic circuits. It is important that proper voltage be set up beforeconnecting the function generator to the circuit or else damage may occur. Functiongenerators normally have controls for adjustingthe peak amplitude of a signal and may also have a means of adjusting the 0 volt level.Oscilloscope (Figure L1.1d): The oscilloscope is the most important test instrument for testing circuits and you should become completely familiar with its operations. Its a versatiletest instrument letting you see a graph of the voltage as a function of time in a circuit andcompare waves. Because an oscilloscope allows you to measure various parameters, it isconsidered to be an instrument capable of parametric measurements important in both digitaland analog work. Nearly all complex digital circuits have specific timing requirement thatcan be readily measured with a two channel oscilloscope. There are two basic types of oscilloscope; analog and digital. Both types of scopes have four main control groups: displaycontrols, vertical and horizontal control and trigger controls.Circuit board (protoboards): Circuit boards are convenient way to construct circuit for testing and experimenting. Most of them look like the one shown in the figure L1.2 . You willnotice the top and bottom horizontal rows are connected as a continuous row. Vertical groupsof five holes are connected together; the vertical group above the center strip is not connectedto vertical group below the center strip.The holes are 0.1 inch apart, which is the same spacing as the pins on an integrated circuitDIP (Dual In-line Pins). Integrated circuits (ICs) are inserted to straddle the center; in thismanner, wires can be connected to the pins of the IC by connecting them to the same verticalgroup as the desired pin.


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Fig. L 1.1 Instruments

Fig. L 1.2 Breadboard

APPARATUS REQUIRED:


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THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has

one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR

and X-OR are known as universal gates. Basic gates form these gates.

AND GATE:

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the

inputs is low.

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The

output is high when any one of the inputs is high. The output is low level when both the

inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The

output is low when the input is high.

NAND GATE:

Sr No. COMPONENT SPECIFICATION QTY1. AND GATE IC 7408 12. OR GATE IC 7432 1

3. NOT GATE IC 7404 14. NAND GATE 2 I/P IC 7400 15. NOR GATE IC 7402 16. X-OR GATE IC 7486 17. NAND GATE 3 I/P IC 7410 18. IC TRAINER KIT - 19. PATCH CORD - 14


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The NAND gate is a contraction of AND-NOT. The output is high when both inputs

are low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are

low. The output is low when one or both inputs are high .

X-OR GATE:

The output is high when any one of the inputs is high. The output is low when both

the inputs are low and both the inputs are high.

PROCEDURE: (i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

AND GATE:

SYMBOL: PIN DIAGRAM:


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OR GATE:

NOT GATE:


X-OR GATE :

SYMBOL : PIN DIAGRAM :


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2-INPUT NAND GATE:



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3-INPUT NAND GATE :

NOR GATE:


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3 Input AND-

7420 Dual Four Input NAND Gate


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7421 Dual Four Input AND Gate

7427 Triple Input NOR Gate

Result: The different ICs were studied and their truth table were verified.


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EXPT NO: 2

DESIGN OF ADDER AND SUBTRACTOR

AIM:To design and construct half adder, full adder, half subtractor and full subtractor

circuits and verify the truth table using logic gates.

THEORY:HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the

sum S and other from the carry c into the higher adder position. Above circuit is call ed as

a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry

out from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it

consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a

half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output

will be taken from OR Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has

two input and two outputs. The outputs are difference and borrow. The difference can be

applied using X-OR Gate, borrow output can be implemented using an AND Gate and an

inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full

subtractor the logic circuit should have three inputs and two outputs. The two half subtractor

put together gives a full subtractor .The first half subtractor will be C and A B. The output


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will be difference output of full subtractor. The expression AB assembles the borrow output

of the half subtractor and the second term is the inverted difference output of first X-OR.

LOGIC DIAGRAM:

HALF ADDER

TRUTH TABLE:

A B CARRY SUM0011

0101

0001

0110

K-Map for SUM: K-Map for CARRY:

SUM = AB + AB CARRY = AB

LOGIC DIAGRAM:

FULL ADDER FULL ADDER USING TWO HALF ADDER


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TRUTH TABLE:

A B C CARRY SUM

00001111

00110011

01010101

00010111

01101001

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

K-Map for CARRY:


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CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0011

0101

0100

0110

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB

K-Map for BORROW:


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BORROW = AB

LOGIC DIAGRAM:FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:


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TRUTH TABLE:A B C BORROW DIFFERENCE

00001111

00110011

01010101

01110001

01101001

K-Map for Difference:

Difference = ABC + ABC + ABC + ABC

K-Map for Borrow:


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Borrow = AB + BC + AC

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.1. AND GATE IC 7408 12. X-OR GATE IC 7486 13. NOT GATE IC 7404 14. OR GATE IC 7432 13. IC TRAINER KIT - 14. PATCH CORDS - 23

PROCEDURE:(i) Connections are given as per circuit diagram.



RESULT:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER


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AIM: To design and implement multiplexer and demultiplexer using logic gates and study of IC 74151, 74153 and IC 74155.

THEORY:

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects

binary information from one of many input lines and directs it to a single output line. The

selection of a particular input line is controlled by a set of selection lines. Normally there are

2n input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines. For this reason,

the demultiplexer is also known as a data distributor. Decoder can also be used as

demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The

data select lines enable only one gate at a time and the data on the data input line will pass

through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y


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0 0 D0 D0 S1 S0

0 1 D1 D1 S1 S0

1 0 D2 D2 S1 S0

1 1 D3 D3 S1 S0

Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1


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1 0 D2

1 1 D3

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X D0 = X S1 S0

0 1 X D1 = X S1 S0

1 0 X D2 = X S1 S0

1 1 X D3 = X S1 S0

Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:


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TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74153:


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APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 22. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. 4:1 MUX IC 74153 1

5. 8:1 MUX IC 74151 1

6. 8:1 DEMUX IC 74155 1

7. PATCH CORDS - 32

PROCEDURE:

(i) Connections are given as per circuit diagram.



RESULT:


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FLIPFLOPS

AIM: To study the working of R-S, J-K, D and T flip-flops.

Requirements : Breadboard, Power supply, logic gates ICs 7400, 7402, 7476, LED.

Theory:

Flip-flops are the basic building blocks of sequential ckt. The clocked FFs change their o/pstate depending upon i/p's at certain interval of time synchronized with the clock pulseapplied to it. Different types of FFs are S-R, J-K, D & T . Their operations are described bythe respective truth tables. MSI chip 7476 incorporates two negative edge triggered Master Slave JK flipflops. The J-K flipflop can be converted to D & T flipflop.

Circuit Diagram:

S-R Flipflop using NAND gate

J-K Flipflop using IC 7476


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T Flipflop using IC 7476

D Flipflop using IC 7476


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PROCEDURE:

(i) Connections are given as per circuit diagram.



Conclusion

Result

SHIFT REGISTERS

AIM: To realize and study of Shift Register.

1) SISO (Serial in Serial out)

2) SIPO (Serial in Parallel out)

3) PIPO (Parallel in Parallel out)

4) PISO (Parallel in Serial out)

COMPONENTS REQUIRED: IC 7474 D Flipflop, Patch Cords.

Theory-

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop

cascaded with output of one flip flop connected to input of next flip flop. All flip flopsreceive common clock pulses which causes the shift in the output of the flip flop. The

simplest possible shift register is one that uses only flip flop. The output of a given flip flop is

connected to the input of next flip flop of the register. Each clock pulse shifts the content of

register one bit position to right.

Pin Description


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Pin Diagram & Circuit Diagram

7474 - Dual D Flip-Flop with Preset and Clear

Fig. 7474 Dual D Flipflop with Preset & Clear

1) SERIAL IN SERIAL OUT (SISO) (Right Shift)

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0

2 0 0

number

1 Clear 1 Input

2 D1 Input

3 Clock 1 input

4 Preset 1 input5 Q1 output

6 Complement Q1 output

7 Ground

8 Complement Q2 output

9 Q2 output

10 Preset 2 input

11 Clock 2 input

12 D2 input

13 Clear 2 input

14 Power supply


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3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:

CLK DATA

OUTPUT

Q A Q B Q C Q D

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1


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LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:


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TRUTH TABLE:

CLK

DATA INPUT OUTPUT

DA DB DC DD Q A Q B Q C Q D

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE:

Check all the components for their working.

Insert the appropriate IC into the IC base.

Make connections as shown in the circuit diagram.

Verify the Truth Table and observe the outputs.


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AGNEL INSTITUTE OF TECHNOLOGY

AND DESIGN

ASSAGAO, BARDEZ, GOA- 403507


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ECE TIME-TABLE FILE

2013-2014

HOD: Prof. Laxmikant Bordekar

Time-table incharge: Prof. Shrinivas Joshi

dsd lab manual aitd

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