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DEPARTMENT OF Electronics and Communication Engineering

COURSE PLAN

Department : Electronics and Communication Engg

Subject : DSD HDL (ECE 206)

Semester & branch : IV ECE

Name of the faculty : GP, SD, SKT

No of contact hours/week : 4 hours/week

Assignment portionAssignment no. Topics

1 L1 L16

2 L17 L34

3 L35 L50

Test portion

Test no. Topics

1 L1 L22

2 L23 L43

Submitted by: Mr.Guruprasad

(Signature of the faculty)Date:

Approved by:

(Signature of HOD)Date:

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MANIPAL INSTITUTE OF TECHNOLOGY(A constituent college of Manipal University, Manipal)

Manipal Karnataka 576 104

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At the end of this course, the student will be able to:

CO1: Discuss the architecture of hardware programmable devices like

PLDs, PLAs and PALs.

CO2: Describe the types of ASIC and their design methodologies.

CO3: Discuss the architectural features of FPGAs

CO4: Design digital circuits using FPGAs

CO5: Discuss various testing methodologies employed in digital design

CO6: Perform testing of designed module - both combinational and sequential

circuits.

CO7: Write and analyze the VHDL code for given design using structural, data

flow and behavioral modeling styles and compare them.

CO8: Write and analyze programs for test benches for the given design using

VHDL.

L.No.Topics

L1 Digital System implementation using ROMs and PROMs.

L2 Digital System implementation using PLAs

L3 Digital System implementation using PLAs

L4 Digital System implementation using PALs

L5 Full-custom, semi-custom, standard cell based.

L6 Programmable ASICs PLDs, CPLDs, MPGAs, FPGAs and ASIC design

flow.

L 7 ACTEL- logic modules and Implementation of digital circuits using

ACTEL logic modules

L 8 Implementation of digital circuits using ACTEL logic modules

L 9 XILINX- logic module and digital circuits using XILINX logic modules

L10 ALTERA- logic module and Implementation of digital circuits using

ALTERA logic modules

L11 Programming Technology: anti fuse, SRAM and EPROM

L12 Programmable I/O cells.

L13 Programmable Interconnect of ACTEL ACT

L14 Programmable Interconnect of Xilinx LCA and ALTERA Max 9000

L15 Testing Combinational Circuit:-Fault Table with examples

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L16 Boolean difference method with properties.

L 17 Path Sensitization with examples and its failure.

L18 D-Algorithm- Introduction to D-Cubes, D-algebra,

L19 D-Algorithm fault propagation with examples.

L20 PODEM with example

L 21 Fault-collapsing techniqueL22 Observability and controllability

L23 Testing sequential circuits: sequential test methods, iterative test generator

L24 Design-for-test(DFT) methods: DFT guidelines for combinational circuits

L25 Critical path ,DFT methods like scan path, Boundary scan etc.

L26 DFT methods like Signature Analysis, BILBO and BIDCO.

L27 Y-chart, Different domains and levels of abstractions

L28 Types of synthesis, steps involved in synthesis, Digital modeling using

HDLs.

L29 VHDL modeling concepts-syntax, entities and architectures

L 30 VHDL object types, Data types: scalar data types with examples,

Composite Data types with examples.

L 31 File data types with examples, Access data types with examples.

L 32 Behavioral Modeling: process statement, sequential statements-if, case,

loop, next, exit, assert, wait, null. Examples

L 33 Behavioral Modeling examples of Combinational circuits - Full-adder,

Full-Subtractor, MUX, DEMUX, Encoder, D-FF, JKFF, State machines.

L 34 Behavioral Modeling examples of sequential circuits -, D-FF, JKFF, State

machines.

L 35 Structural modeling with examples

L 36 Structural modeling with examples

L 37 Data flow modeling with examples

L 38 Data flow modeling with examples

L 39 Mixed modeling with examples

L40 Procedures with examples.

L41 Functions with examples.

L42 Packages and use clauses Configurations, pre-defined and user defined

attributes

L43 Generics and Test benches

L44 Case studies

L45 Case studies

L46 Introduction to Verilog HDL

L47 Verilog v/s VHDL, behavioral Verilog modeling

L48 Structural and dataflow modeling

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References:

[1]M.J.S.Smith (1997),Application Specific ICs,Addison Wesley.

[2]Alexander Miczo(1987) , Digital logic testing and simulation , John Wiley &Sons.

[3]C.H.Roth (1998) , Digital System Design using VHDL ,PWS.

[4]Peter Ashenden (1996) , The Designers Guide to VHDL,Morgan KaufmannPublisher.

[5]Douglas Perry (1998) , VHDL ,McGraw Hill International.

[6]J.Bhaskar (2002) , VHDL Primer , 3rd

edition, Addison Wesley LongmanSingapore Pvt Ltd.

[7]Samir Palnitkar (2001) , Verilog HDL ,Pearson Education Asia.

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