dsp qns
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Digital signal Processor model qnTRANSCRIPT
M.Tech DEGREE I SEMSTER EXAMINATION IN ELECTRONICS
(SIGNAL PROCESSING) – MODEL PAPER – 2012
SP107 – DIGITAL SIGNAL PROCESSORS
1) a. Explain the concept of circular buffering. List down the steps used to
implement an FIR filter using Digital Signal Processors. (5)
b. With suitable diagrams, explain the features of Harvard and Super
Harvard DSP architectures. (5)
OR
2) a. What is multiprocessing? How is it achieved in high level DSP
applications? (5)
b. Distinguish between fixed point and floating point processors. How will
you choose between a fixed point and a floating point processor for your
applications? (5)
3) a. Briefly describe the architecture of TMS320C55x processors. (5)
b. Explain the pipelining and parallelism achieved in TMS320C55x DSP.
(5)
OR
4) a. Explain the various addressing modes used in TMS320C55x processor.
(5)
b. What is CCS? How is it useful in DSP programming? Demonstrate with a
sample program development. (5)
5) a. Describe the two level internal memory architecture of TMS320C6x.
(5)
b. Explain code improvement. How is it achieved? Discuss the constraints.
(5)
OR
6) a. Explain multichannel buffered serial ports and DMA. (4)
b. Explain how the function of flag in conventional processors is achieved in
TMS320C6x family DSP. (3)
c. Explain the instruction types in TMS320C6x family DSP. Give examples
for each . (3)
7) a. With block diagram explain the memory organization of SHARC
processor and compare with that of TMS3206x family DSP? (5)
b. Explain how multiprocessing is achieved in SHARC processor? Also
explain host interface ? (5)
OR
8) a. Explain link ports in SHARC processor .what are the interrupt types in
this processor? (5)
b. Discuss the various functions of program sequences in a SHARC
processor? (5)
9) a. Explain the hardware and software considerations of a sine wave
generator? (5)