dtx-360 maintenance manual - salvex maintenance.pdf · 92050003-03 i dtx-360 maintenance manual...

DTX-360

D I G I T A L C I R C U I T

M U L T I P L I C A T I O N E Q U I P M E N T

Maintenance Manual

Copyright © ECI Telecom Ltd.1998. All Rights Reserved.

This manual may contain minor flaws, omissions, or typesetting errors. Information contained herein isperiodically updated and changes will be incorporated into subsequent editions. If you have encountered anerror, please notify ECI Telecom. All specifications are subject to change without prior notice.

REVISION RECORD

REVISION DESCRIPTION01 PreliminaryJanuary 199402 First edition and printingJune 199703December 1997 Addition of pages 1-8 to1-11 - Card replacement and card

malfunction detection04March 1998 Changes and additions to pages: 5-6, 5-25, 5-35, 1-11-1-14

Publn No.92050003

CE MARK COMPLIANCE

The DTX-360 is marked with a CE Mark (see below). This mark has been affixed todemonstrate full product compliance with the following European directives:

a) Directive 73/23/EEC - Council Directive of 19/02/1973 on the harmonization of the lawsof Member States relating to electrical equipment designed for use within certain voltagelimits.

b) Directive 89/336/EEC - Council Directive of 3/05/1989 on the approximation of laws ofthe Member States relating to Electro-Magnetic Compatibility (EMC).

Issue date: 6 February 1996

This document contains proprietary information. It may not, in whole or in part, be published, used, orreproduced, nor may be disclosed to third parties without the express written permission of ECI Telecom .

Copyright by ECI Telecom Ltd., 1997All rights reserved worldwide

ECI Telecom reserves the right, without notice, to make changes in equipment design orspecifications.

Information supplied by ECI Telecom is believed to be accurate and reliable. However, noresponsibility is assumed by ECI Telecom for its use nor for rights of third parties which mayresult from its use.

Any representations in this document concerning performance are for informational purposes onlyand are not warranties of future performance, either express or implied. ECI Telecom ’s standardlimited warranty, stated in its sales contract or order confirmation form, is the only warrantyoffered by ECI Telecom .

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DTX-360Maintenance Manual

Table of Contents

Section Description Page

1 GENERAL INFORMATION ..........................................................................1-11.1 INTRODUCTION............................................................................................... 1-11.2 STATIC AWARENESS ..................................................................................... 1-11.3 REPAIR AND RETURN.................................................................................... 1-21.3.1 Order Entry (normal shipping time).................................................................... 1-21.3.2 Terminal Malfunction Report ............................................................................. 1-21.3.3 Order Entry (Emergency Order) ......................................................................... 1-41.3.4 Insurance Policy .................................................................................................. 1-41.3.5 Substitutions and Modifications ......................................................................... 1-41.3.6 Limitations of Liability ....................................................................................... 1-41.4 OPS REPAIR ...................................................................................................... 1-51.5 TASKS AUTHORIZED FOR THE USER......................................................... 1-51.6 HANDLING OF ELECTROSTATICALLY SENSITIVE COMPONENTS ..... 1-51.7 HANDLING PRINTED CIRCUIT BOARDS.................................................... 1-61.8 HANDLING PERIPHERAL EQUIPMENT AND TERMINALS ..................... 1-61.9 HANDLING THE OPERATOR STATION....................................................... 1-71.10 AC POWER OUTLETS ..................................................................................... 1-71.11 DETECTING CARD MALFUNCTIONS .......................................................... 1-81.12 DETECTING THE SOURCE OF A CARD MALFUNCTION......................... 1-81.13 CARD REMOVAL UNDER POWER ............................................................. 1-101.14 OMCP/COCP CARD REPLACEMENT.......................................................... 1-111.14.1 Modifying the ethers file................................................................................... 1-111.14.2 Modifying the hosts file .................................................................................... 1-121.14.3 Modifying the config file .................................................................................. 1-121.14.4 Modifying the pofInfo_am file.......................................................................... 1-121.14.5 Resuming Operation.......................................................................................... 1-121.15 TO TURN A TERMINAL OFF........................................................................ 1-131.15.1 Stand Alone Configuration ............................................................................... 1-131.15.2 Cluster configuration......................................................................................... 1-13

2 INTERNAL AND CLUSTER CABLE CONNECTIONS.............................2-1

2.1 GENERAL .......................................................................................................... 2-12.2 TERMINAL - LCOM CONNECTIONS ............................................................ 2-22.2.1 Bitstream Connection.......................................................................................... 2-22.3 LCOM - CCOM CONNECTIONS (FIGURES 2-2 AND 2-3)........................... 2-42.3.1 DLC Connections................................................................................................ 2-42.3.2 BitstreamConnections ......................................................................................... 2-42.4 CCOM - REDUNDANT TERMINAL CONNECTIONS (FIGURES 2-4, 2-5). 2-72.4.1 Bitstream Connections ........................................................................................ 2-72.4.2 DLC Connections................................................................................................ 2-72.4.3 LCOM - Four (4) Compact Terminals Connections (DTX-360C ) ................. 2-102.4.3.1 Bitstream Connections ...................................................................................... 2-102.4.3.2 DLC Connections.............................................................................................. 2-10

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2.4.4 SCOM - Three (3) Compact Terminals + Redundant TerminalConnections (DTX-360C)................................................................................. 2-12

2.4.4.1 Bitstream Connections ...................................................................................... 2-122.4.4.2 DLC Connections.............................................................................................. 2-122.4.5 SCOM + Two (2) Terminals + Redundant Terminal Connections................... 2-142.4.5.1 Bitstream Connections ...................................................................................... 2-142.4.5.2 DLC Connections.............................................................................................. 2-14

3 TRANSMISSION ALARMS............................................................................3-13.1 2.048 MBIT/S E1 TRANSMISSION ALARMS DESCRIPTION ..................... 3-13.1.1 Loss of Incoming Signal (LOS) .......................................................................... 3-13.1.2 Alarm Indication Signal (AIS) ............................................................................ 3-13.1.3 Loss of Alignment (LOF) Alarm ........................................................................ 3-23.1.4 CRC Multiframe (CRC MFR) ............................................................................ 3-23.1.5 High CRC Error .................................................................................................. 3-23.1.6 High Bit Error Rate (H.BER).............................................................................. 3-33.1.6.1 H.BER, Bitstream with the CRC Format ............................................................ 3-33.1.6.2 H.BER, Bitstream without CRC Format............................................................. 3-33.1.7 Low Bit Error Rate (L.BER)............................................................................... 3-33.1.7.1 L.BER, Bitstream without CRC Format ............................................................. 3-33.1.7.2 L.BER, Bitstream with the CRC Format ............................................................ 3-33.1.8 Remote (Far-end) Alarm Indication (RAI) ......................................................... 3-33.1.9 Multiframe Alignment (MFR) ............................................................................ 3-43.1.10 Remote Multiframe Alarm Indication (RMFR).................................................. 3-43.1.11 High Slip Rate (H.SLIP) ..................................................................................... 3-43.1.12 Low Slip Rate (L.SLIP) ...................................................................................... 3-43.1.13 No External Clock Alarm.................................................................................... 3-43.1.14 Bitstream or External Clock Fail ........................................................................ 3-53.1.15 DCME Frame Alarm (DFA) ............................................................................... 3-53.1.16 CC-HBER............................................................................................................ 3-53.1.16.1 Activation Criteria............................................................................................... 3-53.1.16.2 Deactivation Criteria ........................................................................................... 3-53.1.17 CC-LBER............................................................................................................ 3-53.1.17.1 Activation Criteria............................................................................................... 3-53.1.17.2 Deactivation Criteria ........................................................................................... 3-63.1.18 CC-AIS................................................................................................................ 3-63.1.19 Bearer Backward Alarm...................................................................................... 3-63.1.20 Far-End (Remote) Trunk Alarm.......................................................................... 3-63.2 1.544 MBIT/S T1 TRANSMISSION ALARMS DESCRIPTION ..................... 3-73.2.1 Loss Of Frame alignment (LOF - CFA)............................................................ 3-73.2.2 Loss Of incoming Signal (LOS) ........................................................................ 3-73.2.3 Alarm Indication Signal (AIS-CFA) ................................................................... 3-73.2.4 High Bit Error Rate (HBER).............................................................................. 3-83.2.5 Remote (Far-end, Distant) Alarm Indication (RAI) - (Yellow)............................ 3-83.2.6 Low Bit Error Rate (LBER).............................................................................. 3-93.3 MAINTENANCE LEVELS OF TRANSMISSION ALARMS AND

EVENTS (E1 SYSTEM) .................................................................................. 3-10

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3.4 Maintenance Levels of TransmissionAlarms (T1 System) .......................................................................................... 3-13

3.4.1 Change Clock Alarm Severity........................................................................... 3-133.5 TRANSMISSION ALARM HANDLING........................................................ 3-14

4 SYSTEM ALARMS AND EVENTS................................................................4-1

4.1 SYSTEM EVENTS............................................................................................. 4-14.2 CCOM EVENTS................................................................................................. 4-34.3 OPS ACTIONS ................................................................................................... 4-44.4 DTX-360 RESPONSES TO OPS ACTIONS ..................................................... 4-64.5 ONLINE BIT TESTS.......................................................................................... 4-94.5.1 SIGN Hardware Online Test Options ................................................................. 4-94.5.1.1 MFR Trunk (0:15)............................................................................................... 4-94.5.1.2 TRUNK OUT Path Test...................................................................................... 4-94.5.1.3 CLEAR CHANNEL TRANSMITTER (transparent signaling)......................... 4-94.5.1.4 CLEAR CHANNEL RECEIVER ....................................................................... 4-94.5.1.5 TRUNK IN Path Test.......................................................................................... 4-94.5.1.6 SIGN Loop Back Test ......................................................................................... 4-94.5.2 AUXC ONLINE BIT ........................................................................................ 4-104.5.2.1 DSP TEST......................................................................................................... 4-104.5.2.2 PPI TEST .......................................................................................................... 4-104.5.2.3 PEB TX TEST .................................................................................................. 4-104.5.2.4 PEB RX TEST .................................................................................................. 4-104.5.2.5 AUXC 188EC ONLINE EPROM CHECK SUM............................................. 4-104.5.2.6 AUXC 188EC ONLINE FLASH CHECK SUM.............................................. 4-104.5.2.7 AUXC 188EC ONLINE RAM CHECK........................................................... 4-104.5.2.8 AUXC ONLINE INTERRUPT TEST .............................................................. 4-104.5.2.9 AUXC 188EC ONLINE TIMER TEST............................................................ 4-104.5.3 AUXC 188EC ONLINE HDLC TEST ............................................................. 4-114.5.3.1 AUXC 188EC ONLINE DMA TEST............................................................... 4-114.5.3.2 AUXC 188C ONLINE PORT TEST ................................................................ 4-114.5.4 SCPU 188EC ONLINE BIT.............................................................................. 4-124.5.4.1 SCPU ONLINE EPROM CHECK SUM .......................................................... 4-124.5.4.2 SCPU ONLINE FLASH CHECK SUM ........................................................... 4-124.5.4.3 SCPU ONLINE RAM CHECK ........................................................................ 4-124.5.4.4 SCPU ONLINE INTERRUPT TEST................................................................ 4-124.5.4.5 SCPU ONLINE TIMER TEST......................................................................... 4-124.5.4.6 SCPU ONLINE HDLC TEST........................................................................... 4-124.5.4.7 SCPU ONLINE DMA TEST ............................................................................ 4-124.5.4.8 SCPU ONLINE PORT TEST ........................................................................... 4-124.5.5 BMCT ONLINE BIT ........................................................................................ 4-134.5.5.1 GENERAL ........................................................................................................ 4-134.5.5.2 TEST CIRCUIT ................................................................................................ 4-134.5.5.3 CONTROL MEMORIES WRITE READ: ....................................................... 4-134.5.5.4 BRT BMCT TS0:.............................................................................................. 4-134.5.5.5 BMRT BMCT BARKER:................................................................................. 4-134.5.5.6 FAX OUT & VBR CONTROL MEMORY: .................................................... 4-13

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4.5.5.7 BCMODT#N TS0 ............................................................................................. 4-134.5.5.8 BMCT ONLINE EPROM CHECK SUM......................................................... 4-134.5.5.9 BMCT ONLINE RAM CHECK....................................................................... 4-134.5.5.10 BMCT ONLINE FLASH CHECK SUM.......................................................... 4-134.5.5.11 BMCT ONLINE INTERRUPT TEST .............................................................. 4-144.5.5.12 BMCT ONLINE TIMER TEST........................................................................ 4-144.5.5.13 BMCT ONLINE HDLC TEST ......................................................................... 4-144.5.5.14 BMCT ONLINE DMA TEST........................................................................... 4-144.5.5.15 BMCT ONLINE PORT TEST.......................................................................... 4-144.5.6 BMCR CPU ONLINE TEST ............................................................................ 4-154.5.6.1 GENERAL ........................................................................................................ 4-154.5.6.2 CONTROL MEMORIES WRITE READ ........................................................ 4-154.5.6.3 BCBSR#N TS0 ................................................................................................. 4-154.5.6.4 BCMDR#N TS0................................................................................................ 4-154.5.6.5 FAXBSR#N TS0............................................................................................... 4-154.5.6.6 BMCR ONLINE EPROM CHECK SUM......................................................... 4-154.5.6.7 BMCR ONLINE RAM CHECK....................................................................... 4-154.5.6.8 BMCR ONLINE FLASH CHECK SUM.......................................................... 4-154.5.6.9 BMCR ONLINE INTERRUPT TEST.............................................................. 4-154.5.6.10 BMCR ONLINE TIMER TEST ....................................................................... 4-164.5.6.11 BMCR ONLINE HDLC TEST......................................................................... 4-164.5.6.12 BMCR ONLINE DMA TEST........................................................................... 4-164.5.6.13 BMCR ONLINE PORT TEST.......................................................................... 4-164.5.7 CKSL ONLINE BIT SPECIFICATIONS......................................................... 4-174.5.7.1 PPI DATA BUS TEST...................................................................................... 4-174.5.7.2 CKSL 12V TEST.............................................................................................. 4-174.5.7.3 PLL LOCK TEST ............................................................................................. 4-174.5.7.4 TIMING TEST.................................................................................................. 4-174.5.8 XDSP ONLINE BIT (SDSP/TDSP/RDSP) ...................................................... 4-184.5.8.1 GENERAL ........................................................................................................ 4-184.5.8.2 SDSP ODD CELL TEST.................................................................................. 4-184.5.8.3 XDSP HDLC PORT ......................................................................................... 4-184.5.8.4 XDSP DSP_RES1 PORT.................................................................................. 4-184.5.8.5 XDSP DSP_RES2 PORT.................................................................................. 4-184.5.8.6 XDSP BS CM DATA TEST............................................................................. 4-184.5.8.7 XDSP DSP CELL 0-15 TEST .......................................................................... 4-184.5.8.8 188EC ONLINE EPROM CHECK SUM......................................................... 4-184.5.8.9 188EC ONLINE FLASH CHECK SUM .......................................................... 4-184.5.8.10 188EC ONLINE RAM CHECK ....................................................................... 4-194.5.8.11 188EC ONLINE INTERRUPT TEST .............................................................. 4-194.5.8.12 188EC ONLINE TIMER TEST........................................................................ 4-194.5.8.13 188EC ONLINE HDLC TEST ......................................................................... 4-194.5.8.14 188EC ONLINE DMA TEST........................................................................... 4-194.5.8.15 188C ONLINE PORT TEST............................................................................. 4-194.5.8.16 TDSP CELL TEST ........................................................................................... 4-194.5.8.17 FDSP CELL TEST............................................................................................ 4-194.5.8.18 RDSP ODD CELLS TEST ............................................................................... 4-20

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4.5.9 XCPU ONLINE TEST...................................................................................... 4-214.5.9.1 XCPU ONLINE EPROM CHECK SUM ......................................................... 4-214.5.9.2 XCPU ONLINE RAM CHECK........................................................................ 4-214.5.9.3 XCPU ONLINE FLASH CHECK SUM........................................................... 4-214.5.9.4 XCPU ONLINE INTERRUPT TEST............................................................... 4-214.5.9.5 XCPU ONLINE TIMER TEST ........................................................................ 4-214.5.9.6 XCPU ONLINE HDLC TEST.......................................................................... 4-214.5.9.7 XCPU ONLINE DMA TEST ........................................................................... 4-214.5.9.8 XCPU ONLINE PORT TEST........................................................................... 4-214.5.10 OMCP ONLINE TEST ..................................................................................... 4-224.5.10.1 OMCP ONLINE EPROM CHECK SUM......................................................... 4-224.5.10.2 OMCP ONLINE RAM CHECK ....................................................................... 4-224.5.10.3 OMCP ONLINE FLASH CHECK SUM.......................................................... 4-224.5.10.4 OMCP ONLINE INTERRUPT TEST .............................................................. 4-224.5.10.5 OMCP ONLINE TIMER TEST........................................................................ 4-224.5.10.6 OMCP ONLINE HDLC TEST ......................................................................... 4-224.5.10.7 OMCP ONLINE DMA TEST........................................................................... 4-224.5.10.8 OMCP ONLINE LAN CONTROLLER TEST................................................. 4-224.5.10.9 OMCP ONLINE REAL TIME CLOCK TEST ................................................ 4-224.5.10.10 OMCP ONLINE POWER FAILURE TEST .................................................... 4-234.5.10.11 OMCP ONLINE PORT TEST.......................................................................... 4-234.5.11 DSIT TEST DESCRIPTION............................................................................. 4-244.5.11.1 GENERAL ........................................................................................................ 4-244.5.11.2 DSIT T_PPI TEST ............................................................................................ 4-244.5.11.3 DSIT XILINX TEST......................................................................................... 4-244.5.11.4 DSIT 12 TEST .................................................................................................. 4-244.5.11.5 DSIT PLL TEST ............................................................................................... 4-244.5.11.6 ACFA TEST (Alarm Simulation) ..................................................................... 4-244.5.11.7 TS0 PATTERN GENERATOR TEST ............................................................. 4-244.5.11.8 DSIT INPUT BITSTREAMS TEST................................................................. 4-244.5.11.9 DSIT ENC2BC MATRIX TEST ...................................................................... 4-244.5.12 DSIT ENC2BC MATRIX INPUT BITSTREAMS BIT................................... 4-254.5.12.1 DSIT MODE MATRIX TEST.......................................................................... 4-254.5.12.2 DSIT MODE MATRIX INPUT BS TEST (TS0 TEST) .................................. 4-254.5.12.3 DSIT DMUX CM TEST................................................................................... 4-254.5.12.4 DSIT TDSI1 MATRIX TEST........................................................................... 4-254.5.12.5 DSIT TDSI2 MATRIX TEST........................................................................... 4-254.5.12.6 DSIT SHORT DELAY MEMORY TEST........................................................ 4-254.5.12.7 DSIT LONG DELAY MEMORY TEST.......................................................... 4-254.5.12.8 DSIT SIGNAL GENERATOR TEST............................................................... 4-254.5.12.9 DSIT FPD (FAX PATTERN DETECTOR) TEST .......................................... 4-254.5.12.10 DSIT SMAT TS0 TEST ................................................................................... 4-254.5.13 ADPC ONLINE GENERIC DESCRIPTION ................................................... 4-264.5.13.1 DPR Test ........................................................................................................... 4-264.5.13.2 Output Ports Test .............................................................................................. 4-264.5.13.3 PLL Lock Test................................................................................................... 4-264.5.13.4 Test For The Codecs BIT Machine................................................................... 4-26

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4.5.13.5 Codecs Built-in Test.......................................................................................... 4-264.5.13.6 ADPC Bitstream Test (TS0 Test) ..................................................................... 4-274.5.14 QDLI ONLINE BIT DESCRIPTION ............................................................... 4-284.5.14.1 GENERAL ........................................................................................................ 4-284.5.14.2 PPI TEST .......................................................................................................... 4-284.5.14.3 QDLI ACFA DATA BUS TEST ...................................................................... 4-284.5.14.4 QDLI Xilinx REGISTERS TEST ..................................................................... 4-284.5.14.5 QDLI LIU OSL TEST....................................................................................... 4-284.5.14.6 QDLI ACFA PARITY CHECK........................................................................ 4-284.5.14.7 QDLI LOCAL TS0 PATTERN GENERATOR TEST..................................... 4-284.5.14.8 QDLI OUTPUT BITSTREAM TESTS ............................................................ 4-284.5.14.9 QDLI INPUT BITSTREAM TEST .................................................................. 4-284.5.14.10 QDLI LOOP BACK TEST ............................................................................... 4-284.5.15 RDSW TEST..................................................................................................... 4-304.5.16 TSDF ONLINE BIT DESCRIPTION............................................................... 4-31 4.5.16.1 GENERAL ........................................................................................................ 4-314.5.16.2 TSDF PPI TEST................................................................................................ 4-314.5.16.3 TSDF ACFA TEST (ALARM SIMULATION)............................................... 4-314.5.16.4 TSDF LOCAL TS0 GENERATOR TEST ....................................................... 4-314.5.16.5 TSDF MATRIX TEST DESCRIPTION........................................................... 4-324.5.16.6 TSDF MATRIX SYNC TEST.......................................................................... 4-324.5.16.7 TSDF MATRIX CM TEST .............................................................................. 4-324.5.16.8 TSDF MATRIX SWITCH TEST ..................................................................... 4-324.5.16.9 TSDF MATRIX INPUT BS TEST................................................................... 4-324.5.16.10 TSDF MATRIX DEVICES .............................................................................. 4-324.5.17 DSIR ONLINE BIT DESCRIPTION................................................................ 4-334.5.17.1 GENERAL ........................................................................................................ 4-334.5.17.2 DSIR R_PPI TEST............................................................................................ 4-334.5.17.3 DSIR XILINX TEST ........................................................................................ 4-334.5.17.4 DSIR 12 TEST .................................................................................................. 4-334.5.17.5 DSIR PLL TEST............................................................................................... 4-334.5.17.6 ACFA TEST (Alarm Simulation) ..................................................................... 4-334.5.17.7 TS0 PATTERN GENERATOR TEST ............................................................. 4-334.5.17.8 DSIR INPUT BITSTREAMS TEST................................................................. 4-334.5.17.9 DSIR RDSI MATRIX TEST ............................................................................ 4-334.5.17.10 DSIR MDSW MATRIX TEST......................................................................... 4-334.5.17.11 DSIR MDSW MATRIX TEST INPUT BITSTREAMS TEST........................ 4-344.5.17.12 DSIR INLV MATRIX TEST............................................................................ 4-344.5.17.13 DSIR INLV MATRIX INPUT BS TEST (TS0 TEST) .................................... 4-344.5.17.14 DSIR RDSP INPUT BS TEST (RDSP EVEN CELL TEST)........................... 4-344.5.17.15 DSIR ADPC-RX INPUT BITSTREAMS TEST .............................................. 4-344.5.17.16 DSIR TSDF INPUT BITSTREAMS TEST...................................................... 4-344.5.17.17 DSIR “TEST-DSP” TEST ................................................................................ 4-344.6 BUILT-IN TEST DIAGNOSTICS.................................................................... 4-35

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5 JUMPER SETTINGS .......................................................................................5-15.1 DTX - 360 TERMINAL, CARD LAYOUT ....................................................... 5-15.2 DTX - 360C COMPACT TERMINAL, CARD LAYOUT ................................ 5-15.3 DTX - 360 TERMINAL, LIST OF CARD JUMPER SETTINGS..................... 5-25.4 AUXC ................................................................................................................. 5-35.4.1 AUXC Jumper Settings....................................................................................... 5-35.4.2 AUXC Hard Wired ............................................................................................. 5-35.4.3 AUXC Location of Jumpers ............................................................................... 5-35.5 ADPC & ADPX .................................................................................................. 5-45.5.1 ADPC & ADPX Jumper Settings - None............................................................ 5-45.5.2 ADPC & ADPX Hard Wired .............................................................................. 5-45.5.3 ADPC & ADPX Location of Jumpers ................................................................ 5-45.6 CPU..................................................................................................................... 5-55.6.1 CPU Jumper Settings .......................................................................................... 5-55.6.2 CPU Hard Wired................................................................................................. 5-55.6.3 CPU DIP Switch (U72) Settings ......................................................................... 5-55.6.4 CPU Location of Jumpers and DIP Switches ..................................................... 5-55.7 OMCP ................................................................................................................. 5-65.7.1 OMCP Jumper Settings....................................................................................... 5-65.7.2 OMCP Hard Wired ............................................................................................. 5-65.7.3 OMCP DIP Switch (U51) Settings ..................................................................... 5-65.7.4 OMCP Location of Jumpers and DIP Switches.................................................. 5-65.8 BPIF/1 ................................................................................................................. 5-75.8.1 BPIF /1 Jumper Settings...................................................................................... 5-75.8.2 BPIF /1 Hard Wired - None ................................................................................ 5-75.8.3 BPIF /1 Location of Jumpers and DIP Switches................................................. 5-75.8.4 BMCT ................................................................................................................. 5-75.8.5 BMCT Jumper Settings....................................................................................... 5-75.8.6 BMCT Hard Wired - None ................................................................................. 5-85.8.7 BMCT DIP Switch SW1 Settings ....................................................................... 5-85.8.8 BMCT Location of Jumpers and DIP Switches.................................................. 5-85.8.9 DSP ..................................................................................................................... 5-85.8.10 DSP Jumper Settings........................................................................................... 5-85.8.11 DSP Hard Wired - None ..................................................................................... 5-85.8.12 DSP DIP Switch (U102) Settings ....................................................................... 5-95.8.13 DSP Location of Jumpers and DIP Switches...................................................... 5-95.9 RDSW ............................................................................................................... 5-105.9.1 RDSW Jumper Settings..................................................................................... 5-105.9.2 RDSW Hard Wired - None ............................................................................... 5-105.9.3 RDSW Location of Jumpers and DIP Switches................................................ 5-105.10 QDLI ................................................................................................................. 5-115.10.1 QDLI Jumper Settings....................................................................................... 5-115.10.2 QDLI Hard Wired - None ................................................................................. 5-125.10.3 QDLI DIP Switch (U43) Settings ..................................................................... 5-125.10.4 QDLI Location of Jumpers and DIP Switches.................................................. 5-125.10.5 QDLI Rev. E Jumper Settings........................................................................... 5-13

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5.10.6 QDLI REV. E Hard Wired................................................................................ 5-145.10.7 QDLI REV.-E DIP Switch (U75) Settings........................................................ 5-145.10.8 QDLI REV.-E Location of Jumpers and DIP Switches .................................... 5-145.11 CKSL................................................................................................................. 5-155.11.1 CKSL Jumper Settings...................................................................................... 5-155.11.2 CKSL Hard Wired ............................................................................................ 5-155.11.3 CKSL Location of Jumpers............................................................................... 5-155.12 BPIF/0 ............................................................................................................... 5-165.12.1 BPIF /0 Jumper Settings.................................................................................... 5-165.12.2 BPIF /0 Hard Wired - None .............................................................................. 5-165.12.3 BPIF /0 Location of Jumpers ............................................................................ 5-165.13 SIGN & SIGN/L *............................................................................................. 5-175.13.1 SIGN Jumper Settings....................................................................................... 5-175.13.2 SIGN Hard Wired - None.................................................................................. 5-175.13.3 SIGN Location of Jumpers................................................................................ 5-175.14 TSDF................................................................................................................. 5-185.14.1 TSDF Jumper Settings - None .......................................................................... 5-185.14.2 TSDF Hard Wired............................................................................................. 5-185.14.3 TSDF Location of Jumpers ............................................................................... 5-185.15 BPIF/2 ............................................................................................................... 5-195.15.1 BPIF /2 Jumper Settings.................................................................................... 5-195.15.2 BPIF /2 Hard Wired - None .............................................................................. 5-195.15.3 BPIF /2 Location of Jumpers ............................................................................ 5-195.16 BMCR ............................................................................................................... 5-205.16.1 BMCR Jumper Settings..................................................................................... 5-205.16.2 BMCR Hard Wired - None ............................................................................... 5-205.16.3 BMCR DIP Switch (SW1) Settings .................................................................. 5-205.16.4 BMCR Location of Jumpers and DIP Switches................................................ 5-205.17 BPIF/3 ............................................................................................................... 5-215.17.1 BPIF /3 Jumper Settings.................................................................................... 5-215.17.2 BPIF /3 Hard Wired - None .............................................................................. 5-215.17.3 BPIF /3 Location of Jumpers and DIP Switches............................................... 5-215.18 GDSP................................................................................................................. 5-225.18.1 GDSP Jumper Settings...................................................................................... 5-225.18.2 GDSP Hard Wired - None................................................................................ 5-225.18.3 GDSP DIP Switch (U102) Settings................................................................... 5-225.18.4 GDSP Location of Jumpers and DIP Switches ................................................. 5-225.19 DSIR /L ............................................................................................................. 5-235.19.1 DSIR /L Jumper Settings .................................................................................. 5-235.19.2 DSIR /L Hard Wired - None ............................................................................. 5-235.19.3 DSIR /L Location of Jumpers ........................................................................... 5-235.20 CPU /L .............................................................................................................. 5-245.20.1 CPU /L Jumper Settings.................................................................................... 5-245.20.2 CPU /L DIP Switch (U61) Settings .................................................................. 5-245.20.3 CPU /L Location of Jumpers and DIP Switches............................................... 5-245.21 OMCP /L........................................................................................................... 5-255.21.1 OMCP /L Jumper Settings ................................................................................ 5-25

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5.21.2 OMCP /L Hard Wired....................................................................................... 5-255.21.3 OMCP /L DIP Switch (S2) Settings.................................................................. 5-255.21.4 OMCP /L Location of Jumpers and DIP Switches ........................................... 5-255.22 BMCT /L........................................................................................................... 5-265.22.1 BMCT /L Jumper Settings ................................................................................ 5-265.22.2 BMCT /L Hard Wired - None........................................................................... 5-265.22.3 BMCT /L DIP Switch (SW2) Settings.............................................................. 5-275.22.4 BMCT /L Location of Jumpers and DIP Switches ........................................... 5-275.23 TSDF /L ............................................................................................................ 5-285.23.1 TSDF /L On Circuit Wired (Hard Wired)......................................................... 5-285.23.2 TSDF /L Location of Jumpers .......................................................................... 5-285.24 BMCR /L........................................................................................................... 5-295.24.1 BMCR /L Jumper Settings................................................................................ 5-295.24.2 BMCR /L Hard Wired - None........................................................................... 5-295.24.3 BMCR /L DIP Switch (SW2) Settings.............................................................. 5-295.24.4 BMCR /L Location of Jumpers and DIP Switches ........................................... 5-295.25 DSIT /L ............................................................................................................. 5-305.25.1 DSIT /L Jumper Settings................................................................................... 5-305.25.2 DSIT /L Hard Wired - None ............................................................................. 5-305.25.3 DSIT /L Location of Jumpers ........................................................................... 5-305.26 LDCH REV A ................................................................................................... 5-315.26.1 LDCH Jumper Settings ..................................................................................... 5-315.26.2 LDCH Hard Wired - None............................................................................... 5-315.26.3 LDCH DIP Switch (S2) Settings....................................................................... 5-315.26.4 LDCH Location of Jumpers............................................................................. 5-315.27 LDCH REV B ................................................................................................... 5-325.27.1 LDCH Jumper Settings ..................................................................................... 5-325.27.2 LDCH Hard Wired - None................................................................................ 5-325.27.3 LDCH DIP Switch (S2) Settings- None............................................................ 5-325.27.4 LDCH Location of Jumpers.............................................................................. 5-325.28 CCOM............................................................................................................... 5-335.28.1 CCOM Cards Layout ........................................................................................ 5-335.28.2 CCOM List of Card Jumper Settings............................................................... 5-335.29 CRIO JUMPER SETTINGS ............................................................................. 5-345.29.1 CRIO Hard Wired - None ................................................................................. 5-345.29.2 CRIO Location of Jumpers ............................................................................... 5-345.30 COCP ................................................................................................................ 5-355.30.1 COCP Jumper Settings...................................................................................... 5-355.30.2 COCP Hard Wired - None ................................................................................ 5-355.30.3 COCP DIP Switch (SW2) Settings ................................................................... 5-355.30.4 COCP Location of Jumpers and DIP Switches................................................. 5-355.31 LCOM ............................................................................................................... 5-365.31.1 LCOM Cards Layout......................................................................................... 5-365.31.2 LCOM List of Card Jumper Settings ................................................................ 5-365.32 SCOM ............................................................................................................... 5-365.32.1 SCOM Cards Layout......................................................................................... 5-365.33 LCMB ............................................................................................................... 5-37

x 92050003-02

Table of Contents


5.33.1 LCMB Jumper Settings - None......................................................................... 5-375.33.2 LCMB Hard Wired - None ............................................................................... 5-375.33.3 LCMB DIP Switches (SW2 to SW6) Settings.................................................. 5-375.34 LRMX ............................................................................................................... 5-385.34.1 LRMX Jumper Settings (for 75Ω or 100Ω) ..................................................... 5-385.34.2 LRMX Hard Wired - None ............................................................................... 5-385.35 LRMX ............................................................................................................... 5-395.35.1 LRMX Jumper Settings - None......................................................................... 5-395.35.2 LRMX Hard Wired - for 120Ω ......................................................................... 5-395.36 POWER SUPPLY............................................................................................. 5-405.36.1 Power Supply Front Panel................................................................................. 5-405.36.2 Power Supply Shelf........................................................................................... 5-405.37 MBPU ............................................................................................................... 5-415.37.1 MBPU Jumper Settings..................................................................................... 5-415.37.2 MBPU Hard Wired - None ............................................................................... 5-415.37.3 MBPU DIP Switch Settings .............................................................................. 5-415.38 SUMMARY OF JUMPER AND SWITCH SETTINGS.................................. 5-425.38.1 DTX-360 Cards................................................................................................. 5-425.38.2 Trunk & Bearer Impedance Configuration ....................................................... 5-445.39 CCOM CARDS................................................................................................. 5-455.40 LCOM CARDS................................................................................................. 5-465.40.1 Trunk & Bearer Impedance Configuration ....................................................... 5-465.41 POWER SUPPLY SHELF CARDS.................................................................. 5-47

92050003-02 1-1

1

GENERAL INFORMATION

1.1 IntroductionThis manual identifies and explains maintenance concepts and features with regard tothe DTX-360 system. It outlines procedures to aid maintenance personnel withtroubleshooting diagnosis, fault isolation, analysis, location, and correction.

1.2 Static AwarenessThe DTX-360 is designed for easy maintenance. Prior to maintenance, however, itshould be noted that there are SPECIAL PRECAUTIONS that should be followed. Itmust be remembered that electronic devices are easily damaged by accidentalintroduction of ground or foreign voltages. Therefore, certain tools and test equipmentcommonly used on electro-mechanical systems should never be used on an electronicsystem. These include: battery buzzers, AC wire-wrap guns, electric soldering irons,guns, test picks, and test lamps. The following precautions must be observed:

a. The DTX-360 uses various metal oxide semiconductor (MOS) devices. Special handling of circuit cards which contain these devices is required. All personal tools, test equipment, and metal objects that come in contact with MOS devices must be electrically grounded. Any static or foreign voltage that is introduced into these devices may damage them permanently.

b. DO NOT use tools or test equipment that draw an appreciable amount of currentwhen attached to the system, such as test lamps and picks.

c. DO NOT use tools or test equipment that could introduce foreign voltages into the system. For example, a battery-powered buzzer operates on only six or nine volts, but the voltage introduced across the buzzer coil when the magnetic field collapsed, can reach a momentary peak in excess of 100 volts, which can destroy solid- state devices.

Section 1 DTX-360General Maintenance

1-2 92050003-04

1.3 Repair and ReturnRepair and return orders are issued to fix customer-owned material where serviceconditions do not require advance replacement or when least- costly service is desired.Generally, repair and return orders are mailed into the Material Service Center (MSC).The MSC will repair or replace (with repaired equipment) at our option, materialsreturned to our facilities.

Note: If the system ceases to respond and/or operate (freezes), perform a Power Up Reset, verifyreturn to proper operation and report immediately to ECI Telecom Field EngineeringDepartment, specifying all relevant information, including History Report etc.

1.3.1 Order Entry (normal shipping time)Repair of defective materials is handled by calling your MSC representative. You will be issuedan Order Control Number that will serve as your Return Authorization (RA). Each packagereturned should be clearly identified with the RA number. A complete description of failuresymptoms should be enclosed for each returned part (Fig. 1-1). Shipment to the MSC must becomplete; do not send parts separately - some at one time and others at a later date. The MSCrepresentative will prepare an order and file it in our receiving area pending arrival of the parts.Send the materials when the Return Authorization number is received.

a) Typical Delivery Interval

Thirty days should be allowed for our repair time starting from when your materials are received by the MSC and when the materials are shipped back.

b) Invoicing Policy

In-warranty repair service is done at no charge. You pay the freight inbound and we will pay the outbound freight. A "no charge" invoice will be sent to you to close your purchase order. Premium freight service, if requested, will be invoiced to the customer. All terms are net 30 days.

Out-of-warranty invoices on repaired parts will generally be at 40% of full listprice plus freight and taxes for equipment manufactured by ECI Telecom.However, major repairs will require cost estimates prior to completion of work.In this case, a price quotation will be supplied with the repair order confirmationprior to the start of repair work. All terms are net 30 days.

1.3.2 Terminal Malfunction Report

In the rare event that a terminal ceases to operate, and is “stuck”, please do thefollowing:

• Perform a Power Up Reset

• Verify return (of the terminal) to proper operation

• Report to ECI Telecom as soon as possible - Please attach to your report all relevantinformation, such as History Reports.

DTX-360 Section 1Maintenance General

92050003-04 1-3

Description Serial No. RevisionDescripción No. de serie RevisiónDéscription Numéro de serie RévisionBeschreibung Serial No. Revision

Company Country CityCompania Pais CiudadCompagnie Pays VilleGesellschaft Land Stadt

System No. Site DateSistema No. Ubicación FechaNuméro de système Site DateAnlage Stelle Datum

-------------------------------------------------------Description of FaultDescripción de la fallaDéscription de panneBeschreibung der Fehler

Name SignatureNombre FirmaNom SignatureName Unterschrift

Figure 1-1. Malfunction Report

ECI Telecom GmbHBüropark OberurselIn der Au 2761440 Oberursel/TaunusGermanyTel: +49-6171-6209-0Fax: +49-6171-6209-88

ECI Telecom (HK) Ltd.2806 China Resources Building26 Harbour Road, WanchaiHong KongTel: +852-2824-4128Fax: +852-2802-4411

MSC LOCATIONS

ECI Telecom Inc.927 Fern StreetAltamonte Springs, FL 32701USATel: +1-407-331-5500Fax: +1-407-260-7136

ECI Telecom (UK) Ltd.ISIS House, Reading RoadBasingstokeHampshire RG24 8TW EnglandTel: +44-1256-388000Fax: +44-1256-388180


1-4 92050003-04

1.3.3 Order Entry (Emergency Order)

Enter your emergency service orders by calling the MSC and providing us with yourmaterials requirements; warranty status, air express shipping instructions, purchaseorder number and name of the person authorizing the purchase order.

For service call your local agent.

a) Method of Shipment

High priority orders must be shipped via express/traceable means; regular ordersmay be shipped via any standard available carrier as directed by the customer.

Shipment number and other delivery information may be obtained by calling theMSC. A return authorization and pre-addressed return labels are sent with all in-warranty shipments to facilitate your immediate return of the defective equipment.

b) Invoicing Policy/Payment Terms

In-warranty shipments are not invoiced immediately to allow you 30 days from date of shipment to return the defective equipment. Out-of-warranty shipments are invoiced immediately.

1.3.4 Insurance Policy

ECI Telecom will insure, at its own expense, materials shipped from ECI to customers.However, materials shipped from a customer's location to the MSC by the customermust be insured by the customer at his own expense.

1.3.5 Substitutions and Modifications

ECI reserves the right to make substitutions and modifications in the specifications ofequipment designed by ECI that do not materially and adversely affect the performanceof the equipment.

1.3.6 Limitations of Liability

Except as described under "Warranty", ECI shall not be liable for any liability, loss,damage, or expense relating to, arising out of, or in connection with the purchase,operation, use of licensing of equipment, software, and services. In no event shall ECIbe liable for any SPECIAL, indirect, accidental, or consequential damages of any nature,regardless of whether ECI has been advised of the possibility of such damages.


92050003-04 1-5

1.4 OPS RepairRepair of the "SUN" workstation used in the DTX-360 system as an OPS is provided byyour local "SUN" service office. Repair of defective OPS is handled by calling yourMSC representative who will, in turn, arrange all the necessary procedures with theSUN service office.

When all the procedures are arranged, your MSC representative will inform you abouthis arrangements. He also will inform you whether the repair is an in-warranty or out-of-warranty service. After all the procedures have been done, you may send your defectiveOPS to the service center, following your MSC representative`s instructions.

During the warranty period the OPS will be repaired at no charge by the local serviceoffice. During the out-of-warranty period you will be charged by the "SUN" serviceoffice for the OPS repair.

1.5 Tasks Authorized for the UserThe user may perform the following repair and testing actions:

Connecting/disconnecting plug-in cables in the DTX-360 system.

Extracting and inserting any PCB in the DTX-360 card cage. With the exception ofthe line-interface cards, power supply units, and the redundant cards in the change-over matrix, all other cards should be removed only with the power switched OFF.

Note: Use of a grounding strap is obligatory when a PCB is being extracted orinserted into the card cage.

Connecting and disconnecting DC-power (or AC) cable(s) (if applicable), to theDTX-360 system and its peripheral equipment and/or operator station

Performing all test procedures described in this Manual

1.6 Handling of Electrostatically Sensitive ComponentsThe DTX-360 uses MOS Semiconductor devices. Special handling precautions must beobserved when handling PCBs. All personal tools, test equipment, and metal objects thatcome in contact with MOS devices must be electrically grounded. Any static and/orexternal voltage that is introduced into these devices can damage them permanently.

Personnel handling PCBs should be grounded, using a grounding strap.


1-6 92050003-04

1.7 Handling Printed Circuit Boards Do not rub, scratch, or scrape the printed wiring side with a sharp or abrasive object.

Do not expose to excessive heat or humidity.

Do not make any unauthorized modifications, repairs, or adjustments.

Do not use abrasive cleaners.

Do not mark the cards with any writing instrument that leaves a conductive deposit,such as lead pencil.

Do not stack PCBs on top of each other.

Do not store PCBs in an area that contains air pollutants (gas, smoke, dust, etc.) thatmay contain harmful agents. Store PCBs in anti-static conductive bags.

1.8 Handling Peripheral Equipment and TerminalsSeveral external devices may be connected to the DTX-360 terminal:

• An operator station (and printer)

• A modem (for remote operation of the OPS)

• An RS232 multiplexer (in a cluster configuration)

All of the devices listed above are powered from the AC mains, and should not behandled with the cover removed.

Use only lint-free cloth to clean the surfaces (cover or keyboard) of the devices.

When servicing a DTX-360 terminal, make sure that no tools are placed on the top of theterminal.

Each cabinet may house several terminals. Special precautions must be taken when thetop terminal is serviced in order to prevent tools, screws, washers, etc., from falling intothe lower terminals.


92050003-04 1-7

1.9 Handling the Operator StationThe operator station is a fully featured workstation containing delicate peripherals andthe following precautions should be observed:

a) The system should be connected to a grounded (earthed) power outlet. Work stations which are not grounded do not work properly and can be a safety hazard. If the system is not properly grounded, abnormal program execution and problems in reading disks/diskettes may occur.

b) The system should be isolated from sources of electrical noise and from devices that can cause excessive voltage variations. Some common sources of electrical noise are:

• Air conditioners, fans, and large blowers

• Transformers and alternators

• Large electric motors

• Radio and TV transmitters, and HF security devices

c) The system should be placed in a relatively dust-free place.

d) Air inlets should be kept clear of paper or other materials that mayobstruct air flow.

1.10 AC Power OutletsAC outlets are provided for the ETHERNET HUB and Modem. These power outlets arenot provided with overload protection and appropriate care should be taken (externalfusing or other overload protection procedures).


1-8 92050003-04

1.11 Detecting Card MalfunctionsWhen a card malfunctions, the terminal’s self diagnostic process detects the malfunctionand an indication is displayed on the AUXC Card Display LEDs.

The indication contains the number of the malfunctioning card (1-52), according to itsslot location in the terminal.

For additional information regarding card malfunctions, please refer to report # 15 in theOMCP Monitor (in the OPS). Appendix A in the OPS-360 User’s Manual(Cat. # 92050005) contains detailed information about an OMCP Monitor session.

In the Built-In Test Report Window, select option 3 (Online BIT) to view details of cardmalfunction.

Note: In some cases, the cause of the malfunction may be a card other than the card thatreports the problem, e.g., the TSDF card is indicated as malfunctioning when in fact it isthe DSIR card. See next section for additional information.

1.12 Detecting the Source of a Card MalfunctionIn some cases the card that announces a malfunction (on the AUXC LED panel) is notmalfunctioning itself, but is affected by another card, that is actually the source of theproblem.

The following table contains a list of cards that announce malfunctions, the test that isperformed on the cards and a list of cards which may be connected to the malfunction.

Test Number Test Subject Testing Card Source of Indication

0309-0316 PCMITR (0:7) TSDF DSIR

0322-0329 PCMITR (0:7) TSDF DSIR

0317 BRR (0:1) TSDF QDLI-BR

0334 BRTBMCT (0:1) TSDF BMCT

0335 BRTBMCT (0:1) TSDF BMCT

0336 LVDSIT TSDF DSIT

0337 VBR_DIS TSDF DSIT

0338 PCMTCT0 TSDF QDLI-TR0

0343-0344 PCMTCT(0:1) TSDF QDLI-TR0





92050003-04 1-9


0353 SIGT TSDF SIGN

0354 CCTSTT TSDF DSIT

0355 ORWT TSDF AUXC






0373-0374 BRR (0:1) TSDF QDLI-BR

0383-0390 SIGTO (0:7) TSDF SIGN

0607 PCMITT (0:7) DSIT TSDF

0609 LDCT (0:2) DSIT LDCT (0-3)

0617 LRET (0:3) DSIT TDSP0

0612 BCMODT (0:3) DSIT BMCT

0614 PCMITE (0:7) DSIT DSIR

0709 BCBS(D)R (0:3)D (0:1)

DSIR BMCR0

0710 BCBS(D)R (0:3)D (0:1)

DSIR BMCR1

0711 FAXBSR (0:7) DSIR BMCR0,1

0714 PCMDECR (0:2) DSIR ADPCR

0715 PCMDECR (0:3) DSIR LDCR (0-3)

1210-1225 Card 0 CELLS TDSP0 DSIT

1210-1225 Card 1 CELLS TDSP1 DSIT

1404 PCMENCT (0:1) ADPCT DSIT

1405 ENCMODT (0:1) ADPCT DSIT

1501-1515 card 0 CELLS LDCT0 DSIT




1-10 92050003-04



2208-2223 LREBSR (0:15) RDSP DSIR

2401-2415 card 0 CELLS LDCR0 DSIR




3208-3228-3223 card 0 CELLS SDSP0 DSIT

3208-3228-3223 card 1 CELLS SDSP1 DSIT

4015-4018 BCBST (0:3) BMCT TDSP

4023-4026 LRET (0:3) BMCT TDSP0

4023-4026 LRET (0:3) BMCT TDSP1

5004-5011 PCMST (0:7) SIGN TSDF

6035-6036 card 0 PCMTCR (0:1) QDLI-TR0 TSDF




8027 card 0 BRTSDF0 BMCR0 TSDF

8027 card 1 BRTSDF0 BMCR1 TSDF

1.13 Card Removal Under PowerImportant : Before handling cards, make sure that you are connected to a proper anti-static device

Before starting a procedure which might affect traffic, make sure that the terminal doesnot carry live traffic.

The QDLI cards may be removed and replaced while the terminal is powered (ON).

Before removing/replacing all other cards, please turn the terminal OFF.

Note: Before turning a terminal OFF, make sure that it does not carry live traffic.


92050003-04 1-11

1.14 OMCP/COCP Card ReplacementEach OMCP/COCP card contains an Ethernet Chip with a unique MAC address.

If you replace an OMCP card, you must make sure that the correct MAC and IP addressare entered in the appropriate locations (files).

The files are:

ethers

hosts

config

pofInfo_am

Note: If the replacement OMCP/COCP card is an original Spare card, it is most likelythat its MAC address is already in the /etc /ethers file.

1.14.1 Modifying the ethers file

Before you replace an OPMC/COCP card, do the following:

1. In the OPS, open an xterm window.

2. Type su - (including the hyphen - ) and press RETURN (RETURN means theRETURN key)

3. The system will prompt you for a password; type sys$ops and press RETURN.(This will log you into the system as a super user).

4. Type emacs /etc/ethers and press RETURN (Open an editor to add a newaddress to the MAC Address file).

5. Add a line to the end of the displayed file (copy and paste an existing line).

6. Copy the last four (4) digits from the MAC chip (U183 in the OMCP card, U58 inthe COCP card - see exact location in the Jumper Setting, chapter 5 of this manual,pages 5-6, 5-25 and 5-35)

7. In the line that you added to the file, replace the last four (4) digits in the MACaddress with the digits that you copied from the MAC Chip.

8. In the OMCP Number column, change the OMCP number to the highest number + 1(e.g., if the highest OMCP number displayed is OMCP-105, the new OMCP numberis OMCP-106). If it is a COCP, change the COCP number in the same way.

Note: If you are starting a new cluster, add 1 to the left-most digit instead of adding1 to the right-most digit (e.g., the number of the first terminal in the second clusterwill be 201).

9. Save the changed MAC Address file and Exit the emacs editor. (Use the Save iconand/or the File pull down menu to execute the Save. Use the File pull down menu toexecute the Exit operation).


1-12 92050003-04

1.14.2 Modifying the hosts file

1. Type emacs /etc/hosts (Open an editor to add a new address to the IPAddress file).


3. Increment by 1 the number of the last group in the last IP address (in the new line).

Note: If you are operating in a WAN environment, type in your IP address.

4. Change the OMCP/COCP number in the new line to the number you gave theOMCP in the MAC file (e.g., OMCP-107).

5. Save the changed IP Address file and Exit the emacs editor.

1.14.3 Modifying the config file

1. Type emacs /usr/local/etfs/config and press RETURN (Opens aneditor to add a new OMCP to the configuration file).


3. Change the OMCP/COCP number in the new line to the number you gave theOMCP/COCP in the MAC file (e.g., OMCP-107).

4. Save the changed file and Exit the emacs editor.

1.14.4 Modifying the pofInfo_am file

• Type emacs /usr/local/ops/etc/pofInfo_am and press RETURN(Opens an editor to update the file responsible for communications between the OPSand the terminals).

• Add a line after the last line displaying OMCP or COCP (copy and paste an existing line).

• Change the OMCP number in the new line to the number you gave the OMCP in theMAC file (e.g., OMCP-107).

• In column 2 - Type the number 6 if the card is an OMCP, or 7 if the card is a COCP.

• In column 4 - increment the last number by 1.

• Save the changed file and Exit the emacs editor.

1.14.5 Resuming Operation After completing the implementation of the required changes in all the above files, do

the following:

• Close the OPS process - either by pressing the EXIT icon on the OPS control panel,or by typing opsCheck -terminate in an xterm window and press RETURN.

• In an xterm window, type reboot (to reset the ops) and press RETURN.

• When prompted for a login, type ops_user and press RETURN


92050003-04 1-13

• When prompted for a password, type user$ops and press RETURN

The OPS control panel will be displayed.

To resume operations, do the following:

1. Verify that live traffic does not pass through the terminal.

2. Verify that the terminal does not process live traffic (the terminal should be blockedfrom the exchange) before proceeding.

After verifying that no traffic passes through the terminal, do the following:

1. If the Terminal Mode is not Disable, do the following:

• Select the terminal by clicking on it in the cluster window

• Select Edit Info from the Setup menu

• In the Edit Terminal Info secondary window, change the Protection Mode toDisable

2. Turn OFF the DTX-360 terminal/CCOM.

3. Insert/Replace the OMCP/COCP card.

4. Turn terminal/CCOM ON

Note: Follow Terminal Reset/Restart procedures as described in the following paragraph.

1.15 To Turn a Terminal OFFPerforming RESET or OFF/ON operations on a terminal depend on the terminal being ina Stand Alone or a Cluster configuration:

1.15.1 Stand Alone Configuration

If the terminal is in this configuration, do the following:

1. Verify that the terminal does not process live traffic (the terminal should be blockedfrom the exchange).

2. Turn the terminal OFF by pressing the Main Switch on the AUXC front panel.

1.15.2 Cluster configuration

If the terminal is in this configuration, do the following:

1. Verify that the Protection Mode of the terminal is Disable (Terminal ProtectionMode is displayed on the Terminal Block, on the top right corner of the ClusterWindow in the OPS).

2. If the Terminal Mode is not Disable, do the following:

• Select the terminal by clicking on it in the cluster window

• Select Edit Info from the Setup menu


1-14 92050003-04

• In the Edit Terminal Info secondary window, change the Protection Mode toDisable

3. Verify that the terminal does not process live traffic (the terminal should be blockedfrom the exchange).

4. Turn the terminal OFF by pressing the Main Switch on the AUXC front panel.

Note: The CCOM may be turned off directly, as it does not have a Protection Mode.

92050003-02 2-1

2

INTERNAL AND CLUSTERCABLE CONNECTIONS

2.1 General

This section contains information concerning internal cable connections in a DTX-360cabinet and in a cluster configuration.

ECI Telecom provides ready-made cables and connectors required for this phase of thesystem's installation.

The cluster configurations described in this manual are a Full Cluster (8+1) and aCompact Cluster.

After positioning the cabinets, fixing and checking the positions of the shelves, inter-cabinet cabling may commence. The following procedures should be performed:

1. Connect the Trunks, Bearers and DLC lines from each individual terminal to theLCOM back panel.

2. Connect the trunks, bearer, and DLC cables from the LCOM(s) to exchange DDF. 3. Connect Bit Streams and DLC from LCOM(s) to CCOM. 4. Connect CCOM to Redundant terminal (BS and DLC). 5. Wire up Bit Streams from CCOM to ISC for ninth (9) terminal (where applicable). 6. Connect the Alarm outputs. 7. Wire up Power Supplies to LCOM, CCOM, and Terminals.

Section 2 DTX-360Cluster Cable Connections Maintenance

2-2 92050003-02

2.2 Terminal - LCOM ConnectionsThe basic operational unit of the DTX-360 is a cabinet, containing two (2) operatingterminals and a Local PM (LCOM) shelf (Fig 2-1).

Note: The following Bitstream and DLC connection instructions refer only toDTX-360 systems. For instructions concerning DTX-360C, please refer to Section 2.4.3

2.2.1 Bitstream ConnectionEach cable (bearer and trunk) carries four (4) bitstreams from the LCOM motherboardto each terminal motherboard.

Connection (LCOM):

J110 - Bearers 1-4

J126 - Trunk 1-4

J132 - Trunk 5-8

J140 - Trunk 9-12

J146 - Trunk 13-16

Connection (Terminal): BPIF 0/1 -J3, J4

• Upper part of module from LCOM connects to upper DTX-360 terminal(BPIF0/1)

• Lower part of module from LCOM connects to lower DTX-360 terminal(BPIF0/1)

Note: See markings on BPIF cards for exact location of bearers and trunks.

Cable: 8 pair 28 AWG overall shield (WS102)

Connector: DIN 3x7 pin IDC

DTX-360 Section 2Maintenance Cluster Cable Connections

92050003-02 2-3

J106

J110

J126

J132

J140

J146

D L C

B R

T R

T R

T R

T R

UP

PE

R

TE

RM

INA

LLO

WE

R

TE

RM

INA

L

BP

AU

BP

IF0

BP

IF1

J3

J3

J4

J4

BP

AU

BP

IF0

BP

IF1

J3

J3

J4

J4

J36

J36

WS102

WS102

WS102

W S 1 0 2

W S 1 0 2

WS102

WS102

WS102

WS102

WS102

WS102

WS102

Figure 2-1 LCOM Terminal Cable Connections


2-4 92050003-02

2.3 LCOM - CCOM Connections (Figures 2-2 and 2-3)

2.3.1 DLC Connections

Each DTX-360 LCOM connects to the CCOM with four (4) DLC and four (4)Terminal-select lines.

Connection (LCOM(s)): J120

Connection (CCOM) : J108 (for LCOM 1) J110 (for LCOM 2) J112 (for LCOM 3) J114 (for LCOM 4)


Connector: IDC D type 15 pin male

2.3.2 BitstreamConnections

Each DTX-360 LCOM connects to the CCOM with four (4) Bearer and sixteen (16)Trunk lines.

Connection (CCOM ):J118, J120, J122, J124 (for Bearers of LCOMs 1,2,3, 4, respectively)J128, J138, J148, J158 (for LCOM 1 TRs)J130, J140, J150, J160 (for LCOM 2 TRs)J132, J142, J152, J162 (for LCOM 3 TRs)J134, J144, J154, J164 (for LCOM 4 TRs)

Connection (LCOM(s)):J116 (BR)J124, J130, J138, J144 (TRs)


Connector: IDC D type 25 pin male


92050003-02 2-5

Figure 2-2 DTX-360 - Inter-Cabinet Cabling


2-6 92050003-02

Figure 2-3. DTX-360C - Inter-Cabinet Cabling


92050003-02 2-7

2.4 CCOM - Redundant Terminal Connections(Figures 2-4, 2-5)

2.4.1 Bitstream ConnectionsEach bitstream cable leads four (4) trunks or bearers from the CCOM to the Redundantterminal (Figures 2-4 and 2-5).

Connection (Terminal): BPIF 0/1 - J3, J4

Connection (CCOM):J109 (upper half) (BR)J113, J117, J119, J123 (upper half) (TRs)

Cable: 8 pair 28 AWG overall shielding (WS102)

Connector: Module DIN 3x7 pin IDC

2.4.2 DLC ConnectionsFour (4) DLC and alarm lines connect the CCOM to the standby terminal.

Connection (CCOM): (J105) (upper half)

Connection (Terminal): AUP J36 (upper half)

Cable: 8 pair 28 AWG overall shielding

Connector: Module DIN 3x7 pin IDC

Note: DTX-360C Cabling instructions for CCOM-Standby Terminal connections aresimilar to those given in item 2.4. An exact graphic illustration appears in Figure 2-5.


2-8 92050003-02

W S 1 0 2

W S 1 0 2

W S 1 0 2

W S 1 0 2

W S 1 0 2

W S 1 0 2

D L C

B R

T R

T R

T R

T R

.

Figure 2-4 DTX-360 - CCOM-Redundant Terminal Cable Connections


92050003-02 2-9

W S 1 0 2

W S 1 0 2

W S 1 0 2

W S 1 0 2

W S 1 0 2

W S 1 0 2

D L C

B R

T R

T R

T R

T R

Figure 2-5 DTX-360C - CCOM-Redundant Terminal Cable Connections


2-10 92050003-02

2.4.3 LCOM - Four (4) Compact Terminals Connections(DTX-360C )In addition to full size DTX-360 terminals, the user can assemble cabinets and clustersof DTX-360C (Compact). A DTX-360C terminal can accommodate four (4) bearer linesand eight (8) bitstreams.

2.4.3.1 Bitstream ConnectionsBitstream connections to DTX-360C terminals 1-4 are as follows:

Connection (LCOM): (WS102)J110 - Bearers 1-4 for Terminals 1, 2J118 - Bearers 1-4 for Terminals 3, 4J126 - Trunks 1-4 for Terminals 1, 2J132 - Trunks 1-4 for Terminals 3, 4J140 - Trunks 5-8 for Terminals 1, 2J146 - Trunks 5-8 for Terminals 3, 4

Connection (Terminals):BPIF0 J3 Upper half for Bearers 1-4

Lower half for Trunks 1-4BPIF0 J4 Upper half for Trunks 5-8

2.4.3.2 DLC ConnectionsDLC connections to DTX-360C terminals 1-4 are as follows:

Connection (LCOM): (WS102)J105 - for Terminals 3, 4J106 - for Terminals 1, 2

Connection (Terminal): AUP J36

Note: See Figure 2-6, cable routing for LCOM-Terminal(compact) connections.


92050003-02 2-11

Figure 2-6. DTX-360C Cluster (4 Terminals) - Cable Connections


2-12 92050003-02

2.4.4 SCOM - Three (3) Compact Terminals + RedundantTerminal Connections (DTX-360C)A DTX-360 C (Compact) cluster may be comprised of three (3) active terminals and one(1) redundant terminal.In this case, the LCOM functions as a CCOM (see LCOM drawing for card layoutinformation).

2.4.4.1 Bitstream ConnectionsBitstream connections to DTX-360C terminals 1-3 + Redundant are as follows:Connection (SCOM): (Figure 7-37) (WS102)

J110 - Bearers 1 - 4 for Terminals 1, 2J116 - Bearers 1 - 4 for Redundant TerminalJ118 - Bearers 1 - 4 for Terminal 3J126 - Trunks 1 - 4 for Terminals 1, 2J132 - Trunks 1 - 4 for Terminal 3J124 - Trunks 1 - 4 for Redundant TerminalJ140 - Trunks 5 - 8 for Terminals 1, 2J146 - Trunks 5 - 8 for Terminals 3J130 - Trunks 5 - 8 for Redundant Terminal

Connection (Terminals): (Figure 7-37)BPIF0 J3 - Upper half for Bearers 1 - 4Lower half for Trunks 1 - 4BPIF0 J4 - Upper half for Trunks 5 - 8

2.4.4.2 DLC ConnectionsDLC connections to DTX-360C terminals 1 - 3 + Redundant are as follows:Connection (SCOM): (Figure 7-37) (WS102)

J105 - for Terminals 3J106 - for Terminals 1, 2J120 - for Redundant Terminal

Connection (Terminal): BPAU J36


92050003-02 2-13

J116

J110

J106J36

J36

J3

J3

J3

J124

J120 J36

J3

J132

J126J3

J3

J3

J130

J146

J140J4

J4

J4

J4

TERMINAL 1

TERMINAL 2

TERMINAL RED.

TERMINAL 1

TERMINAL 2

TERMINAL 1

TERMINAL 1

TERMINAL 2

TERMINAL 3

TERMINAL 1

TERMINAL 2

TERMINAL 3

DLC TERMINAL 1

DLC TERMINAL 2

BEARER 1-4 TERMINAL 1


BEARER 1-4 TERMINAL RED.

DLC REDUNDANT TERMINAL

TERMINAL RED. TRUNKS 1-4 TERMINAL RED.

TRUNK 1-4 TERMINAL 1


TERMINAL RED. TRUNKS 5-8




S C O M TERMINALS ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

ws-102

J118BEARER 1-4 TERMINAL 3 ws-102

J3 TERMINAL 3


TERMINAL RED.

DLC TERMINAL 3 ws-102TERMINAL 3J36J105

Figure 2-7 SCOM Connected to 3 Compact Terminals + Redundant TerminalCable Connections


2-14 92050003-02

2.4.5 SCOM + Two (2) Terminals + Redundant TerminalConnectionsWhen operating in 1+1 or 2+1 (one or two terminals and a redundant terminal), theLCOM function as SCOM (see LCOM drawing for card layout information).

Note: This option is identical for Regular (full size) and Compact terminals.

2.4.5.1 Bitstream ConnectionsBitstream connections to DTX-360 terminals - (one or two terminals) + Redundant areas follows:Connection (SCOM): (Figure 7-38) (WS102)

J110 - Bearers 1 - 4 for Terminals 1, 2J116 - Bearers 1 - 4 for Redundant TerminalJ126 - Trunks 1 - 4 for Terminals 1, 2J124 - Trunks 1 - 4 for Redundant TerminalJ140 - Trunks 5 - 8 for Terminals 1, 2J130 - Trunks 5 - 8 for Redundant Terminal

Connection (Terminals): (Figure 7-38)BPIF0 J3 - Upper half for Bearers 1 - 4Lower half for Trunks 1 - 4BPIF0 J4 - Upper half for Trunks 5 - 8BPIF1 J3 - Lower half for Trunks 9 - 12(For full-size terminals only)BPIF1 J4 - Upper half for Trunks 13 - 16(For full-size terminals only)

2.4.5.2 DLC ConnectionsDLC connections to DTX-360 terminals 1 - 2 + Redundant are as follows:Connection (SCOM): (Figure 7-38) (WS102)

J106 - for Terminals 1, 2J120 - for Redundant Terminal

Connection (Terminal): BPAU J36


92050003-02 2-15

J116

J110

J106J36

J36

J3

J3

J3

J124

J120 J36

J3

J126J3

J3

J130

J140J4

J4

J4

TERMINAL 1

TERMINAL 2

TERMINAL RED.

TERMINAL 1

TERMINAL 2

TERMINAL 1

TERMINAL 2

TERMINAL 1

TERMINAL 2

DLC TERMINAL 1

DLC TERMINAL 2



BEARER 1-4 TERMINAL RED.

DLC TERMINAL RED.

TRUNKS 1-4 TERMINAL RED.

TERMINAL RED.



TRUNKS 5-8 TERMINAL RED. TERMINAL RED.



TERMINAL RED.

S C O M TERMINALS

Figure 2-8 . SCOM Connected to Two (2) Compact Terminals or One (1) RegularTerminal + Redundant Terminal - Cable Connections

92050003-02 3-1

3

Transmission Alarms

The following is a description of the DTX-360 alarms resulting from the alarmconditions on the trunk and/or bearer side (Transmission Alarms). Transmission alarmsare sub-divided into two categories: the E1 (2.048 Mbit/s) and T1 (1.544 Mbit/s) Trunkand /or Bearer Interface, respectively. Refer to the DTX-360 Alarm Tables (Tables 3-6and 3-7) for further information.

3.1 2.048 Mbit/s E1 Transmission Alarms Description

3.1.1 Loss of Incoming Signal (LOS)

The LOS alarm goes ON if:

• 3 or less ones are received in a time interval of 250 microsec, or

• no receive route clock pulse is received during 4 system clock cycles

The LOS alarm goes OFF if no alarm condition exists.

3.1.2 Alarm Indication Signal (AIS)

The AIS Alarm goes “ON” when an unframed “ALL ONES” signal is received on thePCM path for the duration of two frames (250µsec)

The AIS alarm goes “OFF” if no alarm condition exists.

Section 3 DTX-360Transmission Alarms Maintenance

3-2 92050003-02

3.1.3 Loss of Alignment (LOF) Alarm

Loss and recovery of FRAME ALIGNMENT are in accordance with ITU Rec. G.704and G.706 (BLUE BOOK).

a) Loss of Frame Alignment

Frame alignment will be assumed to have been lost when three consecutive incorrectframe alignment signals have been received.

If the bitstream includes a CRC field, then a loss of frame alignment can also bedeclared in response to failure to achieve CRC multiframe alignment in accordance withG.706, Para. 6.4.2, or by exceeding a specified count of errored CRC message clocks asindicated in Rec. G.706, Para. 4.3.2.

b) Strategy for Frame Alignment Recovery

Frame alignment will be assumed to have been recovered when the following sequenceis detected:

• For the first time, the presence of the correct frame alignment signal

• The absence of the frame alignment signal in the following frame detected byverifying that bit 2 of the basic frame is a 1

• For the second time, the presence of the correct frame alignment signal in the nextframe

3.1.4 CRC Multiframe (CRC MFR)

This alarm is issued only for bitstreams that include a CRC field in accordance withRec. G.704 and G.706.

After frame alignment has been declared, CRC multiframe alignment shall be declaredafter at least two valid CRC multiframe alignment signals can be located within 8 msec,the time separating two CRC multiframe alignment signals being 2 msec or a multiple of2 msec. The search for the CRC multiframe alignment signal should be carried out onlyin basic frames not containing the frame alignment signal.

3.1.5 High CRC Error

This alarm is issued only for the bitstreams that include a CRC field. High CRC ERRORalarm is declared if the CRC error count in an one-second interval exceeds 914 errors.

Upon detection of such an event, a new search for frame alignment is initiated.

DTX-360 Section 3Maintenance Transmission Alarms

92050003-02 3-3

3.1.6 High Bit Error Rate (H.BER)

a) H.BER ACTIVATION CRITERIA

5 consecutive seconds with BER higher than 10-3 per second.

b) H.BER DEACTIVATION CRITERIA

5 consecutive seconds with BER less than 10-3 per second.

3.1.6.1 H.BER, Bitstream with the CRC Format

If the bit stream includes CRC field: CRC counter > 805

3.1.6.2 H.BER, Bitstream without CRC Format

If the bit stream is without CRC: No. of frame errors > 28 errors/seconds.

3.1.7 Low Bit Error Rate (L.BER)

This alarm indicates a bit error rate higher than or equal to 10-6, but less than 10-3.

3.1.7.1 L.BER, Bitstream without CRC Format

Frame alignment signal errors are used to estimate the bit error rate.

a) ACTIVATION CRITERIA:

One 2 minute interval with BER in the range of 10-6 to 10-3.

b) DEACTIVATION CRITERIA:

One 2 minute interval with BER less than 10-6.

3.1.7.2 L.BER, Bitstream with the CRC Format

CRC ERRORS/SECOND are used to estimate the bit error rate.

a) ACTIVATION CRITERIA:

Two consecutive 30 second intervals each with a CRC error count greater than or equalto 60.

b) DEACTIVATION CRITERIA:

Two consecutive 30 second intervals each with a CRC error count less than 60.

3.1.8 Remote (Far-end) Alarm Indication (RAI)

Far-end equipment indicates a loss of frame alignment by activating the remote alarmindication (Bit 3 in TS0 of the frame not containing frame alignment signal). Activationof the incoming RAI alarm is delayed for 100 msec. RAI alarm is cleared if Bit 3 in TS0is "0".


3-4 92050003-02

3.1.9 Multiframe Alignment (MFR)

TS16 consists of a multiframe structure in accordance with ITU Rec. G.704. Multiframealignment (MFR) loss is declared when two consecutive multiframe alignment signalshave been received with an error.

Multiframe alignment is recovered as soon as the first multiframe alignment signal isdetected.

3.1.10 Remote Multiframe Alarm Indication (RMFR)

Far-end equipment indicates a loss of multiframe alignment by activating the RemoteMultiframe Alarm Indication (Bit 6 in TS16, Frame 0).

3.1.11 High Slip Rate (H.SLIP)

Slips are counted at the trunk side input and output plesiochronous buffers and at thebearer side input plesiochronous buffer.

a) H.SLIP ACTIVATION CRITERIA

More than 30 slips in an interval less than one hour.

b) H.SLIP DEACTIVATION CRITERIA

1 hour interval with less than 30 slips.

3.1.12 Low Slip Rate (L.SLIP)

a) L.SLIP ACTIVATION CRITERIA

More than 5 slips in time interval which is smaller or equal 24 hours, but less than 30slips per hour.

b) L.SLIP DEACTIVATION CRITERIA:

24 hours with less than 5 slips.

3.1.13 No External Clock Alarm

This alarm is declared only if the external clock is defined as main or reserve systemclock (TX or TRO).

Deactivation of "NO EXTERNAL CLOCK" alarm is delayed for 500 msec.


92050003-02 3-5

3.1.14 Bitstream or External Clock Fail

The Tx and TRO system clock frequency range is tested by the system.

If the frequency range is not within ± 60 ppm of the nominal value, then the clock isrejected as a system clock. The Clock Fail Alarm will cease automatically 15 minutesafter fail detection (or immediately, by operator selection of this clock). If the clockreturns to function as a system clock, it will be tested again.

Bouncing between two clock sources will normally not take place, because switchingbetween the Reserve and Main clocks takes place only if the reserve system clock is lostor fails.

3.1.15 DCME Frame Alarm (DFA)

DCME frame alignment will be assumed to have been lost when three consecutiveunique words received in the control channel do not match the unique words defined inG.763 Para. 11.2.1.

DCME frame alignment will be assumed to have been recovered upon the correctreception of the unique word patterns defined in G.763 Para. 11.2.1 (including the MFunique work pattern).

3.1.16 CC-HBER

BER > 10-3 detected in the control channel will trigger activation of the CC-HBERalarm.

The BER detection criteria is based on an analysis of the number or errors detected bythe GOLAY error protection code (24, 12) for ADPCM; BCH for LD-CELP.

3.1.16.1 Activation Criteria

ERRORS DETECTED > 1440 in a measurement period of up to 1 minute.

3.1.16.2 Deactivation Criteria

ERRORS DETECTED < 1440 in a measurement period of up to 1 minute.

3.1.17 CC-LBER

BER ≥ 10-5 detected in the control channel will trigger activation of the CC-LBERalarm.

3.1.17.1 Activation Criteria

ERRORS DETECTED ≥ 14 in a measurement period of 1 minute.


3-6 92050003-02

3.1.17.2 Deactivation Criteria

ERRORS DETECTED < 14 in a measurement period of 1 minute.

3.1.18 CC-AIS

The CC-AIS alarm goes "ON" when an "ALL ONES" signal is received in the controlchannel bits for a duration of 4 msec (2 DCME frames) for ADPCM; 5msec for LD-CELP.

The CC-AIS alarm goes "OFF" when at least two zeros are received during a 4 msecperiod (2 DCME frames).

3.1.19 Bearer Backward Alarm

A far-end DCME indicates loss of DCME frame alignment (DFA) by activating thebearer backward alarm indication in the control channel structure.

3.1.20 Far-End (Remote) Trunk Alarm

The DCME control channel contains provisions of transmitting an IT related alarm tothe distant end.

Remote trunk alarm event indicates to the operator that a far end destination has at leastone alarmed IT.


92050003-02 3-7

3.2 1.544 Mbit/s T1 Transmission Alarms Description

3.2.1 Loss Of Frame alignment (LOF - CFA)

LOF failure is declared when the LOF defect persists for 2.5 s ± 0.5 s, except when theAIS defect or failure is present.

Alarm recovery: An existing LOF failure is cleared when an AIS failure isdeclared, or when a valid framing is detected for a time equal or greater than T, where0 s <= T <= 20 s.

Default severity: Prompt (Major) alarm

Consequent actions: Trunk - Inject RAI towards local ISC, Send IT alarm in CC tofar-end DCME.

Bearer - For all Trunk Channels that are destined to the faulty bearer: Inject AIS/64towards ISC.If alarm extension per BS is defined, inject AIS/2M to all output trunks which all theirtime slots are marked as faulty.

Send BW alarm in transmitting bearer CC. Send RAI in transmitting bearer if allincoming bearers are failed.

3.2.2 Loss Of incoming Signal (LOS)

Alarm declaration: LOS failure is declared when the LOS defect persists for 2.5 s± 0.5 s,

Alarm recovery: An existing LOS failure is cleared when the LOS defect isabsent for a time equal or greater than T, where 0 s <= T <= 20 s.





3.2.3 Alarm Indication Signal (AIS-CFA)

Alarm declaration: AIS failure is declared when the AIS defect persists for 2.5 s ±0.5 s,


3-8 92050003-02

Alarm recovery: An existing AIS failure is cleared when the AIS defect is absentfor a time equal or greater than T, where 0 s <= T <= 20 s.

Default severity: Service (Minor) alarm




3.2.4 High Bit Error Rate (HBER)

HBER is defined as a Bit Error Rate of more than 10-3

Alarm declaration: 5 consecutive Severely Errored Seconds (SES)

SES criteria:

If bit stream includes CRC field: CRC counter > 320

For bit stream without CRC: No. of frame errors > 8

errors/seconds.

Alarm recovery: 5 consecutive seconds with BER less than 10-3.

Reference: M.2100





3.2.5 Remote (Far-end, Distant) Alarm Indication (RAI) - (Yellow)

Alarm declaration: A far-end equipment indicates loss of frame alignment byactivating the remote alarm indication. For SF mode, the far-end failure is declaredwhen bit #6 of all channels has been zero for at least 335 ms.

For ESF mode, the far-end failure is declared if the Yellow alarm signal pattern occursin at least 7 out of 10 contiguous 16 bit pattern intervals


92050003-02 3-9

Alarm recovery: RAI alarm is cleared as soon as the DS1 terminal determinesthat it is no longer receiving an RAI signal from the far-end. For SF mode, the far-endfailure is cleared when bit #6 of at least one channel is non-zero for a period T, where Tis usually less than 1 second and always less than 5 seconds.

For ESF mode, the far-end failure is cleared if the Yellow alarm signal pattern does notoccur in 10 contiguous 16 bit pattern intervals.

Default severity: Service (Minor) alarm

Consequent actions: Trunk - Send IT alarm in CC to far-end DCME.

Bearer - For all Trunk Channels that are destined to that bearer:

Inject AIS/64 towards ISC.If alarm extension per BS is defined, inject AIS/2M to all output trunks which all theirtime slots are marked as faulty.

3.2.6 Low Bit Error Rate (LBER)

A LBER is defined as a BER of more than 10-6 but less than 10-3

Alarm declaration: Bit Stream without CRC Format:2 consecutive 2 minutes periods, each has 193 or more bipolar violation errors but lessthan 28 frame errors per second

Bit Stream with CRC Format:

2 consecutive 10 seconds periods, each period has more than 15 CRC errors but lessthan 320 CRC errors per second.

Alarm recovery: For Bit Stream without CRC Format:Two consecutive 2 minutes periods, each has 193 or less bipolar violation errors.

For Bit Stream with CRC Format:2 consecutive 10 seconds periods, each one with less than 15 CRC errors.

Default severity: Deferred (Minor) alarm

Consequent actions: None


3-10 92050003-02

3.3 Maintenance Levels of Transmission Alarmsand Events (E1 System)The maintenance alarm classification of a limited number of alarms is user selectable asshown in Table 3-2.

Transmission Alarms classification resulting in Prompt, Deferred, or Service Alarms areshown in Tables 3-1, 3-2, and 3-3, respectively. The default Transmission Alarmsclassification resulting in system events are shown in Table 3-4.

Table 3-1. Prompt Alarms

DESCRIPTION ALARM

LOS - TRUNK STREAM # PROMPT

LOS - BEARER STREAM # PROMPT

LOF - TRUNK STREAM # PROMPT

LOF - BEARER STREAM # PROMPT

H.BER - TRUNK STREAM # PROMPT

H.BER - BEARER STREAM # PROMPT

H.SLIP RX - BEARER STREAM # PROMPT

CRC-MFR - TRUNK STREAM # PROMPT

CRC-MFR - BEARER # PROMPT

MFR TRUNK STREAM # PROMPT

CLOCK FAILED - BEARER # PROMPT

CC HBER - DESTINATION # PROMPT

DFA - DESTINATION # PROMPT


92050003-02 3-11

Table 3-2. DTX-360 Transmission Alarm Classification

FAULT CONDITIONALARM

CLASSIFICATIONPMA/DMA/SA/MEI

DEFAULT

Failure of i/c primary group (LOF or LOS or HBER) PMA

AIS on primary group trunk side User selectable S.A.

AIS on primary group bearer side User selectable S.A.

MFR alarm (TS16) on primary group trunk side User selectable PMA

RAI on primary group trunk side User selectable S.A.

RAI on primary group bearer side User selectable S.A.

Remote MFR alarm (TS16) on primary group trunk side User selectable S.A.

CRC MFR alarm on primary group User selectable PMA

Abnormal circuit supervision on trunk channel User selectable M.E.I

LBER (10E-6<10E-3) on primary group User selectable DMA

H.SLIP-TX at trunk interface primary group User selectable MEI

L.SLIP-TX at trunk interface primary group User selectable MEI

H.SLIP -RX at trunk interface primary group User selectable MEI

L.SLIP-RX at trunk interface primary group User selectable MEI

H.SLIP-RX at bearer interface primary group User selectable PMA

L.SLIP-RX at bearer interface primary group User selectable MEI

AIS in DCME control channel (CC AIS) User selectable S.A.

BER>10E-3 in DCME control channel (CC HBER) User selectable PMA

LBER (10E-6<BER<10E-3) in DCME control channel (CC LBER) User selectable DMA

Loss of DCME Frame (DFA) User selectable PMA

Bearer backward alarm in DCME control channel User selectable S.A.

Legend:

PMA = Prompt Maintenance AlarmDMA = Deferred Maintenance AlarmSA = Service Alarm


3-12 92050003-02

Table 3-3. Deferred Alarms

DESCRIPTION ALARM

L.BER - TRUNK STREAM # DEFERRED

L.BER - BEARER STREAM # DEFERRED

CLOCK FAILED - STREAM # DEFERRED

CLOCK FAILED - EXTERNAL DEFERRED

CC LBER - DESTINATION # DEFERRED

Table 3-4. Service Alarms

DESCRIPTION ALARM

AIS - TRUNK STREAM # SERVICE

AIS - BEARER STREAM # SERVICE

H.SLIP - TRUNK STREAM # SERVICE

RAI - TRUNK STREAM # SERVICE

RAI - BEARER STREAM # SERVICE

RMFR - REMOTE MFR TRUNK STREAM # SERVICE

CC AIS - DESTINATION # SERVICE

BEARER BACKWARD ALARM - DESTINATION # SERVICE

Table 3-5. Transmission Events

DESCRIPTION ALARM

H.SLIP TX - trunk # EVENT

L.SLIP TX - trunk # EVENT

L.SLIP RX - trunk # EVENT

L.SLIP RX - bearer # EVENT

TRO-CLOCK-SELECT - STREAM - 0 TO 7 EVENT

TRO-CLOCK-SELECT - EXTERNAL EVENT

TRO-CLOCK-SELECT - BEARER EVENT

RX-CLOCK-SELECT - BEARER EVENT

HIGH-CRC ERROR TRUNK - 0 TO 7 EVENT

HIGH-CRC ERROR TRUNK - BEARER EVENT

REMOTE TRUNK ALARM - DESTINATION # EVENT

AVERAGE CC BER THRESHOLD EVENT

BER EXCESS THRESHOLD EVENT

SEVERELY ERRORED SEC (CC) THRESHOLD EVENT


92050003-02 3-13

3.4 Maintenance Levels of Transmission Alarms(T1 System)

Fault Condition Alarm Classification

PMA/DMA/SA/MEI

Default

LOS-CFA (Carrier failure alarm ) on i/c primary group PMA

LOF-CFA (Carrier failure alarm ) on i/c primary group PMA

AIS-CFA (Carrier failure alarm ) on i/c primary group USER SELECTABLE SA

YELLOW-CFA (Remote Alarm Indication) on i/c primarygroup

USER SELECTABLE SA

LOF (out of frame) or LOS defect on i/c primary group MEI

AIS defect on i/c primary group MEI

Abnormal circuit supervision on trunk channel USER SELECTABLE DMA

HBER (BER > 10-3) on bearer interface primary group PMA

HBER (BER > 10-3) on trunk interface primary group USER SELECTABLE PMA

LBER (10-6 < BER < 10-3) on primary group USER SELECTABLE DMA

H.SLIP-TX at trunk interface primary group USER SELECTABLE MEI

L.SLIP-TX at trunk interface primary group USER SELECTABLE MEI

H.SLIP-RX at trunk interface primary group USER SELECTABLE MEI

L.SLIP-RX at trunk interface primary group USER SELECTABLE MEI

H.SLIP-RX at bearer interface primary group USER SELECTABLE PMA

L.SLIP-RX at bearer interface primary group USER SELECTABLE MEI

3.4.1 Change Clock Alarm Severity

Any change in one of the system clocks (TX,RX,TRO) will be logged as "CHANGECLOCK".

The new clock will also be logged, e.g.,:

TX-CLOCK CHANGE CLOCK = TR B.S.2

Alarm severity of a "change clock" event depends on the "MAIN" clock and"RESERVE" clock definitions.

a) If "CHANGE CLOCK" triggers selection of the "MAIN" clock, the alarm severitywill be recorded as "PROMPT".

b) If "CHANGE CLOCK" triggers selection of the "RESERVE" clock, the alarmseverity will be recorded as "DEFERRED".

c) If "CHANGE CLOCK" triggers selection of a clock not defined as "MAIN" or"RESERVE", the alarm severity will be recorded as "EVENT".


3-14 92050003-02

3.5 Transmission Alarm HandlingTables 3-6 and 3-7 show consequent actions of the DTX-360 system resulting fromTransmission Alarms for the different Trunk and Bearer interfaces. These tables indicateNear End and Far End response and corresponding signals sent to the trunk and bearerbitstreams.

Table 3-6. Trunk Side Interface Alarms

FAULT

CONDITIONS

TRUNK-SIDE

LOCAL,

DCME

ALARM

DEFAULT

QDLI / SIGN

LED

INDICATOR

GENERATE

TOWARD

LOCAL ISC

BACKWARDALARMINDICATION

GENERATE ON

BEARER TO

CORRESP. DCMEs

FAULT INDICATIONIN AFFECTEDTRUNK CHANNEL(IT ALARM IN CC)

Failure of I/CB.S=LOS orLOF or HBER

PROMPT FR (QDLI) Inject RAI YES

AIS on I/C B.S. SERVICE (*) AIS (QDLI) Inject RAI YES

MFR-ALARM(TS16)

PROMPT MFR-LED(SIGN)

Inject RMFR YES

RAI(Bit 3, TS0)

SERVICE (*) RAI (QDLI) YES

AbnormalCircuit"AB"=11 in TS16

---------------(*) YES if CSV(Q33)enabled

10-6 < BER < 10-3

(LBER)DEFERRED

RMFR (TS16) SERVICE (*) YES

(*) Alarm classification may be changed by configuration


92050003-02 3-15

Table 3-7. Bearer Side Interface Alarms

FAULTCONDITIONSBEARER-SIDE

LOCAL,DCMEALARMDEFAULT

BR-QDLILEDINDICATOR

GENERATETOWARDLOCAL ISC(TRUNKSIDE)

GENERATE ON BEARERTO SELECTEDCORRESP. DCME

ALARMINDICATIONON RELEVANTCCTS.

BACKWARD ALARMINDICATIONIN CC Bit)

BACKWARDALARMINDICATION INTS$ Bit3)

Failure of I/CBearer = LOSor LOFor HBER

PROMPT FR (BR-QDLI) InjectAIS/64K &A,B="11" onTS16 (Note 1)

YES Inject RAI if allBearers in conf.are in failure orAIS

AIS on I/CBearer

SERVICE (*) AIS(BR-QDLI)

InjectAIS/64K &A,B="11" onTS16 (Note 1)

YES Inject RAI if allBearers in conf.are in failure orAIS

RAI(Bit3, TS0)

SERVICE (*) RAI(BR-QDLI)


YES

10-6 < BER < 10-3

(LBER) in2MB Bearer

DEFERRED(*)

Loss ofDCME Frame(LDFA)

PROMPT InjectAIS/64K &A,B="11" onTS16 (Note 1)

YES

BER >10-3 in CC(CC-HBER)

PROMPT InjectAIS/64K &A,B="11" onTS16 (Note 1)

YES

BearerBackwardAlarm

SERVICE (*) InjectAIS/64K &A,B="11" onTS16 (Note 1)

AIS in CC(CC-AIS)

SERVICE (*) InjectAIS/64K &A,B="11" onTS16 (Note 1)

YES

Fault Indication ofaffected trunkchannel inCC (IT-Alarm)


10-6 < BER < 10-3

in CC (CC-LBER)DEFERRED(*)

(*) Alarm classification may be changed by configuration.

Note 1. If alarm extension per Bitstream is enabled, then AIS/2MB should be injected only if all TS of the trunk BS are in "INJECT AIS/64K" condition

92050003-02 4-1

4

SYSTEM ALARMS AND EVENTS

4.1 System EventsTable 4-1 describes a mapping between the DTX-360 terminal events and CMIPnotifications. For each event the following data is given:

Event name: Name of the event.

Default Alarm Severity:

If applicable, this column shows the corresponding default severity of the alarmgenerated by the event. An empty value means not applicable.

Parameter for Instance Identification:

Parameter of the event which is used to identify the managed object which emittedthe notification, i.e., the RDN (Relative Distinguished Name) of that object.

Other Event Parameters:

Additional parameters of the event: ON/OFF is a popular parameter; it means that anotification is sent when this event occurs (the parameter values ON) and anothernotification is sent when the event is terminated (the parameter values OFF).

Notification:

Name of the corresponding notification which sent by the managed object via theCMIP EVENT-REPORT primitive for reporting the event.

All the following events, shown in the table below, are inserted into the event log ofthe corresponding DTX-360 terminal, and they are displayed in the event report.

Section 4 DTX-360System Alarms and Events Maintenance

4-2 92050003-02

Table 4-1. DTX-360 Events Mapping

EVENT NAME DEFAULTALARMSEVERITY

PARAMETER FORINSTANCE ID

OTHER EVENTPARAMETERS

NOTIFICATION

PROMPT trunk # ON/OFF communicationsAlarm

SERVICE trunk # ON/OFF communicationsAlarm

PROMPT dest # ON/OFF communicationsAlarm

dest # ON/OFF communicationsAlarm

EVENT trunk # ON/OFF communicationsAlarm

EVENT clock type SOURCE # equipmentAlarm

clock type SOURCE # protectionSwitchReporting

EVENT Card Name (ID) equipmentAlarm

BS Serviced by red. EVENT trunk # or Rx bearer # RED. CARD # protectionSwitchReporting

Terminal bit failure Card Name (ID) REASON equipmentAlarm

Software downloaderror

EVENT Card Name softwareAlarm

SERVICE dest # ON/OFF communicationsAlarm

EVENT bc # DEST #, DEC # channelCheck FailureReport

EVENT bc # DEST #, ENC #,F.E. DEC #

channelCheck FailureReport

EVENT bc # remoteMapSwitch Report

statisticsAlarm EVENT dest # STATISTICS NAME Statistics Alarm

TERMINAL ALARMSTATE

dest # AlarmState(Normal/Service/Deferred/Prompt/Critical)

stateChange

DLC Voice/VBD NE EVENT terminal ID ON/OFF attributeValueChange

DLC Voice/VBD NE EVENT dest # ON/OFF attributeValueChange

DLC 64Kbs NE EVENT dest # ON/OFF attributeValueChange

DLC 64Kbs NE EVENT dest # ON/OFF attributeValueChange

TERMINAL STATUS dest # MAINTENANCE/BYPASS/ON_LINE/OFF_LINE/OUT_OF_CONFIG

attributeValueChange

ACO terminal ID ON/OFF attributeValueChange

RX CHANNEL_CHKAlarm

EVENT dest # ON/OFF communicationsAlarm

TX CHANNEL_CHKAlarm

EVENT dest # ON/OFF communicationsAlarm

clock type ON/OFF communicationsAlarm

DTX-360 Section 4Maintenance System Alarms and Events

92050003-02 4-3

4.2 CCOM EventsTable 4-2 describes the CCOM events reported to the OPS:

Event name: Name of the event

Default Alarm Severity

If applicable, this column shows the corresponding default severity of the alarmgenerated by the event. An empty value means not applicable.

Class

Managed object class which emits the notification. In this case it can be one of thefollowing: dcmeCluster or dcmeCCOM.

Event Parameters: Parameters of the event.

Notification

Name of the corresponding notification which is sent by the managed object via theCMIP EVENT-REPORT primitive for reporting the event.

Table 4-2: CCOM Events Mapping


CLASS EVENTPARAMETERS

NOTIFICATION

CCOM ACO dcmeCCOM ON/OFF attributeValueChange

TERMINALSWITCHED TOREDUNDANT

DEFERRED dcmeClusterNE TERMINAL #,manual/automatic,ON/OFF

attributeValueChange

PROTECTIONMATRIX

PROMPT dcmeCCOM equipmentAlarm

TERMINALCRITICAL ALARM

dcmeClusterNE TERMINAL # equipmentAlarm

CLUSTER ALARMSTATE

dcmeClusterNE Cluster-AlarmState(Normal/Service/Deferred/Prompt)

stateChange

CCOM ALARMSTATE

dcmeCCOM CCOM-AlarmState(Normal/Deferred/Prompt)

stateChange


4-4 92050003-02

4.3 OPS ActionsTable 4-3 lists the OPS actions (user events) in the DTX-360 system. For each userevent the following data is given:


Default Alarm Severity

If applicable, this column shows the corresponding default severity of the alarmgenerated by the event.

Parameters: Parameters of the event

Source:

Indicates how the event originated, for example, due to a user operation, a response fromthe DCME terminal, etc.


92050003-02 4-5

Table 4-3. OPS (User) Events

EVENT NAME DEFAULT ALARMSEVERITY

PARAMETERS SOURCE

DOWNLOAD TOBACKGROUND MAP

EVENT User operation

ENABLE MAP SWITCH EVENT User operation

MAP SWITCH EVENT User operation

DISABLE MAP SWITCH EVENT User operation

SELECTIVE UPDATE EVENT User operation

RESET EVENT User operation

BYPASS EVENT User operation

RELEASE BYPASS EVENT User operation

CHANGE-OVER EVENT User operation

CHANGE-OVER RELEASE EVENT User operation

DCME MAINTENANCERELEASE REQUEST

EVENT NORMAL/FORCED,release timeout

User operation

TRUNK MAINTENANCERELEASE REQUEST

EVENT NORMAL/FORCED,TRUNK BS# releasetimeout

User operation

CANCEL MAINTENANCERELEASE

EVENT TRUNK BS# (?) User operation

MAINTENANCELOOPBACK

EVENT TRUNK BS #

MAINTENANCE TESTMODE

EVENT TRUNK BS #

ACO EVENT User operation

CONFLICT BETWEEN OPSAND DCME DATA

DEFERRED Event raised afterACTION reply


PROMPT Event raised aftertimeout


PROMPT Event raised aftertimeout


4-6 92050003-02

4.4 DTX-360 Responses to OPS ActionsTable 4-4 lists events that are displayed in the event report that correspond withresponses from the DTX-360 to user actions. For each event the following data is given:


Default Alarm Severity:

If applicable, this column shows the corresponding default severity of the alarmgenerated by the event.

Parameters: Parameters of the event

Source:

Indicates how the event originated, for example, due to an immediate reply to a useroperation, an acknowledge from the ISC, etc.


92050003-02 4-7

Table 4-4. DTX-360 Responses to OPS Events


PARAMETERS SOURCE

BACKGROUND MAP DOWNLOADACKNOWLEDGED

EVENT User operation reply

MAP SWITCH ENABLED EVENT ACK/NACK User operation reply

MAP SWITCH DISABLED EVENT User operation reply

MAP SWITCH ACKNOWLEDGED EVENT User operation reply

SELECTIVE UPDATEACKNOWLEDGED


RESET ACKNOWLEDGED EVENT User operation reply

BYPASS ACKNOWLEDGED EVENT User operation reply

RELEASE BYPASSACKNOWLEDGED


CHANGE OVER ACKNOWLEDGED EVENT User operation reply

CHANGE-OVER RELEASEACKNOWLEDGED


DCME MAINTENANCE RELEASEREQUEST ACKNOWLEDGED

EVENT NORMAL/FORCED Event raised after ISCacknowledge

TRUNK MAINTENANCE RELEASEREQUEST ACKNOWLEDGED

EVENT NORMAL/FORCED,TRUNK BS#

Event raised after ISCacknowledge

TRUNK MAINTENANCE RELEASEREQUEST NOT ACKNOWLEDGED

EVENT TRUNK BS # Event raised after timeout

TRUNK CLEAR OF TRAFFIC EVENT TRUNK BS # Event raised after ISCacknowledge

DCME CLEAR OF TRAFFIC EVENT Event raised after ISCacknowledge

DCME FORCED RELEASEACTIVATED (TIMEOUT EXPIRED)

EVENT Event raised after timeout

DCME CIRCUITS NOT IDLE(TIMEOUT EXPIRED)

EVENT Event raised after timeout

TRUNK FORCED RELEASEACTIVATED (TIMEOUT EXPIRED)


TRUNK CIRCUITS NOT IDLE(TIMEOUT EXPIRED)


MAINTENANCE RELEASECANCELED

EVENT TRUNK BS #(?) User operation reply


4-8 92050003-02

The OPS informs the Operator, on request, about BIT alarms.

BUILT-IN TEST REPORT

SEVERITY CARD FAIL ATTRIBUTE SLOT #

CRITICAL T-CPU TX 6 (20)

CRITICAL R-CPU RX 40 (12)

CRITICAL S-CPU SA 5 (19)

CRITICAL* TDSP 1 TX-1 11 (24)

CRITICAL* TDSP 2 TX-2 13 (26)

CRITICAL* RDSP RX 47 (17)

CRITICAL

CRITICAL

SDSP 1

SDSP 2

SA

SA

3 (18)

4

CRITICAL* QDLI 1 TR 1-4 29 (5)

CRITICAL* QDLI 2 TR 5-8 30 (6)

CRITICAL* QDLI 3 TR 9-12 31

CRITICAL* QDLI BR 1-4 28 (4)

CRITICAL* QDLI RD-1 34 (7)

CRITICAL* QDLI RD-2 35

CRITICAL* RDSW 1 27 (3)

CRITICAL RDSW 2 33

CRITICAL* ADPC T TX 10 (23)

CRITICAL* ADPC R RX 46 (16)

CRITICAL CKSL 36 (8)

CRITICAL TSDF 37 (9)

CRITICAL SIGN 38 (10)

CRITICAL OMCP 39 (11)

CRITICAL DSIR 41 (13)

CRITICAL BMCR DST-1(1-2) 42 (14)

CRITICAL BMCR DST-3(3-4) 44 (15)

CRITICAL AUXC 1 (1)

CRITICAL DSIT 7 (21)

CRITICAL BMCT 8 (22)

For detailed INIT BIT RESULTS type: I<ENTER>

NOTES:1. CRITICAL* = BIT may decide that severity is only DEFERRED.2. Slot numbers in parentheses are for DTX-360COMPACT.3. BMCR attribute in parentheses are for 2-destination BMCR version.4. GDSP RX and GDSP SA will be replaced in the future by GSP RX and GSP SA, respectively (1617 DSP board).


92050003-02 4-9

4.5 Online BIT TestsThe following sections provide a description of the various online built-in tests.

4.5.1 SIGN Hardware Online Test Options

4.5.1.1 MFR Trunk (0:15)

The Multiframe Loss Alarm port is periodically polled and the result is stored in a logfile.

4.5.1.2 TRUNK OUT Path Test

By sampling and latching relevant bits in the Trunk Out (TO) bitstream the 486 CPU cancompare this byte with intended signaling data which was originated by its software.

4.5.1.3 CLEAR CHANNEL TRANSMITTER (transparent signaling)

The transmit line has timeslot which carries redundant known data. The line is sampledand checked by hardware and the result bit ('0' = pass) is read by 486 CPU via port.

4.5.1.4 CLEAR CHANNEL RECEIVER

A Test pattern can be injected at the receiver side to one of the 16 trunks instead of thereal traffic coming from the bearer thus allowing to check whether predicted informationhas been received. The real data of the injected trunk is lost during this test.

4.5.1.5 TRUNK IN Path Test

Note: This sub-test should be performed if there is Multiframe Loss Alarm in 2 consecutive inputtrunks for a certain time period and it is likely that the signaling detector has failed.

This signaling detector is then disconnected from the real traffic and a test pattern isinjected into it. If the Multiframe Loss Alarm is now OFF and the predicted signalingdata is debounced by this detector then the problem is outside the SIGN card.

4.5.1.6 SIGN Loop Back Test

The 386 SIGN CPU initiates a signaling test sequence by writing data to the Trunk OutControl Memory, This pattern is sent to the QDLI which closes the internalLOOPBACK path between Trunk_Out and Trunk_In. The initiated signaling data onTrunk Out should be received by the detector (87c51) on Trunk In path and reported tothe 486 CPU. If the desired data was not received within 20 msec a FAILUREMESSAGE should be reported.


4-10 92050003-02

4.5.2 AUXC ONLINE BIT

4.5.2.1 DSP TEST

This test checks the communication with the DSP by means of keep alive messages.

4.5.2.2 PPI TEST

This test performs reading of the output ports and compares it to an image register.

4.5.2.3 PEB TX TEST

This test verifies the operation of the TDSI1 MATRIX by means of write/read to controlmemory and by means of establishing routing from input bitstream to test point atoutput 7.

4.5.2.4 PEB RX TEST

This test verifies the operation of the TDSI1 MATRIX by means of write/read to controlmemory and by means of establishing routing from input bitstream to test point atoutput 7.

4.5.2.5 AUXC 188EC ONLINE EPROM CHECK SUM

The program can read the EPROM content, make a sum of the data, and compare it to avalue stored in the EPROM.

4.5.2.6 AUXC 188EC ONLINE FLASH CHECK SUM

The program can read the Flash Memory content, make a sum of the data, and compareit to a value stored in the Flash.

4.5.2.7 AUXC 188EC ONLINE RAM CHECK

(performed in the boot process)

The program writes a specific data to specific locations in the RAM. Afterwards theprogram compares the data in the RAM.

4.5.2.8 AUXC ONLINE INTERRUPT TEST

The main program examines the interrupts. This is done by declaring a counter for eachinterrupt and examining the count value against another known interrupt time. Forexample, the 2msec interrupt output can be the time base for checking the timer interruptor vice-versa. It should check that X interrupts from one input are arriving in Yinterrupts from another input.

4.5.2.9 AUXC 188EC ONLINE TIMER TEST

There are three timers. One produces a pre-scaled clock and the two others generateinterrupts. The timers are checked by their interrupt. This check is included in theInterrupt controller check.


92050003-02 4-11

4.5.3 AUXC 188EC ONLINE HDLC TEST

The integrity of the HDLC channels is checked by transmitting a known string andacknowledging it by receiving data from the other side (KEEP ALIVE).

4.5.3.1 AUXC 188EC ONLINE DMA TEST

The DMA is checked by the same program which checks the HDLC. The data transferflows through the DME.

4.5.3.2 AUXC 188C ONLINE PORT TEST

The ports in the card are tested by reading them and comparing the data against data thatshould be stored in them.


4-12 92050003-02

4.5.4 SCPU 188EC ONLINE BIT

4.5.4.1 SCPU ONLINE EPROM CHECK SUM

The program can read the EPROM content and make a sum of the data and compare it toa value stored in the EPROM.

4.5.4.2 SCPU ONLINE FLASH CHECK SUM

The program can read the Flash Memory content, , make a sum of the data, and compareit to a value stored in the Memory.

4.5.4.3 SCPU ONLINE RAM CHECK

(performed in the boot process)

The program writes a specific data to specific locations in the RAM. Afterwards theprogram compares the data in the RAM.

4.5.4.4 SCPU ONLINE INTERRUPT TEST

The main program examines the interrupts for interval. This is done by declaring acounter for each interrupt and examining the count value against another knowninterrupt time. For example, the 2msec int. output can be the time base for checking thetimer interrupt or vice- versa. It should check that X interrupts from one input arearriving in Y interrupts from another input.

4.5.4.5 SCPU ONLINE TIMER TEST

There are three timers. One produces a pre-scaled clock and the two others generateinterrupts. The timers will be checked by their interrupt. This check is included in theInterrupt controller check.

4.5.4.6 SCPU ONLINE HDLC TEST

The integrity of the HDLC channels will be checked by transmitting a known string andacknowledging it by receiving data from the other side (KEEP ALIVE).

4.5.4.7 SCPU ONLINE DMA TEST

The DMA is checked by the same program which checks the HDLC. The data transferflows through the DMA.

4.5.4.8 SCPU ONLINE PORT TEST



92050003-02 4-13

4.5.5 BMCT ONLINE BIT

4.5.5.1 GENERAL

This section describes briefly the items tested in the BMCT card after reset in hardwareblock.

4.5.5.2 TEST CIRCUIT

The test circuit is checked by connecting to it a known pattern.

4.5.5.3 CONTROL MEMORIES WRITE READ:

The CPU writes 0x55555555 and 0xAAAAAAAA to the VBR, FAX IN, FAX OUTcontrol memories and reads them back at the same 2 msec to verify writing.

4.5.5.4 BRT BMCT TS0:

The bearer output TS0 BIT 2 is checked to be alternating every pcm frame. This verifiesthe output PAL operation.

4.5.5.5 BMRT BMCT BARKER:

Correct barker is checked on the BMCT output. This verifies the barker transmitteroperation.

4.5.5.6 FAX OUT & VBR CONTROL MEMORY:

The functioning of the FAX OUT and the VBR CONTROL MEMORY is verified, byrouting data from the FAX OUT DOUBLE BUFFER on TS 32 and receiving it back bythe test circuit.

4.5.5.7 BCMODT#N TS0

On the 4 output bitstreams, BCMODT#N TS0 BIT 2 is checked to be alternating everyPCM frame. This verifies that the MODE CONTROL TRIPLE BUFFER is operating.

4.5.5.8 BMCT ONLINE EPROM CHECK SUM


4.5.5.9 BMCT ONLINE RAM CHECK

The program will write a specific data to specific locations in the RAM. Afterwards theprogram will compare the data in the RAM.

4.5.5.10 BMCT ONLINE FLASH CHECK SUM

The program can read the Flash Memory content. make a sum of the data, and compareit to a value stored in the Flash Memory.


4-14 92050003-02

4.5.5.11 BMCT ONLINE INTERRUPT TEST

The main program examines the interrupts for interval. This is done by declaring acounter for each interrupt and examining the count value against another knowninterrupt time. For example, the 2msec interrupt output can be the time base forchecking the timer interrupt or vice-versa. It should check that X interrupts from oneinput are arriving in Y interrupts from another input.

4.5.5.12 BMCT ONLINE TIMER TEST


4.5.5.13 BMCT ONLINE HDLC TEST

The integrity of the HDLC channels are checked by transmitting a known string andacknowledging it by receiving data from the other side (KEEP ALIVE).

4.5.5.14 BMCT ONLINE DMA TEST


4.5.5.15 BMCT ONLINE PORT TEST



92050003-02 4-15

4.5.6 BMCR CPU ONLINE TEST

4.5.6.1 GENERAL

This document describe briefly the items tested in the BMCT card after reset inhardware.

4.5.6.2 CONTROL MEMORIES WRITE READ

The CPU writes 0x55555555 and 0xAAAAAAAA to the VBR, FAX IN, FAX OUTcontrol memories and reads them back at the same 2 msec to verify writing.

4.5.6.3 BCBSR#N TS0

On the 8 output bitstreams BCBSR#N TS0 BIT 2 is checked to be alternating everyPCM frame. This verifies the output circuit of these lines.

4.5.6.4 BCMDR#N TS0

On the 8 output bitstreams BCMDR#N TS0 BIT 2 is checked to be alternating everyPCM frame. This verifies that the MODE CONTROL DOUBLE BUFFER is operating.

4.5.6.5 FAXBSR#N TS0

On the 8 output bitstreams FAXBSR#N TS0 BIT 2 is checked to be alternating everyPCM frame. This verifies the FAX OUT DOUBLE BUFFER and the data transmissionof fax data to the DSPs.

4.5.6.6 BMCR ONLINE EPROM CHECK SUM

The program can read the EPROM content, make a sum of the data and compare it to avalue stored in the EPROM.

4.5.6.7 BMCR ONLINE RAM CHECK

The program will write a specific data to specific locations in the RAM. Afterwards theprogram compares the data in the RAM.

4.5.6.8 BMCR ONLINE FLASH CHECK SUM

The program can read the Flash Memory content and make a sum of the data andcompare it to a value stored in the Flash Memory.

4.5.6.9 BMCR ONLINE INTERRUPT TEST

The main program will examine the interrupts for interval. This is done by declaring acounter for each interrupt and examine the count value against another known interrupttime. For example, the 2msec interrupt output can be the time base for checking thetimer interrupt or vice-versa. It should check that X interrupts from one input arearriving in Y interrupts from another input.


4-16 92050003-02

4.5.6.10 BMCR ONLINE TIMER TEST


4.5.6.11 BMCR ONLINE HDLC TEST


4.5.6.12 BMCR ONLINE DMA TEST


4.5.6.13 BMCR ONLINE PORT TEST



92050003-02 4-17

4.5.7 CKSL ONLINE BIT SPECIFICATIONS

4.5.7.1 PPI DATA BUS TEST

During this test, only the output port is tested. The PPI data bus is read and compared tothe image.

4.5.7.2 CKSL 12V TEST

This test detects that the +/- 12 volt supplied by the DC-DC converter is in the permittedranges; +/- volt is the power source of the APLL located in the CKSL card. A fault inthis test means that the APLL is out of normal operation.

4.5.7.3 PLL LOCK TEST

This test detects if the APLL is in normal operation.

4.5.7.4 TIMING TEST

This test performs system timing accuracy tests with the CKSL internal timer.


4-18 92050003-02

4.5.8 XDSP ONLINE BIT (SDSP/TDSP/RDSP)

4.5.8.1 GENERAL

The SDSP cells (DSP devices) are tested by means of sine signal injection from theDSIT card towards the SDSP card and detection of this tone by the SCPU.

4.5.8.2 SDSP ODD CELL TEST

This test verifies that each odd cell is able to detect the sine signal. The test procedure isas follows:

1. A 1400Hz signal is routed by SMAT MATRIX toward odd cells (I.T801-IT815)

2. The SDSP wait for 8 Act_on, 8 Tone_On and 8 Sine messages with the appropriateI.T. number.

3. An Idle signal is routed by SMAT MATRIX toward the ITs

4. The SDSP waits for Act_off messages with the appropriate I.T. number

4.5.8.3 XDSP HDLC PORT

This test performs reading of the HDLC output port and compares it to an imageregister.

4.5.8.4 XDSP DSP_RES1 PORT

This test performs reading of the RES1 output port and compares it to an image register.

4.5.8.5 XDSP DSP_RES2 PORT

This test performs reading of the RES1 output port and compares it to an image register.

4.5.8.6 XDSP BS CM DATA TEST

This test performs reading of the control memory data and compares it to an imagememory.

4.5.8.7 XDSP DSP CELL 0-15 TEST

This test performs KEEP ALIVE REQUEST Messages to the DSP cells, and waits forKEEP ALIVE RESPONSE Messages from the cells. (KEEP ALIVE RESPONSEincludes the results of the TDSP test.)

4.5.8.8 188EC ONLINE EPROM CHECK SUM


4.5.8.9 188EC ONLINE FLASH CHECK SUM

The program can read the Flash Memory content, make a sum of the data, and compareit to a value stored in the Flash Memory.


92050003-02 4-19

4.5.8.10 188EC ONLINE RAM CHECK

The program writes a specific data to specific locations in the RAM. Afterwards theprogram compares the data in RAM.

4.5.8.11 188EC ONLINE INTERRUPT TEST


4.5.8.12 188EC ONLINE TIMER TEST


4.5.8.13 188EC ONLINE HDLC TEST


4.5.8.14 188EC ONLINE DMA TEST


4.5.8.15 188C ONLINE PORT TEST

The ports in the card are tested by reading them and comparing against the data thatshould be stored in them.

4.5.8.16 TDSP CELL TEST

1. TCPU selects a free DSP task from the DSP task FIFO.

2. TCPU sends an assign task with I.T. number = 800 + DSP task number (1-192).

3. TCPU waits for "fax data ready" message from TDSP.

4. TCPU sends "start fax data message" to TDSP task.

5. TCPU checks the test results in the Fax Pattern Detector port.

4.5.8.17 FDSP CELL TEST

The FDSP cells (DSP devices) are tested by means of sending a Fax signal (trainingsignal with data) towards the FDSP cell and detecting its output by the FPD (Fax Patterndetector) located at the DSIT card. The structure of the Fax signal is as follows: 30msecof idle signal + 230msec of training signal + 1msec of 55H, AAH data.


4-20 92050003-02

4.5.8.18 RDSP ODD CELLS TEST

Each odd cell transmits a 2000Hz signal on its TS2 output. This signal is routed by theRDSI and MDSW matrices towards the TS2 input of the same odd cell. The inputtimeslot is in SPD mode and so it detects the 2000Hz signal and reports to the RCPU.


92050003-02 4-21

4.5.9 XCPU ONLINE TEST

4.5.9.1 XCPU ONLINE EPROM CHECK SUM


4.5.9.2 XCPU ONLINE RAM CHECK

(Performed in the boot process)

The program writes specific data to specific locations in the RAM. Afterwards theprogram will compare the data in RAM.

4.5.9.3 XCPU ONLINE FLASH CHECK SUM


4.5.9.4 XCPU ONLINE INTERRUPT TEST


4.5.9.5 XCPU ONLINE TIMER TEST


4.5.9.6 XCPU ONLINE HDLC TEST


4.5.9.7 XCPU ONLINE DMA TEST


4.5.9.8 XCPU ONLINE PORT TEST



4-22 92050003-02

4.5.10 OMCP ONLINE TEST

4.5.10.1 OMCP ONLINE EPROM CHECK SUM


4.5.10.2 OMCP ONLINE RAM CHECK

(Performed in the boot process)

The program writes specific data to specific locations in the RAM. Afterwards, theprogram will compare the data in RAM.

4.5.10.3 OMCP ONLINE FLASH CHECK SUM


4.5.10.4 OMCP ONLINE INTERRUPT TEST

The main program examines the interrupts for interval. This is done by declaring acounter for each interrupt and examining the count value against another knowninterrupt time. For example, the 2msec interrupt output can be the time base forchecking the timer interrupt or vice versa. It should check that X interrupts from oneinput are arriving in Y interrupts from another input.

4.5.10.5 OMCP ONLINE TIMER TEST

There are three timers. One produces a pre-scaled clock and the other two generateinterrupts. The timers are checked by their interrupt. This check is included in theInterrupt controller check.

4.5.10.6 OMCP ONLINE HDLC TEST


4.5.10.7 OMCP ONLINE DMA TEST


4.5.10.8 OMCP ONLINE LAN CONTROLLER TEST

The KEEP ALIVE test checks the integrity of the LAN controller by sending messagesbetween the OMCP card (via the LAN controller on the card) and the OPS, and viceversa.


92050003-02 4-23

4.5.10.9 OMCP ONLINE REAL TIME CLOCK TEST

The Real Time Clock Test compares clock time on the OMCP card with clock time onthe OPS, and in case of a discrepancy, the OMCP readjusts its time in order to be insynchronization with the OPS clock time.

4.5.10.10 OMCP ONLINE POWER FAILURE TEST

In the event of a power failure in the Power Supply Unit, an event will be shown in thelog of the History Report of OPS Main Menu Reports.

4.5.10.11 OMCP ONLINE PORT TEST



4-24 92050003-02

4.5.11 DSIT TEST DESCRIPTION

4.5.11.1 GENERAL

The TCPU is responsible for performing the BIT process in the DSIT card. Thefollowing hardware facilities are used for this purpose:

a) ACFA device which is used as PCM FAS word detector.b) Timeslot 0 pattern generator, implemented in the timing circuit.c) Test pattern generator (tones and fax signal, end to end pattern)d) Fax Demodulator data detector (EB21H pattern detector)

4.5.11.2 DSIT T_PPI TEST

This test performs a reading of the output ports and compares it to an image register.

4.5.11.3 DSIT XILINX TEST

This test verifies that the XILINX is in operational state.

4.5.11.4 DSIT 12 TEST

This test detects that the +/- 12 volt supplied by the DC-DC converters is in thepermitted ranges; +/- 12 volt is the power source of the PLL located in the DSIT card. Afault in this test means that the PLL is out of normal operation.

4.5.11.5 DSIT PLL TEST

This test detects a no lock condition of the PLL.

4.5.11.6 ACFA TEST (Alarm Simulation)

This test checks the alarm detection circuit of the ACFA; the purpose of this test is toeliminate a false alarm detection.

4.5.11.7 TS0 PATTERN GENERATOR TEST

This test checks the TS0 pattern generator. The test is performed by using the ACFAdevice as TS0 detector.

4.5.11.8 DSIT INPUT BITSTREAMS TEST

This test checks 8 input bitstreams coming from the TSDF card and carries the ITs. Thetest is performed by means of a timeslot test; each Timeslot 0 input is connected througha Mux to the ACFA device located in the DSIT card.

4.5.11.9 DSIT ENC2BC MATRIX TEST

This test verifies the operation of the ENC2BC MATRIX by means of read/write to thecontrol memory and by means of establishing routing from input bitstream to test pointat output 7.


92050003-02 4-25

4.5.12 DSIT ENC2BC MATRIX INPUT BITSTREAMS BIT

This test checks the following incoming bitstream: LDCT (0:2) from LDC_TX cardADPCT (0:1) from ADPC-TX card

4.5.12.1 DSIT MODE MATRIX TEST

This test verifies the operation of the MODE MATRIX by means of read/write to thecontrol memory and by means of establishing routing from input bitstreams to test pointat output 7.

4.5.12.2 DSIT MODE MATRIX INPUT BS TEST (TS0 TEST)

This test checks the following incoming bitstream: BMCODT(0:3) from BMCT card.

4.5.12.3 DSIT DMUX CM TEST

This test verifies the operation of the DMUX by means of write/read to the controlmemory.

4.5.12.4 DSIT TDSI1 MATRIX TEST

This test verifies the operation of the TDSI1 MATRIX by means of write/read to thecontrol memory and by means of establishing routing from input bitstream to test pointat output 7.

4.5.12.5 DSIT TDSI2 MATRIX TEST

This test verifies the operation of the TDSI2 MATRIX by means of write/read to thecontrol memory and by means of establishing routing from input bitstream to test pointat output 7.

4.5.12.6 DSIT SHORT DELAY MEMORY TEST

This test checks the 28.750msec delay memory RAM by means of TS0 test.

4.5.12.7 DSIT LONG DELAY MEMORY TEST

This test checks the LONG delay memory RAM by means of TS0 test. This test pathincludes also the SHORT delay memory RAM.

4.5.12.8 DSIT SIGNAL GENERATOR TEST

This test checks the signal generator by means of TS0 test.

4.5.12.9 DSIT FPD (FAX PATTERN DETECTOR) TEST

This test verifies that the FPD detects the 55, AA pattern properly.

4.5.12.10 DSIT SMAT TS0 TEST

This test is a partial test of the SMAT MATRIX, the test verifies that the routing ofinput TS0 Pattern done under the control of the SCPU was done appropriately.


4-26 92050003-02

4.5.13 ADPC ONLINE GENERIC DESCRIPTION

The ADPC online BIT process contains the following sub-tests:

1. DPR Test

2. Output Ports Test

3. PLL Lock Test

4. Test for the Codecs BIT Machine

5. Codecs Built-in Test

6. ADPC Bitstream Test (TS0 Test)

4.5.13.1 DPR Test

1. The DPR Test is performed by read/write to/from one unused address on the DPR.

2. While writing/reading, it should be noted that every 2 msec the timing changes theMSB of the accessed address.

4.5.13.2 Output Ports Test

The Output Port Test is performed by reading from the output ports and comparing tothe image value.

4.5.13.3 PLL Lock Test

The PLL Lock Test is performed by reading lock indication on the input port pin.

4.5.13.4 Test For The Codecs BIT Machine

1. General

The main task of the card is to perform: PCM to ADPCM transformation in the EncoderCard (Tx Side) & ADPCM to PCM transformation in Decoder Card (Rx Side).

2. BIT General Description

The ADPC Card includes a complex built-in Test Machine which inserts ITUPCM/ADPCM Patterns (bitstreams) into the tested Codec and compare the tested Codecoutput to the expected pattern stream. The input pattern streams and the expected outputpattern streams are stored in EPROM memory chips. The process is controlled by thetiming system of the Card and through the output ports.

3. Codecs BIT Machine Test Description.

This test checks the process described without passing through the Codecs. It isperformed by selecting specific modes for this test through the output ports, inserting atransparent pattern stream (from the EPROM), and comparing it without passing throughthe Codecs to the expected pattern on the EPROM.


92050003-02 4-27

4.5.13.5 Codecs Built-in Test.

1. BIT General Description

The ADPC Card BIT Machine inserts ITU PCM/ADPCM pattern streams into the testedCodec and compares the output to the expected pattern stream. The input pattern streamsand the expected output pattern streams are stored in the EPROM Memory Chips. Theprocess is controlled by the timing system of the Card and through the output ports.

2. Codecs BIT Machine Test Process

The Codecs BIT Machine Test is performed as follows:

a. Select the tested Codec (Codec-0, Codec-1, Codec-2, Codec-3, Codec-R) by writing to output port.

b. Select the corresponding law (A-law or µ-law) according to card configuration.

c. Select the specific test mode: 64 kbit/s (Transparent), 40 kbit/s, 32 kbit/s, 24 kbit/s, 16 kbit/s.

d. Reset the Codec BIT machine by writing to output port.

e. Start the Codec BIT Machine by writing to output port.

f. Read the test result by input port (after a delay for completing the test).

g. Select all the test modes (step 3) for each one of the Codecs (step 1).

4.5.13.6 ADPC Bitstream Test (TS0 Test)

1. The ADPC Bitstream Test is performed by routing one of the input bitstreams, one ofthe input mode streams, or one of the output bit-streams to the DSIR Card (if ADPCR)or to the DSIT Card (if ADPCT).

2. DSIR Card (if ADPCR) or DSIT Card (if ADPCT): bitstream is tested for Timeslot 0(TS0).


4-28 92050003-02

4.5.14 QDLI ONLINE BIT DESCRIPTION

4.5.14.1 GENERAL

The QDLI BIT process is performed for four Input Line Bitstreams Interfaces, in the T1or E1 format. The following hardware facilities are used for these tests:

• ACFA device used as PCM FAS word detector

• Timeslot 0 (TS0) pattern generator, implemented in the timing circuit

• PCM synchronizing Word Receiver built-in QDLI Xilinx

• Line Interface Unit monitoring transmit drive performance of DLIs

4.5.14.2 PPI TEST

Performs reading of the output ports and compares it to an image register.

4.5.14.3 QDLI ACFA DATA BUS TEST

Performs Read and Write from/to ACFA-IN(3:0) and ACFA-OUT(3:0) ControlRegister.

4.5.14.4 QDLI Xilinx REGISTERS TEST

Performs reading of the output port and compares it to an image register.

4.5.14.5 QDLI LIU OSL TEST

This test checks the output driver circuit of the Line Interface; the test is based on LIUself detector for the output driver circuit.

4.5.14.6 QDLI ACFA PARITY CHECK

This test checks the ACFA-IN elastic buffer.

4.5.14.7 QDLI LOCAL TS0 PATTERN GENERATOR TEST

The test checks the Local TS1 Pattern Generator by means of TS1 pattern detectorimplemented in the QDLI XILINX.

4.5.14.8 QDLI OUTPUT BITSTREAM TESTS

This test checks 2 output bitstreams (which contain the TCs) going to the TSDF card.The test is performed using data contained in Timeslot 0.

4.5.14.9 QDLI INPUT BITSTREAM TEST

This test checks 4 inputs: 2 bitstreams (which contain the TCs) coming from the TSDFand 2 bitstreams (which carry the signaling data) coming from the SIGN card.


92050003-02 4-29

4.5.14.10 QDLI LOOP BACK TEST

1. DLI DF (DOUBLE FRAME) LOOP BACK

This test performs a loop back test of a specific DLI.

The data is transmitted from the Test Generator Built-in QDLI Xilinx to ACFA-OUT intransparent mode and via Line Interface Unit in Local Loopback mode to ACFAIN.

This test should be performed for each DLI (1, 2, 3, 4).

2. DLI CRC LOOP BACK

This test is performed only for CRC defined bitstreams. This test is intended to inspectAlarms and CRC errors in ACFA-IN in Local Loop back mode.

This test should be defined for each DLI (1, 2, 3, 4)

3. DLI ALARM SIMULATION TEST

This test is based on a self built-in alarm simulation circuit located in each ACFAdevice. The device is defined to CRC4 mode. The above test should be defined for eachDLI (1, 2, 3, 4)


4-30 92050003-02

4.5.15 RDSW TEST

During normal operation, the CPU reads the status of the RSDW card. The RDSW cardcannot be tested online as it is a traffic-affected component. In the event that traffic isswitched to a redundant QDLI card, a successful change-over process, in effect, “tests”the operation of the RDSW card and confirms that it is functioning properly.


92050003-02 4-31

4.5.16 TSDF ONLINE BIT DESCRIPTION

4.5.16.1 GENERAL

The TSDF BIT process is performed over three PPI devices, two ACFA devices, aLOCAL TS0 generator, and seven MATRIX devices.

a) PPI devices are used as general purpose I/O ports.

b) ACFA devices are used as a PCM FAS word detector.

c) TS0 generator is used for local TS0 insertion.

d) MATRIX devices are used for TSI.

4.5.16.2 TSDF PPI TEST

The TSDF PPI Test performs a reading of the output ports and the control registers andcompares it to an image.

4.5.16.3 TSDF ACFA TEST (ALARM SIMULATION)

This test checks the alarm detection circuit of the ACFA.

The test is based upon a built-in alarm simulation self-test feature of the ACFA deviceand simulates a LOSS OF SYNCHRONIZATION.

4.5.16.4 TSDF LOCAL TS0 GENERATOR TEST

This test checks the TS0 generator and uses the ACFA device as a TS0 detector.


4-32 92050003-02

4.5.16.5 TSDF MATRIX TEST DESCRIPTION

This test performs synchronization, Connection Memory (CM), and connection testsover all MATRIX devices.

4.5.16.6 TSDF MATRIX SYNC TEST

This test checks whether or not incomplete instructions have been received by the deviceor if the device is asking for initialization. In the event that incomplete instructions havebeen received or if the device is asking for initialization, it is declared faulty.

4.5.16.7 TSDF MATRIX CM TEST

This test verifies that instructions given during initialization are properly carried out.

4.5.16.8 TSDF MATRIX SWITCH TEST

This test checks TS0 coming from the Matrix by means of the ACFA device (after theACFA device has confirmed that TS0 is present and operating properly).

4.5.16.9 TSDF MATRIX INPUT BS TEST

This test checks TS0 of the four incoming bitstreams as they enter and pass through theMatrix to the ACFA device.

4.5.16.10 TSDF MATRIX DEVICES

All TDSF MATRIX devices are checked in the same manner using the tests described inSections 4.4.16.6, 4.4.16.7, 4.4.16.8, and 4.5.16.9: SYNC TEST, CM TEST, SWITCHTEST, and INPUT BS TEST.

The tests include the following MATRIX devices:

a) TSDF RTSI1

b) TSDF RTSI2

c) TSDF BRTX

d) TSDF TTSI

e) TSDF SIGTX

f) TSDF BRRX

g) TSDF SIGTO


92050003-02 4-33

4.5.17 DSIR ONLINE BIT DESCRIPTION

4.5.17.1 GENERAL

The RCPU is responsible for performing the BIT process of the DSIR card and of theRDSP cells. The following hardware facilities are used for these tests:

a) ACFA device which is used as PCM FAS word detector.b) Timeslot 0 (TS0) pattern generator, implemented in the timing circuit.

4.5.17.2 DSIR R_PPI TEST

This test performs reading of the output ports and compares it to an image register.

4.5.17.3 DSIR XILINX TEST

This test verifies that the XILINX is in operational state.

4.5.17.4 DSIR 12 TEST

This test detects that the +/- 12 volt supplied by the DC-DC converters is in thepermitted ranges; +/- 12 volt is the power source of the PLL located in the DSIR card. Afault in this test means that the PLL is out of normal operation.

4.5.17.5 DSIR PLL TEST

This test detects a no lock condition of the PLL.

4.5.17.6 ACFA TEST (Alarm Simulation)

This test checks the alarm detection circuit of the ACFA. Its purpose is to eliminate afalse alarm detection.

4.5.17.7 TS0 PATTERN GENERATOR TEST

This test checks the TS0 pattern generator. The test is performed by using the ACFAdevice as TS0 detector.

4.5.17.8 DSIR INPUT BITSTREAMS TEST

This test checks 4 input bitstreams coming from the BMCR. The test is performed byusing data contained in Timeslot 0; each Timeslot 0 input is connected through a Mux toACFA device located in the DSIR card.

4.5.17.9 DSIR RDSI MATRIX TEST

This test verifies the operation of the RDSI MATRIX by means of read/write to thecontrol memory and by means of establishing routing from input bitstream to test pointat output 7.


4-34 92050003-02

4.5.17.10 DSIR MDSW MATRIX TEST

This test verifies the operation of the MDSW MATRIX by means of read/write to thecontrol memory and by means of establishing routing from input bitstreams to test pointat output 7.

4.5.17.11 DSIR MDSW MATRIX TEST INPUT BITSTREAMS TEST

This test checks the following incoming bitstreams: BCBSR(0:3)D(0:3) from the BMCRcard, FAXBSR(0:3) from BMCR card, and BMCDR(0:3)D(0:3) from the BMCR card.

4.5.17.12 DSIR INLV MATRIX TEST

This test verifies the operation of the INLV MATRIX by means of read/write to thecontrol memory and by means of establishing routing from input bitstreams to test pointat output 7.

4.5.17.13 DSIR INLV MATRIX INPUT BS TEST (TS0 TEST)

This test checks the following incoming bitstreams: INLV1 IN(0:7), INLV2 IN(0:7).

4.5.17.14 DSIR RDSP INPUT BS TEST (RDSP EVEN CELL TEST)

This test checks 4 input bitstreams coming from the RDSP. This is a Timeslot 0 test;each Timeslot 0 input is connected through the RDSI MATRIX to the ACFA devicelocated in the DSIR card. The TS0 source to this test is in the DSP even cells, so this testis also used as an RDSP EVEN CELLS test.

4.5.17.15 DSIR ADPC-RX INPUT BITSTREAMS TEST

This test checks 4 input bitstreams coming from the ADPC-RX. This is a Timeslot 0test; each Timeslot 0 input is connected through the RDSI MATRIX to the ACFAdevice located in the DSIR card.

4.5.17.16 DSIR TSDF INPUT BITSTREAMS TEST

This test checks 2 input bitstreams coming from the TSDF. The test is performed byusing data contained in Timeslot 0; each Timeslot 0 is connected through the RDSIMATRIX to the ACFA device located in the DSIR card.

4.5.17.17 DSIR “TEST-DSP” TEST

This test checks the communication with the DSP by means of KEEP ALIVE messagesand by means of a TS0 test of the DSP output.


92050003-02 4-35

4.6 Built-in Test DiagnosticsThis sub-section describes the online Test Descriptions for the DTX-360 System.

Table 4-5. Test Number and Range Per Card

Test # CARD RANGE

123456

OMCPXOMCPTSDFCKSLRDSW0RDSW1

0000-01990200-02990300-03990400-04990500-0599

7891011121314

TCPUXCPUDSITGDSP0 (card)GDSP0 (DSP cells)GDSP1 (card)GDSP1 (DSP cells)ADPC-TX

1000-10991100-11991200-12991300-13991400-14991500-15991600-1699

151617181920

RCPUXCPUDSIRRDSP (card)RDSP (DSP cells)ADPC-RX

2000-20992100-21992200-22992300-23992400-2499

2122232425

SCPUXCPUDSITGDSP(card)GDSP (DSP cells)

3000-30993100-31993200-32993300-3399

26 BMCT 4000-4199

27 SIGN 5000-5199

28 QDLI0 6000-6099

29 QDLI1 6100-6199

30 QDLI2 6200-6299

31 QDL13 6300-6399

32 QDLI4 6400-6499

33 QDLIRD 6500-6599

34 QDLIOP 6600-6699

35 AUXC 7000-7099

36 BMCR0 8000-8199

37 BMCR1 8200-8299


4-36 92050003-02

TABLE 4-6/1. OMCP TEST

TEST NUMBER TEST NAME

0000 OMCP BOOT TEST

0001 OMCP RAM TEST

0002 OMCP FLASH TEST

0003 OMCP INTERRUPT TEST

0004 OMCP TIMER TEST

0005 OMCP DMA TEST

0006 OMCP I/O PORT TEST

0007 OMCP REAL TIME CLOCK TEST

0008 OMCP LAN TEST

0009 OMCP 5V TEST

0010 OMCP 12V TEST

0011 OMCP PS 1 TEST

0012 OMCP PS 2 TEST

0013 OMCP PS 3 TEST

0014 OMCP PS 4 TEST

0015 OMCP PS 5 TEST

0016 OMCP PS 6 TEST

0017 OMCP AUXC HDLC LINK

0018 OMCP AUXC HDLC DEVICE

0019 OMCP SIGN HDLC LINK

0020 OMCP SIGN HDLC DEVICE

0021 OMCP TCPU HDLC LINK

0022 OMCP TCPU HDLC DEVICE

0023 OMCP RCPU HDLC LINK

0024 OMCP RCPU HDLC DEVICE

0025 OMCP S-CPU HDLC LINK


92050003-02 4-37



0026 OMCP S-CPU HDLC DEVICE

0027 OMCP BMCR0 HDLC LINK

0028 OMCP BMCR0 HDLC DEVICE

0029 OMCP BMCR1 HDLC LINK

0030 OMCP BMCR1 HDLC DEVICE

0031 OMCP BMCT HDLC LINK

0032 OMCP BMCT HDLC DEVICE


TESTS NUMBER TEST NAME

0034 OMCP QDLI0 HDLC LINK







0041 OMCP QDLI HDLC DEVICE

0042 RDSW0 UART LINK

0043 RDSW1 UART LINK


4-38 92050003-02

TABLE 4-7. TCPU ( XCPU ) TEST


1001 TCPU BOOT TEST

1002 TCPU RAM TEST

1003 TCPU FLASH TEST

1004 TCPU INTERRUPT TEST

1005 TCPU TIMER TEST

1006 TCPU DMA TEST

1007 TCPU I/O PORT TEST

1008 TCPU BMCT HDLC LINK

1009 TCPU BMCT HDLC DEVICE

1010 TCPU SIGN HDLC LINK

1011 TCPU SIGN HDLC DEVICE

1012 TCPU S-CPU HDLC LINK

1013 TCPU S-CPU HDLC DEVICE

1014 TCPU RCPU HDLC LINK

1015 TCPU RCPU HDLC DEVICE

1016 TCPU GDSP HDLC LINK

1017 TCPU GDSP HDLC DEVICE


92050003-02 4-39

TABLE 4-8/1. TCPU ( DSIT ) TEST


1100 DSIT T_PPI1 TEST

1101 DSIT T_PPI2 TEST

1102 DSIT 12V TEST

1103 DSIT XILINX TEST

1104 DSIT PLL TEST

1105 DSIT ACFA ALARM SIMULATION TEST

1106 DSIT ACFA IN MUX

1107 DSIT TS0 Pattern TEST

1108 DSIT PCMITT0_7

1109 DSIT ENC2BC

1110 DSIT ENCTO_2

1111 DSIT ADPCT0_1

1112 DSIT MODE

1113 DSIT BCMODT0_3

1114 DSIT TDSI1 TEST



1115 DSIT TDSI1 E.B. INPUT TEST

1116 DSIT TDSI2 TEST

1117 DSIT TDSI2 MODEO0_2 TEST

1118 DSIT TDSI2 LRETO0_2 TEST

1119 DSIT DMUX TESTDMUX CM

1120 DSIT TDSI1 INPUTS TEST


4-40 92050003-02



1121 DSIT TDSI2 INPUT TEST

1122 DSIT DM28 TEST

1123 DSIT DM200 TEST

1124 DSIT SMAT SWITCH TEST

1125 DSIT SIGNAL GEN TEST

1126 DSIT FDP TEST

TABLE 4-9. TCPU (GDSP0 card) TEST


1200 GDSP BOOT TEST

1201 GDSP RAM TEST

1202 GDSP FLASH TEST

1203 GDSP INTERRUPT TEST

1204 GDSP TIMER TEST

1205 GDSP DMA TEST

1206 GDSP I/O PORT TEST

1207 GDSP0 HDLC PPI

1208 GDSP0_RES1 PORT


1210 GDSP0 BS CM

TABLE 4-10. TCPU ( GDSP0 DSP CELLS) TEST


1300 GDSP0 CELL0 TEST




1304 GDSP0 CELL4 TESTT


1306 GDSP0 CELL6 TESTT




92050003-02 4-41

TABLE 4-11. TCPU TEST (GDSP0 DSP CELLS)









TABLE 4-12. TCPU TEST (GDSP1 card)


1400 GDSP1 BOOT TEST

1401 GDSP1 RAM TEST

1402 GDSP1 FLASH TEST

1403 GDSP1 INTERRUPT TEST

1404 GDSP1 TIMER TEST

1405 GDSP1 DMA TEST

1406 GDSP1 I/O PORT TEST

1407 GDSP1 HDLC PPI



1410 GDSP1 BS CM

TABLE 4-13/1. TCPU TEST (GDSP1 DSP CELLS )












4-42 92050003-02

TABLE 4-13/2. TCPU TEST ( GDSP1 DSP CELLS )









TABLE 4-14/1. ADPC-TX TEST


1600 ADPC-TX DPR TEST

1601 ADPC-TX PPI TEST

1602 ADPC-TX PLL TEST

1603 ADPC-TX BIT TESTER TEST

1604 ADPC-TX PCMENCT0 INPUT TEST

1605 ADPC-TX PCMENCT1 INPUT TEST

1606 ADPC-TX ENCMODT0 INPUT TEST

1607 ADPC-TX ENCMODT1 INPUT TEST

1608 ADPC-TX ADPCT0 OUTPUT TEST

1609 ADPC-TX ADPCT1 OUTPUT TEST

TABLE 4-14/2. ADPC-TX TEST


1610 ADPC-TX CODEC-0 TEST



1613 ADPC-TX CODEC-R TEST


92050003-02 4-43

TABLE 4-15. RCPU (XCPU) TEST


2000 RCPU BOOT TEST

2001 RCPU RAM TEST

2002 RCPU FLASH TEST

2003 RCPU INTERRUPT TEST

2004 RCPU TIMER TEST

2005 RCPU DMA TEST

2006 RCPU I/O PORT TEST

2007 RCPU BMCR0 HDLC LINK

2008 RCPU BMCR0 HDLC DEVICE




2012 RCPU BMCR2 HDLCDEVICE



2015 RCPU SIGN HDLC LINK

2016 RCPU SIGN HDLC DEVICE

2017 RCPU S-CPU HDLC LINK

2018 RCPU S-CPU HDLC DEVICE

2019 RCPU TCPU HDLC LINK

2020 RCPU TCPU HDLC DEVICE

2021 RCPU RDSP HDLC LINK

2022 RCPU RDSP HDLC DEVICE


4-44 92050003-02

TABLE 4-16/1. RCPU (DSIR) TEST


2100 DSIR T_PPI TEST

2101 DSIR 12V TEST

2102 DSIR XILINX TEST

2103 DSIR PLL TEST

2104 DSIR ACFA ALARM SIMULATION TEST

2105 DSIR TS0 PATTERN TEST

2106 DSIR RDSI TEST

2107 DSIR MDSW CM TEST

2108 DSIR BMCR0 OUTPUT TESTS






2112 DSIR BMCR0 / BMCR1 /FAX OUTPUT TESTS



2113 DSIR INLV TEST

2114 DSIR PCMDECR0_2 TEST

2115 DSIR BRRTDSF0_1

2116 DSIR CCTSTR TEST

2117 DSIR TEST-DSP TEST


92050003-02 4-45

TABLE 4-17. RCPU TEST (RDSP CARD)


2200 RDSP BOOT TEST

2201 RDSP RAM TEST

2202 RDSP FLASH TEST

2203 RDSP INTERRUPT TEST

2204 RDSP TIMER TEST

2205 RDSP DMA TEST

2206 RDSP I/O PORT TEST

2207 RDSP HDLC PPI

2208 RDSP_RES1 PORT

2209 RDSP_RES2 PORT

2210 RDSP BS CM

TABLE 4-18. RCPU TEST (DSP CELLS)


2300 RDSP CELL0 TEST



2303 RDSP CELL3 TESTT










2313 RDSP CELL13TEST




4-46 92050003-02

TABLE 4-19.CKSL TEST


0300 CKSL PPI TEST

0301 CKSL 12V TEST

0302 CKSL PLL TEST

0303 CKSL TX_CK

0304 CKSL CLDT

0305 CKSL SYNCT~

0306 CKSL CLDDT

0307 CKSL C1.5T

0308 CKSL RX_CK

0309 CKSL CLDR

0310 CKSL SYNCR~

0311 CKSL TO_CK

0312 CKSL CLDTO

0313 CKSL SYNCTO~

0314 CKSL C1.5TO

0315 CKSL MFTO

0316 CKSL INTCK

0317 CKSL INT 1.5M


92050003-02 4-47

TABLE 4-20/1. ADPC-RX TEST


2400 ADPC-RX DPR TEST

2401 ADPC-RX PPI TEST

2402 ADPC-RX PLL TEST

2403 ADPC-RX BIT TESTER TEST

2404 ADPC-RX ADPCR0 INPUT TEST



2407 ADPC-RX DECMODR0 INPUT TEST

2408 ADPC-RX DECMODR1 INPUT TEST

2409 ADPC-RX PCMDECR0 OUTPUT TEST



TABLE 4-20/2. ADPC-RX TEST


2412 ADPC-RX CODEC-0 TEST



2416 ADPC-RX CODEC-R TEST


4-48 92050003-02

TABLE 4-21/1. S-CPU TEST (XCPU)


3000 S-CPU BOOT TEST

3001 S-CPU RAM TEST

3002 S-CPU FLASH TEST

3003 S-CPU INTERRUPT TEST

3004 S-CPU TIMER TEST

3005 S-CPU DMA TEST

3006 S-CPU TCPU HDLC LINK FAIL

3007 S-CPU RCPU HDLC LINK FAIL

3008 S-CPU SIGN HDLC LINK FAIL

3009 S-CPU -DSP HDLC LINK FAIL

3010 S-CPU RDSP HDLC LINK FAIL

3011 S-CPU GDSP HDLC LINK FAIL

3012 S-CPU TCPU HDLC DEVICE FAIL

3013 S-CPU RCPU HDLC DEVICE FAIL

3014 S-CPU SIGN HDLC DEVICE FAIL

3015 S-CPU -DSP HDLC DEVICE FAIL

3016 S-CPU RDSP HDLC DEVICE FAIL

3017 S-CPU GDSP HDLC DEVICE FAIL

TABLE 4-22. S-CPU TEST (DSIT)


3100 DSIT S_PPI TEST

3101 DSIT SMAT TEST


92050003-02 4-49

TABLE 4-23. S-CPU TEST (GDSP CARD)


3200 GDSP BOOT TEST

3201 GDSP RAM TEST

3202 GDSP FLASH TEST

3203 GDSP INTERRUPT TEST

3204 GDSP TIMER TEST

3205 GDSP DMA TEST

3206 GDSP HDLC PPI

3207 GDSP_RES1 PORT

3208 GDSP_RES2 PORT

3209 GDSP BS CM

TABLE 4-24. S-CPU TEST (GDSP CELLS )


3300 GDSP CELL0 TEST





3305 GDSP CELL5 TEST GDSP CELL0 INPUT TEST












4-50 92050003-02

TABLE 4-25/1.QDLIx TEST (x = 1 to 6)


6x01 QDLIx PPI1 TEST




6x05 QDLIx XILINX DATA BUS

6x06 QDLIx LOCAL TS0 TEST

6x07 DLI0 ACFA-0 IN TEST




6x11 DLI0 ACFA-0 OUT DATA BUS TEST




6x15 DLI0 OSL TEST

6x16 DLI1 OSL TEST

6x17 DLI2 OSL TEST

6x18 DLI3 OSL TEST

6x19 QDLIx INPUT BS0 TEST

6x20 QDLIx INPUT BS1 TEST

6x21 QDLIx OUTPUT BS0 TEST

6x22 QDLIx OUTPUT BS1 TEST

6x23 QDLIx INPUT SIG0 TEST

6x24 QDLIx INPUT SIG1 TEST


92050003-02 4-51

TABLE 4-25/2. QDLIx TEST (x = 1 to 6)


6x25 DLI0 LOOP BACK TEST




TABLE 4-26. AUXC TEST


7000 PPI1 TEST

7001 PPI2 TEST

7002 PPI3 TEST

7003 PEB-RX TEST

7004 PEB-TX TEST

7005 DSP TEST

92050003-02 5-1

5

Jumper SettingsThis section describes the internal user-selectable DIP switches and jumpers located on the DTX-360cards.

5.1 DTX - 360 Terminal, Card Layout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26AUXC

GDSP

GDSP

-CPU/L

-CPU/L

DSIT/L

BMCT/L

ADPC

-DSP

-DSP

LDCH

LDCH

LDCH

LDCH

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52RDSW

QDLI

QDLI

QDLI

QDLI

RDSW

QDLI

QDLI

CKSL

TSDF/L

SIGN*

OMCP/L

-CPU/L

DSIR/L

BMCR/L

BMCR/L

ADPX

GDSP

LDCH

LDCH

LDCH

LDCH

5.2 DTX - 360C Compact Terminal, Card Layout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

AUXC

RDSW

QDLI

QDLI

QDLI

QDLI

CKSL

TSDF/L

SIGN*

OMCP/L

−CPU/L

DSIR/L

BMCR/L

BMCR/L

ADPX

GDSP

GDSP

-CPU/L

-CPU/L

DSIT/L

BMCT/L

ADPC

-DSP

-DSP

* In this document SIGN & SIGN/L named as SIGN .

Section 5 DTX-360Jumper Settings Maintenance

5-2 92050003-04

5.3 DTX - 360 Terminal, List of Card Jumper Settings

Card Dwg. No. SettingsAUXC 238009-7411-011 GivenADPC 238009-7412-011 "ADPX 238009-7412-021 "BPIF-1 238009-7416-011 "-DSP 238009-7420-011 "RDSW 238009-7421-011 "QDLI 238009-7422-011 "CKSL 238009-7423-011 "BPIF-0 238009-7426-011 "SIGN 238009-7430-011 "BPIF-2 238009-7436-011 "BPIF-3 238009-7446-011 GivenGDSP 238009-7467-011 GivenLDCT 238009-74xx-* GivenPS3V 238009-74xx-* None

DSIR /L 238009-7513-011 Given-CPU /L 238009-7514-011 "OMCP /L 238009-7515-011 "BMCT /L 238009-7518-011 "TSDF /L 238009-7535-011 "BMCR /L 238009-7540-011 "DSIT /L 238009-7543-011 "

DTX-360 Section 5Maintenance Jumper Settings

92050003-04 5-3

5.4 AUXC

5.4.1 AUXC Jumper Settings

JMP No. Function Setting DescriptionJP1 Select Program 1-2 Boot - Normal operation

Boot / Test 2-3 Test - Fluke testJP2 Select Operation 1-2 Clock - Normal operation

Clock / Watchdog 2-3 Watchdog enabled

5.4.2 AUXC Hard Wired

JMP No. Function Setting DescriptionJP3 Select operation 1-2 CPU - Normal operation

µ-law / A-law 2-3 A-law enabledJP4 Buzzer IN Normal operation

OUT Disabled

5.4.3 AUXC Location of Jumpers

J9

1

1

1


5-4 92050003-04

5.5 ADPC & ADPX

5.5.1 ADPC & ADPX Jumper Settings - None

5.5.2 ADPC & ADPX Hard Wired

JMP No. Function Setting DescriptionJP2 Automatic control 1-2 Normal operation

of test equipment 2-3 Fluke test

5.5.3 ADPC & ADPX Location of Jumpers

JP 21


92050003-04 5-5

5.6 CPU

5.6.1 CPU Jumper Settings

JMP No. Function Setting DescriptionJP1 Watchdog select 1-2 Disabled- Normal operation

2-3 EnabledJP2 Software select IN Test PROM

Test/ Boot OUT Boot - Normal operation

5.6.2 CPU Hard Wired

JMP No. Function Setting DescriptionJP3 Select operating IN 25 MHz

frequency OUT 33 MHz - Normal operationJP4 TRIST function IN Enabled

not in use OUT Disabled - Normal operationJP5 CPU BIT IN Enabled - Normal operation

OUT Disabled

5.6.3 CPU DIP Switch (U72) Settings

Pole No. Function Setting Description1 - 8 T. B. D. OFF (Open) Not in use

ON (Close) Not in use

5.6.4 CPU Location of Jumpers and DIP Switches

JP 2JP5

JP1

U72

1

JP3JP4


5-6 92050003-04

5.7 OMCP

5.7.1 OMCP Jumper Settings

JMP No. Function Setting DescriptionJP1 Select program IN Test program

OUT Normal operation (Boot)JP2 Select Watchdog 1-2 Disabled - Normal operation

2-3 Enabled

5.7.2 OMCP Hard Wired

JMP No. Function Setting DescriptionJP5 CPU self-test bit IN Enabled- Normal operation

OUT DisabledJP6 Select frequency IN 25 MHz - Normal operation

OUT 33 MHz

5.7.3 OMCP DIP Switch (U51) Settings

Pole No. Function Setting Description1 - 7 OFF (Open) Not in use

ON (Close) Not in use8 Monitor display OFF (Open) Monitor On - ECI

ON (Close) Monitor Off - ALCATEL

5.7.4 OMCP Location of Jumpers and DIP Switches

J1

J2

JP 2

JP1U183

1

JP6JP5

U51


92050003-04 5-7

5.8 BPIF/1

5.8.1 BPIF /1 Jumper Settings

JMP No. Function Setting DescriptionJP5 to JP12 Select input 1-2 for 75Ω (Note 2)

bitstream shield OUT for 100 or 120Ω (Note 3) Note 1 connection to CGND 2-3 option for 75Ω only (Note 4)

Notes: 1. Jumpers JP5 to JP12 correspond to trunks TR1 to TR8. 2. Shield of input bitstream connected to CGND with 0.1 µF capacitor 3. For 100 or 120Ω operation shield of input bitstream not connected to CGND 4. Shield of input bitstream connected to CGND (option for 75Ω only) .

5.8.2 BPIF /1 Hard Wired - None

5.8.3 BPIF /1 Location of Jumpers and DIP Switches

5.8.4 BMCT

5.8.5 BMCT Jumper Settings

JMP No. Function Setting DescriptionJP1 Watchdog 1-2 Disabled - Normal operation.

circuit control 2-3 Enabled - Future operation.JP2 WRITE enable for IN WRITE enabled

control OUT Disabled - Normal operation.JP3 Select IN Test program.

operating program OUT Normal operation.JP4 ICE test enable IN Ready for ICE test (Note)

OUT Normal operation

Note: 1. In test mode JP4 is connected to In-Circuit-Emulator for R&D only.


5-8 92050003-04

5.8.6 BMCT Hard Wired - None

5.8.7 BMCT DIP Switch SW1 Settings



5.8.8 BMCT Location of Jumpers and DIP Switches

sw1

1

5.8.9 -DSP

5.8.10 -DSP Jumper Settings

JMP No. Function Setting DescriptionJP2 Automatic control of

test equipmentIN Fluke test

OUT Normal operationJP3 Select Program 1-2 Test PROM by Fluke only

Test/ Boot 2-3 Boot - Normal operation (PROG)JP5 Select trigger for 1-2 CLOCK enabled - normal

Watchdog 2-3 CPU PORT enabled

5.8.11 -DSP Hard Wired - None


92050003-04 5-9

5.8.12 -DSP DIP Switch (U102) Settings



5.8.13 -DSP Location of Jumpers and DIP Switches

JP2

JP5

JP3

U102

U

D

1

1


5-10 92050003-04

5.9 RDSW

5.9.1 RDSW Jumper Settings

JMP No. Function Setting DescriptionJP1 Select CPU control IN CPU control- Normal operation

Bypass - (TR0connected to BR0)

OUT CPU control disabled

JP2 Select clock test OUT Normal operation (note 1)External test 2-3 Test by FLUKE only (note 2)

JP3 Select CPU control IN CPU disabledOUT CPU enabled - Normal operation

Notes: 1. For normal operation, no jumper is required between 1 & 2. If the short is removed, the jumper is required.

2. For Fluke test, remove short between terminals 1 & 2 on card.

5.9.2 RDSW Hard Wired - None

5.9.3 RDSW Location of Jumpers and DIP Switches

JP1

JP2

JP3

1


92050003-04 5-11

5.10 QDLI

5.10.1 QDLI Jumper Settings

JMP No. Function Setting DescriptionJP1 Select reset control 1-2 Normal operation

CPU or Watchdog 2-3 Watchdog enabledJP2 Select operating

program1-2 Test program

2-3 Normal operationJP3, JP4 OUT Not in use.

75Ω 100Ω 120Ω (Note 1)

JP5 Select DLI0 IN OUT OUTJP6 impedance OUT IN OUTJP7 OUT OUT INJP8 Select DLI1 IN OUT OUTJP9 impedance OUT IN OUTJP10 OUT OUT INJP11 Select DLI2 IN OUT OUTJP12 impedance OUT IN OUTJP13 OUT OUT INJP14 Select DLI3 IN OUT OUTJP15 impedance OUT IN OUTJP16 OUT OUT IN

JP18toJP20 OUT Not in useJP21 Control connection 1-2, 3-4 for 75Ω (Note 2)

of DLI0 output shieldto CGND

OUT for 100 or 120 Ω (Note 3)

JP22 Control connection 1-2, 3-4 for 75Ω (Note 2)of DLI1 output shieldto CGND







5-12 92050003-04

Notes:1. Only one jumper should be used.2. For 75Ω operation the outgoing bitstream shield is connected to CGND.3. For 100/120Ω operation the outgoing bitstream shield is not connected to CGND.

5.10.2 QDLI Hard Wired - None

5.10.3 QDLI DIP Switch (U43) Settings



5.10.4 QDLI Location of Jumpers and DIP Switches

JP5JP6JP7

JP8JP9JP10

JP11JP12JP13

JP14JP15JP16

JP21

JP22

JP23

JP1

JP2

U43

JP24

1

1

1

124

2

2

2

3

3

3

3

4

4

4

1

1

JP18 JP19JP20

JP3

JP4


92050003-04 5-13

5.10.5 QDLI Rev. E Jumper Settings

JMP No. Function Setting DescriptionJP1 Select reset control 1-2 Normal operation

CPU or Watchdog 2-3 Watchdog enabledJP2 Select operating

program1-2 Test program

2-3 Normal operationJP3 - 6 Select operation mode

DLI0 - 31-22-3

for E1(2Mhz)for T1(1.5Mhz)

75Ω 100Ω 120ΩJP9 Select DLI0 IN OUT OUT (Note 1)JP10 impedance OUT IN OUTJP11 OUT OUT INJP12 Select DLI1 IN OUT OUT (Note 1)JP13 impedance OUT IN OUTJP14 OUT OUT INJP15 Select DLI2 IN OUT OUT (Note 1)JP16 impedance OUT IN OUTJP17 OUT OUT INJP18 Select DLI3 IN OUT OUT (Note 1)JP19 impedance OUT IN OUTJP20 OUT OUT IN

JP22,23 noneJP24 OUT Not in useJP25 Control connection 1-2, 3-4 for 75Ω (Note 2)

of DLI0 output shieldto CGND






JP28 Control connection ofDLI3 output shield toCGND

1-2, 3-4 for 75Ω (Note 2)

Notes:1. Only one jumper should be used.2. For 75Ω operation the outgoing bitstream shield is connected to CGND.3. For 100/120Ω operation the outgoing bitstream shield is not connected to CGND.


5-14 92050003-04

5.10.6 QDLI REV. E Hard Wired

JP. No. Function Setting Description21 2 - 3

1 - 2

5.10.7 QDLI REV.-E DIP Switch (U75) Settings

Pole No. Function Setting Description 8- 1 T. B. D. OFF (Open) Not in use


5.10.8 QDLI REV.-E Location of Jumpers and DIP Switches

JP9JP10JP11

JP12JP13JP14

JP15JP16JP17

JP18JP19JP20

JP25

JP26

JP27

JP1

JP2

U75

JP28

1

1

1

124

2

2

2

3

3

3

3

4

4

4

1

1

JP21JP22,23,24

JP7JP8

JP3

JP4

JP5

JP6

J7

J8

23

1

23

1

23

1

23

1


92050003-04 5-15

5.11 CKSL

5.11.1 CKSL Jumper Settings

JMP No. Function Setting DescriptionJP2 Internal clock to IN Connected - Normal operation

receive timing ckt OUT DisconnectedJP3 External clock 1-2 75Ω

impedance match 2-3 120Ω(Note ) OUT High impedance

Note: 1. To be set according to customer's requirement.

5.11.2 CKSL Hard Wired

JMP No. Function Setting DescriptionJP1 Automatic control 1-2 Normal operation

of test equipment 2-3 Fluke test

5.11.3 CKSL Location of Jumpers

1 1


5-16 92050003-04

5.12 BPIF/0


JMP No. Function Setting DescriptionJP1 to JP12 Input bitstream 1-2 (Note 2)

shield connection OUT (Note 3) to CGND 2-3 option for 75Ω only (Note 4)

JP13 Bal. Ext. Clk. shield 1-2 (Note 5)conn. to CGND 2-3 (Note 6)

JP14 Balanced Ext. Clock IN (Note 5)(Note 1) shield connection to

CGNDOUT (Note 6)

Notes: 1. JP1 to JP4 correspond to BR1 to BR4JP5 to JP12 correspond to TR1 to TR8JP13 is used for External Clock

2. Input bitstream shield is connected to CGND (option for 75Ω only). 3. For 100/120Ω operation input bitstream shield is not connected to CGND 4. Input bitstream shield is connected to CGND through a 0.1 µF capacitor . 5. Shield of balanced input: External Clock is connected to CGND

(setting preferred also for 75Ω to block antenna signals from the "S" pin). 6. Shield of balanced input: External Clock is not connected to CGND

(only for 100Ω or 120Ω);


5.12.3 BPIF /0 Location of Jumpers


92050003-04 5-17

5.13 SIGN & SIGN/L ** In this document, SIGN & SIGN/L ( Option -021 ) named as SIGN .

5.13.1 SIGN Jumper Settings

JMP No. Function Setting DescriptionJP1 Select signaling

Fluke test / CPUIN Disable boot EPROM

(Fluke test)OUT CPU - Normal operation

JP2 Select firmware Test /Boot

IN Fluke test

OUT Normal operationJP3 Select Watchdog 1-2 Disabled - Normal operation

enable 2-3 Watchdog enabledJP28 Reset to PAL's timing IN Normal operation

OUT Fluke test

5.13.2 SIGN Hard Wired - None

5.13.3 SIGN Location of Jumpers

JP1

1


5-18 92050003-04

5.14 TSDF

5.14.1 TSDF Jumper Settings - None

5.14.2 TSDF Hard Wired

JMP No. Function Setting DescriptionJP1 Select Internal / External Short Internal - Normal operation

ROM for DSP OUT External Memory (N.A)

5.14.3 TSDF Location of Jumpers

JP1


92050003-04 5-19

5.15 BPIF/2


JMP No. Function Setting DescriptionJP1 to JP12 Input bitstream shield IN for 100Ω or 120Ω (Note 1)

connection to CGND OUT " (Note 2)JP13 Balanced Ext. Clock shield IN " (Note 3)

connection to CGND OUT " (Note 4)

Notes: 1. Input bitstream shield is connected to CGND. 2. Input bitstream shield is not connected to CGND. 3. Shield balanced input External Clock is connected to CGND. 4. Shield of balanced input External Clock is not connected to CGND.


5.15.3 BPIF /2 Location of Jumpers

JP1J

P2J

P3J

P4J

P5J

P6J

P7J

P8J

JP9J

JP10J

JP11J

JP12J

J3

J4

JP13J


5-20 92050003-04

5.16 BMCR

5.16.1 BMCR Jumper Settings

JMP No. Function Setting DescriptionJP1 Watchdog 1-2 Disable - Normal operation

circuit control 2-3 Enable - Future operationJP2 WRITE enable for IN WRITE enabled

control 1 OUT WRITE disabled - Normal operation.JP3 Operating program IN Test PROM

select OUT Normal operationJP4 InCircuit Emulation IN Ready for ICE test (Note )

test enable OUT Normal operation

Note: JP4 is connected for ICE test mode for R&D only.

5.16.2 BMCR Hard Wired - None

5.16.3 BMCR DIP Switch (SW1) Settings



5.16.4 BMCR Location of Jumpers and DIP Switches

1


92050003-04 5-21

5.17 BPIF/3


JMP No. Function Setting DescriptionJP1 to JP8 Select input IN for 100Ω or 120Ω (Note 2)

bitstream shield OUT for 100Ω or 120Ω (Note 3)

Notes: 1. Shield of input bitstream connected to CGND.2. Shield of input bitstream not connected to CGND.


5.17.3 BPIF /3 Location of Jumpers and DIP Switches

J3

J4

JP1JP2JP3JP4JP5JP6JP7JP8


5-22 92050003-04

5.18 GDSP

5.18.1 GDSP Jumper Settings

JMP No. Function Setting DescriptionJP2 Automatic control of

test equipmentIN Fluke test

OUT Normal operationJP3 Select Program 1-2 Test PROM by Fluke only

Test/ Boot 2-3 Boot - Normal operation (PROG)JP5 Select trigger for 1-2 CLOCK enabled - normal

Watchdog 2-3 CPU PORT enabled

5.18.2 GDSP Hard Wired - None

5.18.3 GDSP DIP Switch (U102) Settings



5.18.4 GDSP Location of Jumpers and DIP Switches


92050003-04 5-23

5.19 DSIR /L

5.19.1 DSIR /L Jumper Settings

5.19.2 DSIR /L Hard Wired - None

JMP No. Function Setting DescriptionJP1 Download via RCPU OUT (none) Normal operation

Download via connectorJ3

IN R & D use

5.19.3 DSIR /L Location of Jumpers

JP1


5-24 92050003-04

5.20 CPU /L

5.20.1 CPU /L Jumper Settings

JMP No. Function Setting DescriptionJP1 Watchdog select 1-2 Disabled- Normal operation

2-3 EnabledJP2 CPU BIT IN Disabled

OUT Enabled - Normal operationJP3 TRIST function IN Enabled

not in use OUT Disabled - Normal operationJP4 Select operating IN 25 MHz

frequency OUT 33 MHz - Normal operationJP5 Software select IN Test PROM

Test/ Boot OUT Boot - Normal operationJP6 Ram write protect IN Enabled

OUT Disabled

5.20.2 CPU /L DIP Switch (U61) Settings

Pole No. Function Setting Description1 Boot Reset for

DebuggingOFF (Open) Not in use

ON (Close) Disable Reset at boot toBMCT DSIT TDSP

2 - 8 OFF (Open) Not in useON (Close) Not in use

5.20.3 CPU /L Location of Jumpers and DIP Switches

JP5 JP6 JP1

JP2 JP3 JP4

U61

1


92050003-04 5-25

5.21 OMCP /L

5.21.1 OMCP /L Jumper Settings

JMP No. Function Setting DescriptionJP1 Select Watchdog 1-2 Disabled - Normal operation

2-3 EnabledJP2 Select program IN Test program (U92-Test Prom)

OUT Normal operation (Boot)

5.21.2 OMCP /L Hard Wired

JP3 LAN Test IN EnabledOUT-None Disabled

JP4 Select frequency Short 25 MHz - Normal operationNone 33 MHz

JP5 Tristate on Reset IN Enabled(used with ICE ) OUT-None Disabled

JP6 CPU self test bit Short Enabled - Normal operationNone Disabled

5.21.3 OMCP /L DIP Switch (S2) Settings

Pole No. Function Setting Description1 - 7 OFF (Open) Not in use

ON (Close) Not in use8 Monitor display OFF (Open) Monitor ON - ECI

ON (Close) Monitor Off -

5.21.4 OMCP /L Location of Jumpers and DIP Switches

J P 1 JP2 JP4 JP5 JP6

J P 3

S 2

1


5-26 92050003-04

5.22 BMCT /L

5.22.1 BMCT /L Jumper Settings

JMP No. Function Setting DescriptionJP1 ICE test enable IN Ready for ICE test (Note)

OUT Normal operationJP2 WRITE enable for IN WRITE enabled

control OUT Disabled - Normal operation.JP3 Select IN Test program.

operating program OUT Normal operation.(Boot -U56)JP5 Watchdog 1-2 Disabled - Normal operation.

circuit control 2-3 Enabled - Future operation.

Note: 1. In test mode JP4 is connected to In-Circuit-Emulator for R&D only.

5.22.2 BMCT /L Hard Wired - None


92050003-04 5-27

5.22.3 BMCT /L DIP Switch (SW2) Settings

Pole No. Function Setting Description1 Config. Download (0) ON (Close) Default configuration

(1) OFF (Open) TCPU - configuration2 (0) ON (Close) T.B.D - Debugging

(1) OFF (Open) “3 (0) ON (Close) “

(1) OFF(Open) “4 (0) ON (Close) “

(1) OFF (Open) “

5.22.4 BMCT /L Location of Jumpers and DIP Switches

J1

J2

SW2

JP1 JP2 JP3

JP5

1


5-28 92050003-04

5.23 TSDF /L

5.23.1 TSDF /L On Circuit Wired (Hard Wired)

JMP No. Function Setting DescriptionJP1 MF~

AISBRMSDISLDFA~

0-1(None) Enable - R&D

OUT (None) Normal operationJP2 2-3 (None) Internal - Normal operation

1-2 (None) External memory (N.A.)JP3 MF~

AISBRMSDISLDFA~

2-3 (None) Enable - R&D

OUT (None) Normal operation

5.23.2 TSDF /L Location of Jumpers

J1

J2

JP1

JP2

JP3

321


92050003-04 5-29

5.24 BMCR /L

5.24.1 BMCR /L Jumper Settings

JMP No. Function Setting DescriptionJP1 Incircuit Emulation IN Ready for ICE test (Note )

test enable OUT Normal operationJP2 WRITE enable for IN WRITE Enabled

control 1 OUT WRITE Disabled - Normal op.JP3 Operating program IN Test PROM

select OUT Normal operation (Boot- U62)JP4 Watchdog 1-2 Disable - Normal operation

circuit control 2-3 Enable - Future operation

Note: JP1 is connected for ICE test mode for R&D only.

5.24.2 BMCR /L Hard Wired - None

5.24.3 BMCR /L DIP Switch (SW2) Settings

Pole No. Function Setting Description1 Config. Download (0) ON (Close) Default configuration

(1) OFF (Open) RCPU - configuration2 (0) ON (Close) T.B.D - Debugging



(1) OFF (Open) “

5.24.4 BMCR /L Location of Jumpers and DIP Switches

J2

J1

SW2

JP1 JP2 JP3

JP4


5-30 92050003-04

5.25 DSIT /L

5.25.1 DSIT /L Jumper Settings

JMP No. Function Setting DescriptionJP1 Download via RCPU OUT(none) Normal operation

Download via conn. J5 IN R & D useJP2 OUT(none) If U19 - FLASH

IN If U19 - PROM

5.25.2 DSIT /L Hard Wired - None

5.25.3 DSIT /L Location of Jumpers

JP1

JP2

J1

J2


92050003-04 5-31

5.26 LDCH Rev A

5.26.1 LDCH Jumper Settings

JMP No. Function Setting DescriptionJP1 S/W Flash selection IN Normal Operation

OUT For JTAG TestingJP2 U15 U81 Connection 1 - 2 All PALs are routing .

2 - 3 U81 works aloneJP3 DSPs Connection OUT Normal Operation

for J tag tests 1 - 2 All DSPs connecting2 - 3 U9 works alone

JP4- Double PS 3.3v output enable IN (1-2 , 3-4) 3.3v PS connectedOUT No 3.3v - Test mode

5.26.2 LDCH Hard Wired - None

5.26.3 LDCH DIP Switch (S2) Settings

Pole No. Function Setting Description1 - 4 JTAG debugging ON Default mode

OFF

5.26.4 LDCH Location of Jumpers

JP1

JP2

J1

J2

JP3

JP4

S2

1

1

1

1

1

2


5-32 92050003-04

5.27 LDCH Rev B

5.27.1 LDCH Jumper Settings

JMP No. Function Setting DescriptionJP1 S/W Flash selection OUT Normal Operation

IN For JTAG TestingJP4- Double PS 3.3v output enable IN (1-2 , 3-4) 3.3v PS connected

OUT No 3.3v - Test mode

5.27.2 LDCH Hard Wired - None

5.27.3 LDCH DIP Switch (S2) Settings- None

5.27.4 LDCH Location of Jumpers

JP1 J1

J2

JP4

11 2

3 4


92050003-04 5-33

5.28 CCOM

5.28.1 CCOM Cards Layout

1 2 3 4 5 6 7

COCP CRIO CRMX CMRX CRMX CRMX CRMX

5.28.2 CCOM List of Card Jumper Settings

Card Dwg. No. Jumper Settings

CRMX 238009-7461 None CRIO 238009-7462 Given COCP 238009-7464 Given


5-34 92050003-04

5.29 CRIO Jumper Settings

JMP No. Function Setting DescriptionJP1,JP2,JP3 3 parallel controlling

CRIO & COCPIN Normal operation

5Vdc power supply OUT Fluke testJP4 Controlling -12Vdc

power supplyIN Normal operation

to COCP OUT Fluke testJP5 Controlling +12Vdc

power supplyIN Normal operation

to COCP OUT Fluke test

5.29.1 CRIO Hard Wired - None

5.29.2 CRIO Location of Jumpers

JP1JP2JP3

JP4

JP5


92050003-04 5-35

5.30 COCP

5.30.1 COCP Jumper Settings

JMP No. Function Setting DescriptionJP1 Select Program IN Test - not in use

OUT Boot - Normal operationJP2 Select Watchdog 1-2 Disabled - Normal operation

2-3 Enabled

5.30.2 COCP Hard Wired - None

5.30.3 COCP DIP Switch (SW2) Settings



5.30.4 COCP Location of Jumpers and DIP Switches


5-36 92050003-04

5.31 LCOM

5.31.1 LCOM Cards Layout

1 2 3 4 5 6 7 8 9 10 11 12 13 14

LODP LRMX LMRX LRMX LRMX LRMX LRMX

5.31.2 LCOM List of Card Jumper Settings

Cards Dwg. No. Jumper settings

LCMB 238009-7450-011 GivenLRMU 238009-7451-010 GivenLRMB 238009-7451-020 GivenLODP 238009-7452-011 None

5.32 SCOM

5.32.1 SCOM Cards Layout

1 2 3 4 5 6 7 8 9 10 11 12 13 14

COCP CRIO LRMX LMRX LRMX LRMX LRMX LRMX

Note: All relevant cards’ jumper settings are as described above (CCOM, LCOM)


92050003-04 5-37

5.33 LCMB

5.33.1 LCMB Jumper Settings - None

5.33.2 LCMB Hard Wired - None

5.33.3 LCMB DIP Switches (SW2 to SW6) Settings

Pole No. Function Setting Description1 - 8 T. B. D. OFF (Open) DTX 360A/B

ON (Close) DTX-360 Compact


5-38 92050003-04

5.34 LRMX

5.34.1 LRMX Jumper Settings (for 75 Ω or 100Ω)

JMP No. Function Setting DescriptionJP1 to JP16 Select card 1-2 for 75Ω (Note 1)

impedance 2-3 for 100Ω (Note 1)JP17,19,21,JP23,25,27,

Select input bit streamshield

IN option

JP29,31 connection to CGND OUTJP18,20,22,JP24,26,28,

Select output bit streamshield

IN for 75Ω (Note 2)

JP30,32 connection to CGND OUT for 100Ω (Note 2)

Notes: 1. The following table lists the functional relationships between the jumper settingsand the bitstream lines TX (input) or RX (output). The bitstream lines arebetween the ISC and the UP or DOWN DTX-360 terminal.

Terminal UP Terminal DOWNJMP TX JMP RX JMP TX JMP RX

JMP1 TX0 JMP2 RX0 JMP3 TX4 JMP4 RX4JMP5 TX1 JMP6 RX1 JMP7 TX5 JMP8 RX5JMP9 TX0 JMP10 RX0 JMP3 TX4 JMP4 RX4JMP13 TX1 JMP14 RX1 JMP15 TX5 JMP16 RX5

Notes: 2. IN : Shield of outgoing bitstreams connected to CGND (for 75Ω); OUT: Shield of outgoing bitstreams not connected to CGND (for 100Ω).

5.34.2 LRMX Hard Wired - None


92050003-04 5-39

5.35 LRMX

5.35.1 LRMX Jumper Settings - None

5.35.2 LRMX Hard Wired - for 120 Ω

JMP No. Function Setting DescriptionJP1 to JP16 Select card 2-3 for 120Ω only (Notes 1, 2)

impedance

Notes: 1. The following table lists the functional relationships between the jumper settingsand the bitstream lines TX (input) or RX (output). The bitstream lines are betweenthe ISC and the UP or DOWN DTX-360 terminal.

Terminal UP Terminal DOWNJMP TX JMP RX JMP TX JMP RX

JMP1 TX0 JMP2 RX0 JMP3 TX4 JMP4 RX4JMP5 TX1 JMP6 RX1 JMP7 TX5 JMP8 RX5JMP9 TX0 JMP10 RX0 JMP3 TX4 JMP4 RX4JMP13 TX1 JMP14 RX1 JMP15 TX5 JMP16 RX5

Notes: 2. For 120Ω operation, jumpers are required to short pins 2 with 5 and 4 with 6 of transformers T17 to T32.


5-40 92050003-04

5.36 Power Supply

5.36.1 Power Supply Front Panel

INDU INVP INVP PSU PSU PSU PSU PSU PSU

1 2∗A 6 5 4 3 2 12 3∗C 6 5 4 3 2 13 4∗C 5 4 3 2

5.36.2 Power Supply Shelf

Item Dwg. No. Jumper Settings

PSU-40 138009-7570-011 None PSU 138009-7470-011 None INVP 138009-7471-011 None INDU 138002-3125 None MBPU 238009-7475-011 Given


92050003-04 5-41

5.37 MBPU

5.37.1 MBPU Jumper Settings

JMP No. Function Setting DescriptionJ22 Power Supply C.C.1 IN Config #3

configuration control OUT Config #1, 2J23 Power Supply C.C.2 IN Config #1



configuration control OUT Config #2, 3J26 Power Supply C.C.5 IN Config #2, 3

configuration control OUT Config #1

5.37.2 MBPU Hard Wired - None

5.37.3 MBPU DIP Switch Settings

Switch No. Function Setting DescriptionSW1 Power Supply UP Config #2

configuration control DOWN Config #1, 3SW2 Power Supply UP Config #2

configuration control DOWN CONFIG #1, 3


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5.38 Summary of Jumper and Switch Settings

5.38.1 DTX-360 Cards

CARD Part No. JUMPER DIP SWITCH POLEJmp.No. Setting √ Designat. 1 2 3 4 5 6 7 8 √

-CPU 7414 1 1-2 U72 0 0 0 0 0 0 0 02 OUT

-DSP 7420 2 OUT U102 0 0 0 0 0 0 0 03 2-35 1-2

AUXC 7411 1 1-22 1-2

BMCR 7440 1 1-2 Sw1 to 8 0 0 0 0 0 0 0 02 to 4 OUT

BMCT 7418 1 1-2 Sw1 to 8 0 0 0 0 0 0 0 02 to 4 OUT

CKSL 7423 2 IN3 (Note )

SIGN* 7430 1, 2 OUT3 1-228 IN

RDSW 7421 1 IN2, 3 OUT

OMCP 7415 1 OUT ECI - U51 0 0 0 0 0 0 0 02 2-3 Alcatel-U51 0 0 0 0 0 0 0 1

BPIF / 0 7426 1 to 14 (Note )BPIF / 1 7416 5 to 12 (Note )DSIR /L 7513 None-CPU /L 7514 1 1-2 U61 0 0 0 0 0 0 0 0

2 to 5 OUT6 OUT

Jmp. No. Setting √ Designat. 1 2 3 4 5 6 7 8 √

DTX-360 Cards (continued)


OMCP/L 7515 1 2 - 3 ECI - S2 0 0 0 0 0 0 0 02 OUT Alcatel - S2 0 0 0 0 0 0 0 1

BMCT/L 7518 1 to 3 OUT Sw2 1 1 1 1 ( OFF )5 1-2

BMCR/L 7540 1 to 3 OUT Sw2 1 1 1 1 ( OFF )4 1-2

DSIT/L 7543 None


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TSDF 7435 NoneGDSP 7467 2 OUT U102 0 0 0 0 0 0 0 0

3 2-35 1-2

TSDF/L 7535 NoneLDCH 7568 1, 4 IN S2 0 0 0 0Rev A 2 1-2

3 OUTLDCH 7568 1 OUTRev B 4 IN

* In this document SIGN & SIGN/L (Option -021) named as SIGN.

DTX 360 - Jumper and Switch Settings


QDLI 7422 1 1-2 U43 0 0 0 0 0 0 0 02 2-3

3, 4 OUT5 to 16 (Note)18 to 20 OUT21 to 24 (Note)

QDLI 7422 1 1-2 U75 0 0 0 0 0 0 0 0Rev. E 2 2-3

3 to 6 1-2 E1 = 2M2-3 T1=1.5M

9 to 20 (Note )22, 23 NONE

24 OUT25 to 28 (Note )

Note:: See Section 5.1.1 Trunk & Bearer Impedance Configuration


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5.38.2 Trunk & Bearer Impedance Configuration

CARD Part No. Trunk Config. Bearer Config.No. 75Ω 120Ω 100Ω 75Ω 120Ω 100Ω √

QDLI 7422 5,8,11,14 IN OUT OUT IN OUT OUT6,9,12,15 OUT OUT IN OUT OUT IN7,10,13,16 OUT IN OUT OUT IN OUT

21-24 1-2,3-4

OUT OUT 1-2,3-4

OUT OUT

QDLI 7422 9,12,15,18 IN OUT OUT IN OUT OUTRev. E 10,13,16,19 OUT OUT IN OUT OUT IN

11,14,17,20 OUT IN OUT OUT IN OUT25-28 1-2,

3-4OUT OUT 1-2,

3-4OUT OUT

CKSL 7423 3 (Ext. clk) 1-2 2-3 2-3 - - -BPIF/1 7416 5 to12 1-2 OUT OUT - - -BPIF/0 7426 1 to 4 - - - 1-2 OUT OUT

5 to12 1-2 OUT OUT - - -13 (Ext.clk) 1-2 2-3 2-3 - - -14 (Ext.clk) IN OUT OUT - - -

BPIF /3 7446 1 to 8 - IN IN - - -BPIF /2 7436 1 to 8 - IN IN - - -

9 to12 - - - - IN IN13 - IN IN - - -

Note: 75Ω UNBALANCED / 120Ω BALANCED LINE OPERATION


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5.39 CCOM CARDS

CARD PART No. JUMPER DIP SWITCH POLEJmp No. Settings √ Designation 1 2 3 4 5 6 7 8 √

CRIO 7462 1 to5 IN -COCP 7464 1 OUT SW2 0 0 0 0 0 0 0 0

2 1-2


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5.40 LCOM CARDS

CARD Part No. JUMPER DIP SWITCH POLEJMP No. Settings √ Designation 1 2 3 4 5 6 7 8 √

LCMB 7450 - SW 2 to 6 0 0 0 0 0 0 0 0LRMX 7451 1 to 16 (notes 1, 2) -

17,19,21,23,25,27,29,31

OUT (note 2)

18,20,22,24,26,28,30,32

(notes 1, 2)

Notes: 1. See Section 5.3.1 Trunk & Bearer Impedance Configuration.2. For 120Ω operation ignore the LRMX jumper settings and verify that the LRMX

card version is 7451-020.

5.40.1 Trunk & Bearer Impedance Configuration

CARD PART JUMPER Trunk Configuration Bearer ConfigurationNo. No. 75Ω 120Ω 100Ω 75Ω 120Ω 100Ω √

LRMX 7451-010 1 to 16 1-2 note 2-3 1-2 note 2 2-318,20,22,2426,28,30,32

IN note OUT IN note 2 OUT

Note: 75Ω UNBALANCED /120Ω BALANCED LINE OPERATION


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5.41 Power Supply Shelf Cards

CARD PART JUMPER Configuration No.No. No. #1 #2 #3 √

MBPU 7475 J22 OUT OUT INJ23 IN OUT OUTJ24 OUT IN OUTJ25 IN OUT OUTJ26 OUT IN IN

CARD PART SWITCH Configuration No.No. No. #1 #2 #3 √

MBPU 7475 SW1 DOWN UP DOWNSW2 DOWN UP DOWN

dtx-360 maintenance manual - salvex maintenance.pdf · 92050003-03 i dtx-360 maintenance manual...

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