dual boost high performances power factor correction (pfc ... xxi/tesi parillo... · dual boost...

UNIVERSITÀ DEGLI STUDI DI CASSINO

SCUOLA DI DOTTORATO IN INGEGNERIA

DIPARTIMENTO DI AUTOMAZIONE, ELETTROMAGNETISMO,

INGEGNERIA DELL’INFORMAZIONE E MATEMATICA INDUSTRIALE

Dual Boost High Performances Power Factor Correction (PFC) Systems

Fernando Parillo

In Partial Fulfillment of the Requirements for the Degree of

PHILOSOPHIAE DOCTOR in Electrical and Information Engineering

November 2008

TUTOR COORDINATOR Prof. Ciro Attaianese Prof. Giovanni Busatto

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UNIVERSITÀ DEGLI STUDI DI CASSINO SCUOLA DI DOTTORATO IN INGEGNERIA

Date: November 2008

Author: Fernando Parillo

Title: Dual Boost High Performances Power Factor

Correction (PFC) Systems Department: DIPARTIMENTO DI AUTOMAZIONE,

ELETTROMAGNETISMO, INGEGNERIA DELL’INFORMAZIONE E MATEMATICA INDUSTRIALE

Degree: PHILOSOPHIAE DOCTOR Permission is herewith granted to university to circulate and to have copied for non-commercial purposes, at its discretion, the above title upon the request of individuals or institutions.

_____________________ Signature of Author

THE AUTHOR RESERVES OTHER PUBLICATION RIGHTS, AND NEITHER THE THESIS NOR EXTENSIVE EXTRACTS FROM IT MAY BE PRINTED OR OTHERWISE REPRODUCED WITHOUT THE AUTHOR’S WRITTEN PERMISSION.

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Acknowledgements The research world for me is not a new experience, but the same I have many people to thank... First of all I would like to deeply thank Prof. Ciro Attaianese, my mentor, for all he has done for me since 1996. I am thankful to Vito Nardi for his many suggestions and constant help during these years. He had a lot of patience versus me in particular mode at begin of this experience concerning the programming techniques of FPGA devices. I prefer VHDL language instead he prefers the graphical mode of programming but at the end a compromise has been found, almost I hope !!! I give my special thanks to Giuseppe Tomasso , he is the first person that I have known since 1996 after the Prof. Ciro Attaianese, when he was a PhD student. He has involved me in several scientific works. The first scientific experience that I remember with him is concerning the implementation of a H∞ controller on a DC motor on the far 1998. He is for me a great friend. He has been a mentor not only in the research world but also in the life. He has resolved the greatest my health problem, for this, particular thanks also his brother in law Marcello De Rosa. At last, but not least important, I thank a lot my great friend Damiano Capraro, my old age support, for his great contribute and experience in Power Converters design. I known him as a student since 18 November 1997, when we designed the first power converter of our laboratory under the wise supervision of Prof. Ciro Attaianese. Cassino, November 2008

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Acknowledgements This work is dedicated to my father Giovanni. He suggested me on 29 June 2005, appearing in a dream, to participate to a doctoral research course. My father died on 15 March 1989, when I was yet a student. On the day of his death I was at home to study the electrical circuits course. The test was fixed on 31 March 1989. Several times he has come in my dreams to remember me that the day of his death I was not near him, as the remaining of my family, because the extreme importance given to my studies. In these dreams I never be able to tell my father the “true” motivation of My absence at “Vecchio Pellegrini” hospital in Naples, in that day. The last time that I saw my father, yet in life, was the Sunday 12 March 1989. With this experience my father seems to have found peace, in fact I have not received more reproaches concerning to my absence made on the death day. I hope, on the remaining days of my life, to continue contributing to scientific research in honour to my father. Cassino, 28 November 2008

Dedicated to my father Giovanni

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SUMMARY

This work will discuss the design and the implementation of high performance control and diagnostic algorithms for dual boost PFC power converters. Moreover two paralleled PFC converters, based on Active Filtering principle are presented. The first proposed algorithm is based on a current hysteresis principle, and has been implemented on a FPGA device, while the second one is based on a predictive control strategy and implemented on a DSP based microcontroller. At last an example of a residential elevator plant is presented in order to show the whole efficiency, both in terms of algorithms performances and in terms of reduction of power device losses, of the proposed converters topology to respect at the same solution but using the classical single PFC topology. Beside in this work is shown also that the use of dual boost converter based on Power Factor Correction (PFC) are compliant to the recent international standards, in terms of harmonic pollution, such as IEC-61000-3-2 and IEEE-519. ORGANIZATION OF THE BOOK This book is composed by the following chapters:

Chapter 1 − A survey of power converters is presented in function of their topology. The common power electronic devices features are shown. It is also shown the basic concepts to design efficient power converters.

Chapter 2 − Basic concepts of a Power Factor Converter (PFC) are shown. The first part of the chapter is dedicated to readers without expertise in the field of power factor correction systems for the correct comprehension of the following chapters. Moreover a detailed mathematical model will be built up in order to show the different operating modes of a boost converter.

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Chapter 3 − Introduction to active filtering approach and comparison with the passive filtering techniques, widely used in the past, will be done, in order to show the advantage of the active filtering approach respect to classical solutions. Several topology of active filters are shown.

Chapter 4 − Analytical formulation of the proposed algorithms will be executed and a comparison between two solutions will be made.

Chapter 5 − Simulation results of the proposed dual boost PFC architectures are shown and a comparison to classical PFC topology will be discussed.

Chapter 6 − Experimental results based on the simulation results shown in the chapter 5 will be depicted, in this chapter also the thermal efficiency investigation to respect to classical PFC will be done.

Chapter 7 − High performance Supercapacitor Recovery System (SRS) including Power Factor Correction for residential elevator plant is presented.

Chapter 8 − Conclusions and future developments concerning the control strategies proposed in the previous chapters will be discussed, in particular, with reference to control algorithms presented in the chapters 4, 6 and 7.

Appendix A − Used voltage and current Hall effect based transducers main features and mounting considerations are depicted.

Appendix B − Main features of the control unit devices are depicted. The mentioned devices are: ALTERA® Cyclone I EP1C6Q240C6 FPGA and TI® TMS320F2812 DSP.

Appendix C(*) − A brief description of the IEEE 754 floating point standard is depicted and a brief description of the some elementary math functions is described in order to show their implementation on a FPGA device (Work in progress).

(*) The topic “Sfloat_24 non standard floating point numbers FPGA math functions implementation” is not reported in the chapter 8, but simply in an appendix because it is not pertinent to the Power Electronics.

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Contents

Acknowledgements

V

Summary

VII

1 Overview of power electronics 1 1.1 Introduction …………………………………….. 1 1.2 Power system classification ……………………. 2 1.3 Power systems − Operating modes ...………….... 3 1.4 Energy conversions topologies ………..………... 4 1.5 Recent and potentials advancements …………… 5 1.6 Desired characteristics in power electronic device

− efficiency analysis …………………................ 7

2 Overview of Power Factor Correction systems 11 2.1 Introduction …………………………………….. 11 2.2 Recent developments …………………………... 17 2.3 Boost Converter modelling …………………...... 18 2.4 Boost Converter controlling …………...……….. 21 3 Overview of Active Filters for improving power quality 23 3.1 Introduction …………………………………….. 23 3.2 Classification of active filters ………………….. 26 3.2.1 Classification by objective ……………... 26 3.2.2 Classification from system configurations 27

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4 Dual boost high performances Power Factor

Correction (PFC) − Mathematical formulation − 33

4.1 Introduction …………………………………….. 33 4.2 Control Algorithms − Basic concepts …………... 34 4.3 Dual PFC Modelling …………………………… 35 4.4 Dual PFC Controlling ………………………….. 37 4.4.1 Principle of the control strategy ……….. 37 4.4.2 Current hysteresis control algorithm …... 38 4.4.3 Predictive Control of Parallel Power

Factor Correction ………………………. 39

4.5 Dual Boost PFC efficiency analysis …………… 42 5 Dual boost high performances Power Factor

Correction (PFC) − Simulation results − 43

5.1 Introduction ………………………………..…… 43 5.2 Dual Boost PFC Simulation ………………..…... 44 5.2.1 Current hysteresis control scheme ….….. 44 5.2.2 Predictive control scheme ……………… 49 5.3 Considerations ……………………..…………… 53 6 Dual boost high performances Power Factor

Correction (PFC) − Experimental results − 55

6.1 Introduction …………………………………….. 55 6.2 Experimental layout description ……………….. 55 6.3 Dual Boost PFC ………………………………... 58 6.3.1 Current hysteresis control scheme ……... 58 6.3.2 Predictive control scheme …………….... 66

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7 High Performances Supercapacitor Recovery System

including Power Factor Correction (PFC) for elevators

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7.1 Introduction …………………………………….. 73 7.2 Conversion system description ………………… 74 7.3 Supercapacitor recovery system ………………... 75 7.4 PFC Buck-boost control algorithm …………….. 76 7.5 PFC Modulation algorithm …………………….. 78 7.6 Simulation and experimental results …………… 79 8 Discussions 85 8.1 Experimental results …………………………..... 85 8.2 Future developments …………………………… 87 8.3 Conclusions ……………………………………... 92 A Hall Effect transducers: Mean features and basic

mounting considerations 93

A.1 Introduction …………………………………….. 93 A.2 LA 25 NP Hall effect current transducers ……… 93 A.3 LV 25 P Hall effect voltage transducers ……….. 94 B High performances Dual Boost PFC: Control units

− Mean features − 97

B.1 Introduction …………………………………….. 97 B.2 Altera® Cyclone I EP1C6Q240C6 ……………... 97 B.3 TI® TMS320F2812 …………………………….. 99

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C IEEE 754 Standard Floating point arithmetic FPGA

Math library implementation 101

C.1 Introduction …………………………………….. 101 C.2 Storage layout description ……………………… 101 C.3 Basics arithmetic operators …………………….. 104 C.3.1 Floating point adder/subtractor ………... 105 C.3.2 Floating point multiplier ……………….. 105 C.3.3 Reciprocal of a given number/floating

point divider …………………………… 105

C.4 Trigonometric functions ………………………... 106

Bibliography …….……………………………………... 109

Chapter 1. Overview of power electronics

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CHAPTER 1

OVERVIEW OF POWER ELECTRONICS 1.1 Introduction Power electronic converters can be found wherever there is a need to modify the electrical energy form, therefore, they provide the needed interface between the electrical source and the electrical load as depicted in fig.1-1. The power electronics interface facilities the transfer of power from the source to the load by converting voltages and current from one to another, in which it is possible for the source to the load to reverse roles. The controller shown in fig.1-1 allows the management of the power transfer process in which the conversion of voltages and currents should be achieved with an high energy-efficiency and high power density as possible. Adjustable speed electric drives represent an important application of power electronics. With "classical" electronics, electrical currents and voltage are used to carry information, whereas with power electronics, they carry power. Therefore the main metric of power electronics becomes the efficiency.

Fig.1-1: Power electronics interface between the source and the load.

Power electronic systems must be energy efficient and reliable, have a high power density thus reducing their size and weight, and be low cost to make the overall system economically feasible. High energy efficiency is important for several reasons: it lowers operating cost by avoiding the cost of wasted energy, contributes less to global warming, and reduces the need of cooling therefore

Converter

Controller Source Load

Power Electronics interface


2

increasing power density. It’s an old adage: a penny saved is a penny earned. Not only energy conservation leads to financial savings, it helps the environment. It can easily show the relationship in a power electronic system between the energy efficiency, η, and power density. The energy efficiency is defined as:

o

o loss

PP P

η =+

where Po is the output power and Ploss the power losses within the system.

1.2 Power systems classification

The power conversion systems can be classified according to the type of the input and output power as follow:

• AC to DC (rectification) • DC to AC (inversion) • DC to DC (chopping) • AC to AC (cycloconvertion)

AC/DC converters (rectifiers) are used every time an electronic device is connected to the mains (computer, television,...)

DC/AC converters (inverters) are used primarily in UPS or emergency light. During normal working conditions, the electricity will charge the DC battery. During blackout time, the DC battery will be used to produce AC electricity at its output to power up the appliances. An important application, in the power electronics and electrical drives, is the adjustable speed/position electric drives.

DC/DC converters are used in most mobile devices (mobile phone, pda...) to maintain the voltage at a fixed value whatever the charge level of the battery is. These converters are also used for electronic isolation and power factor correction.

(1-1)


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AC/AC converters are used to change either the voltage level or the frequency (international power adapters, light dimmer). In power distribution networks AC/AC converters may be used to exchange power between utility frequency 50 Hz and 60 Hz power grids.

1.3 Power systems − Operating modes DC to DC converters are important in portable electronic devices such as cellular phones and laptop computers, which are supplied with power from batteries primarily. Such electronic devices often contain several sub-circuits, each with its own voltage level requirement different than that supplied by the battery or an external supply. In the next chapters, in particular, will be discuss the application of this kind of converters in the field of power electronics, in particular the applications of the boost active filter converters will be discussed. DC to DC converters may be operate in two modes, according to the current in its main magnetic component (inductor or transformer):

• Continuous - the current fluctuates but never goes down to zero. • Discontinuous - the current fluctuates during the cycle, going down to

zero at or before the end of each cycle. In general a converter could be designed in order to operate in continuous mode (CCM) at high power, and in discontinuous mode (DCM) at low power. A cycloconverter converts an AC waveform, such as the mains supply, to another AC waveform of a lower frequency, synthesizing the output waveform from segments of the AC supply without an intermediate direct-current link. They are most commonly used in three phase applications. In most power systems, the amplitude and the frequency of input voltage to a cycloconverter has fixed values, whereas both the amplitude and the frequency of output voltage of a cycloconverter are variables. The output frequency of a three-phase cycloconverter must be less than about one-third to one-half the input frequency. The quality of the output waveform improves if more switching devices are used (a higher pulse number). Cycloconverters are used in very large variable frequency drives, with ratings of several megawatts.


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1.4 Energy conversion topologies The power converters, beside, can be classified in function of energy conversion mode [1] in:

Linear regulators, fig. 1-2, can output a lower, but not higher, voltage than the input. They are very inefficient if the voltage drop is large and the current high as they dissipate as heat power equal to the product of the output current and the voltage drop; consequently they are not normally used for high-current applications. The inefficiency wastes power and requires higher-rated, and consequently more expensive and larger, components. The heat dissipated by high-power supplies is a problem in itself as it must be removed from the circuitry to prevent unacceptable temperature rises. Linear regulators are inexpensive, reliable, and much simpler than switching regulators. As part of a power supply they may require a large and expensive transformer, unlike switch-mode circuits. Linear regulators can provide a very low-noise output voltage, and are very suitable for powering noise-sensitive low-power analog circuits.

Electronic switch-mode DC to DC, fig. 1-3, converters convert one

DC voltage level to another, by storing the input energy temporarily and then releasing that energy to the output at a different voltage. The storage may be in either magnetic components (inductors, transformers) or capacitors. This conversion method is more power efficient (often 80% to 98%) than linear voltage regulation.

Fig. 1-2: Linear DC power supply

Controller

Line frequency transformer

Utility supply Va,ref

Va Vd


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In addition, each topology may be: • Hard switched - transistors switch quickly while exposed to both full

voltage and full current. • Resonant - an LC circuit shapes the voltage across the transistor and

current through it so that the transistor switches when either the voltage or the current is zero.

Fig. 1-3: Switch-mode power supply 1.5 Recent and potential advancements Technological progress of power devices has a close relationship with their market needs. That is, they are always required to be less noisy, higher efficient, smaller size, lighter weight, more advanced in function, more accurate, and larger capacity. In order to meet these needs a rapid growth in semiconductor fabrication technology is in progress. The power electronics interface of fig.1 consists of solid-state devices, which operate as switches, changing from on to off at a high frequency. There has been a steady improvement in the voltage and current handling capabilities of solid-state devices such as diodes and transistors, and their switching speeds have dramatically increased, with some devices switching in tens of ns. Devices that can handle voltages in kVs and currents in kAs are now available. These semiconductor switches are also integrated in a single package with all the circuitry needed to make them switch, and to provide the necessary protection. Moreover, the costs of these devices are in a steady decline, however a qualitative observation given in the Table I can be made. This table summarize the fundamental properties [1] of the commonly used power devices in function in their power capability and the switching speed, these are the main factors in the choice of a device for a particular application.

Vd

Va

Controller Va,ref

+ -

Rload

iL


6

Device Power Capability Switching speed BJT Medium Medium Mosfet Low Fast GTO High Slow IGBT Medium Medium

Table I: Properties of commonly used controllable switches. Power electronics has benefited from advances in the semiconductor fabrication technology in another important way. The availability of Application Specific Integrated Circuits (ASICS), Digital Signal Processors (DSPs), micro-controllers, and Field Programmable Gate Arrays (FPGAs) at very low costs makes the controller function in the block diagram of fig. 1 easy and inexpensive to implement, while greatly increasing functionality. Fig. 1-4: Symbols of commonly used controllable device mentioned in Table I GTO (a), BJT (b), IGBT (c) and Mosfet (d). The progress in semiconductor technology will undoubtedly lead to higher power ratings, faster switching speed, and lower costs. On the other hand, the forced-commutated thyristor, which was once widely used in circuits for controllable switch applications, is no longer being used in new converter designs with the possible exception of power converter in multi MVA ratings. This is a pertinent example of how the advances in semiconductor power devices have modified converter design.

(a) (b) (c) (d)

vCE B

C

E

iB

iC

G

D

S

vDS

iD

G

C

E

vCE

iC

vAK G

A

K iG

iC


7

A summary of power device capabilities is shown in the following fig. 1-5:

Fig. 1-5: Applications for power devices (From the MITSUBISHI website). Another family of controllable electronic switch is given by the MOS-Controlled Thyristors (MCT). This is a new device that is just appeared on the commercial market. This device has many properties of a GTO, but is a voltage controlled switch, the energy required to control a MCT is the same of that required by a Mosfet or a IGBT. 1.6 Desired characteristics in power electronic device − efficiency analysis In power electronics applications it is desirable that the used power device should have an ideal behaviour, therefore, should be acts as an ideal switch. The ideal controllable switch has the following characteristics [1]:

• Block arbitrarily large forward and reverse voltages with zero current flow when off;


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• Conduct arbitrarily large current with zero voltage drop when on; • Switch from on to off or vice versa instantaneously when triggered; • Small power required from control source to trigger the switch.

Unfortunately the switches are not ideal, therefore, the above conditions are not satisfied, in particular the switching times are not null and in the on state a drop voltage is present. In the real devices conduction losses and switching losses are present. In order to consider power dissipation in a semiconductor device, a controllable switch is connected in the simple circuit shown in fig. 1-6. This circuit models a very commonly encountered situation in power electronics. Fig. 1-6: Simplified clamped inductive switching circuit. By adopting this well know model and with the reference to fig. 1-7 the following consideration can be carry out. The energy dissipated in the device during the turn-on and turn-off transition within the nth switching time are, respectively:

_ , , , _12C ON n OFF n ON n c ONW V I t= ⋅ ⋅

_ , , , _12C OFF n OFF n ON n c OFFW V I t= ⋅ ⋅

with: VOFF switch voltage in the off state; VON switch voltage in the on state; ION switch current in the on state; tC_ON turn on time; tC_OFF turn off time.

Vd +

-

Ia

IT

VT

Ideal


9

Therefore, the power losses over a modulation period due to the turn-on and turn-off transition are:

_ , , , _1

2C ON n OFF n ON n C ONs

P V I tT

= ⋅ ⋅

_ , , , _1

2C OFF n OFF n ON n C OFFs

P V I tT

= ⋅ ⋅

The total switching power losses can be expressed by:

,DSW n d dP fV I d=

where f the switching frequency, I

d the device collector current, V

d power device

terminal voltage and d is the turn-on and turn-off time coefficient. This is an important results because it shows that the switching power loss in a semiconductor switch varies linearly with the switching frequency and the switching times. Therefore, if power device with short switching times would be available, it would possible to operate at high switching frequencies in order to reduce filtering requirements and the same time keep the switching power losses in the device from being excessive. Fig. 1-7: Linearized power devices switching characteristic. The medium power losses during a whole period T of the source voltage can be expressed as follows [2]:

__ , , ,

12

NC ONC ON OFF n ON n ON n

s n

tP V I

T == ⋅ ⋅ δ∑

__ , , ,

12

NC OFFC OFF OFF n ON n OFF n

s n

tP V I

T == ⋅ ⋅ δ∑

_C ONt

sT_C OFFt

ONI

OFFV

OFFIOFFI

OFFV

ONV

(1-2)


10

where CN T f= ⋅

and

,

1

0ON n

=⎧⎪δ ⎨⎪=⎩

,

1

0OFF n

=⎧⎪δ ⎨⎪=⎩

For what concerns the conduction losses within the nth switching period, an approximate evaluation can be performed by means of the follow relation:

, ,,

ON n ON n ONcond n

S

V I tP

T⋅ ⋅

=

where tON the on state switching command duration represents. In the whole period:

, ,1

NON

cond ON n ON ni

tP V I

T == ⋅∑

The on-state value of the voltage VON,n can be evaluated within each sampling period by means of:

, ,ON n O ON ON nV V R I= + ⋅

where V0 and RON are parameters which depends on the particular power device used. In this way, the total power losses in the whole period T referred to each switch can be evaluated as follow:

_ _loss C ON C OFF condP P P P= + +

From the considerations discussed in this paragraph, the following characteristics in a controllable switch are desirable:

• Small leakage current in off state; • Small on-state voltage VON to minimize on-state power losses; • Short turn-on and turn-off times. This will permit the device to be used

at high switching frequencies.

(1-3)

if the turn-on transition occurs in the nth sampling time

if the turn-on transition does not occurs in the nth sampling time

if the turn-off transition occurs in the nth sampling time

if the turn-off transition does not occurs in the nth sampling time

(1-4)

Chapter 2. Overview of PFC

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CHAPTER 2

OVERVIEW OF POWER FACTOR CORRECTION SYSTEMS

2.1 Introduction It is generally the task of power electronics to convert the electric power available from a power source into the best form suited for the user loads. The input power source for equipment handling less than 3 kW of power is usually a single-phase AC source. The converter itself may be an AC–DC or an AC–AC converter, with or without transformer isolation, depending on the requirements of the load. It was very common in the past to use a simple, single-phase diode bridge rectifier with a capacitive output filter as the first stage of the converter as shown in fig. 2-1. The diode bridge rectifies the AC input voltage and the capacitor smoothes out the resulting voltage to make it an almost pure DC waveform. The current drawn from the AC utility source, however, is very non sinusoidal because the bridge diodes conduct current only when the rectified input voltage is equal to or greater than the DC capacitor voltage as shown in fig. 2-2. It is only then that current flows to charge the capacitor. Fig. 2-1: Single phase diode bridge rectifier with capacitive output filter. The diode bridge rectifier shown in fig. 1 has a poor power factor because of the non sinusoidal current it draws from the utility. This current has a very high

C dvacv

D1 D2

D3 D4

iAC AC main

load or

other converter

IDC


12

peak and contains large harmonic components that are injected into the utility supply. If vast numbers of such converters were to be used in industry, the harmonics that would be injected in the utility would be so large that they would create a need for increased volt-ampere ratings of utility equipment (i.e., transformers, transmission lines, and generators) and distort the utility voltage. Fig. 2-2: Diode bridge rectifier output voltage, output current and input current waveforms.

The significant rise [3] in the use of electrical equipment in recent years due to increased consumer demand has made the inefficient use of power less tolerable than in the past. Today, the electrical equipments in Europe must comply with the European Norm IEC-61000–3–2 in force since 2001, and IEEE-519. A sinusoidal waveform is not needed to comply with this regulation. The only requirement is for the harmonic content of the input power to be measured at nominal input voltage and for the input current to be below a limit set by the above mentioned regulations.

VO

t

IDC

t

IAC

t


13

More and more, electrical equipment manufacturers are being forced to improve or “correct” the input power factor of products supplied by an AC utility source. The most common approach to Power Factor Correction (PFC) in a front-end AC–DC converter is to use an active AC–DC boost converter, which is shown in fig. 2-3 along with some typical input current waveforms shown in fig. 2-4−2-5. The converter can produce input current waveforms that are either continuous and sinusoidal with some ripple, or discontinuous and bounded by a sinusoidal envelope with substantially more ripple. The current in both the cases is effectively sinusoidal. Fig. 2-3: AC-DC Active boost converter.

-15

-10

-5

0

5

10

15

0 0.005 0.01 0.015 0.02

time [s]

AC m

ain

curr

ent [

A]

Fig. 2-4: AC-DC boost PFC converter input waveform current in the case of discontinuous conduction mode (DCM).

D5 Lb

C dvT bvacv

D1 D2

D3 D4

iAC

i

AC main

converter


14

-20

-15

-10

-5

0

5

10

15

20

0 0.005 0.01 0.015 0.02

time [s]

AC m

ain

curr

ent [

A]

Fig. 2-5: AC-DC boost PFC converter input waveform current in the case of continuous conduction mode (CCM). Power Factor Correction shapes the input current of power supplies to maximize the real power available from the mains. Ideally, the electrical appliance should present a load that emulates a pure resistor, in which case the reactive power drawn by the device is zero. The current is a perfect replica of the input voltage (usually a sine wave) and is exactly in phase with it. In this case the current drawn from the mains is at a minimum for the real power required to perform the needed work, and this minimizes losses and costs associated. The use of a PFC converter is twofold:

• assuring a unitary power factor by enforcing the voltage and the current delivered by the electric network to be in phase;

• regulating the output voltage to a desired reference value.

The freedom from harmonics also minimizes interference with other devices being powered from the same source. Fig. 2-6 shows the harmonic content of the current waveform of typical single phase bridge rectifier shown in fig.2-1. The fundamental is shown with a


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reference amplitude of 100%, and the higher harmonics are then given with their amplitudes shown as percentages of the fundamental amplitude.

0%

20%

40%

60%

80%

100%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Harmonic number

Fig. 2-6: Harmonic content of the current waveform reported in fig. 2-1.

0%

20%

40%

60%

80%

100%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Harmonic number

Fig. 2-7: Harmonic content of the current waveform of a boost PFC converter. In this manner the input current is shaped to match the input voltage waveform. This is the most popular type of PFC used in today’s power supplies, but it isn’t the only approach to do this.


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The following figure shows the input characteristics of three different [4] 250 W PC power supplies, all with the current waveforms at the same scale factor.

Fig. 2-8: Input characteristics of PC power supplies with different PFC types (None, Passive and Active). In the following is shown the input harmonics of three 250 W PC power supplies, along with the limits according to EN61000−3−2.

Fig. 2-9: Input harmonics of three PC power supplies relative to EN61000-3-2 limits. These limits are for Class D devices, which include personal computers, televisions and monitors. The harmonic amplitudes are proportional to the input power of these devices. The performance of the passive PFC, as shown in this graph, just barely complies with the limit for the third harmonic. The passive PFC circuit suffers from a few disadvantages despite its inherent simplicity.

Harmonic number


17

First, the bulkiness of the inductor restricts its usability in many applications. Second for worldwide operation a line voltage range switch is required, incorporation of the switch makes the appliance/system prone to operators errors if the switch selection is not properly made. It useful to remember that the standard EN61000−3−2 divides the different types of equipment in four classes and then, it specifies for each one of them a limit for each harmonic order between 3-39. If any of these harmonics of the input current is above the limits, the regulations will not be complied. The classification of the equipment[5] is as follows:

• Class B − portable equipment; • Class C − lighting equipment; • Class D − computers, TV sets and monitors; • Class A − all the rest of equipment.

As can be seen most of the industrial power supplies will be included in the Class A group, hence, only the limits of this class will be taken in count in this book.

2.2 Recent developments Recently, several new applications have emerged as additional drivers for the development of the technologies. One such application is commercial transport airplanes where single-phase PFC converters capable of meeting stringent airborne power quality requirements are required for in-flight entertainment (IFE), avionics, communication, and other single-phase loads. The proliferation of variable-speed motor drives in home appliances has also generated a new need for high-power (up to a few kilowatts), high-efficiency, and low-cost single-phase PFC converters. Single-phase diode rectifiers were traditionally used on transport airplanes to power avionics, communication, and other airborne electronic systems. In the late 1990's, airliners started to install PFC systems, which significantly increased the rectification loads of the overall aircraft electrical power systems.


18

The challenges in designing single-phase PFC converters for airborne applications are of twofold. First, the harmonic current limits are much more stringent than for terrestrial systems. Second, the fundamental frequency of airborne AC power system is in the range of 360-800 Hz, compared to 50 and 60 Hz in terrestrial systems. The combination of high line frequency and stringent harmonic current limits requires that the current control bandwidth be much higher than what is required for 50/60 Hz terrestrial applications. There are two major drivers for home appliance applications of PFC converters in recent years:

new functions, such as variable washing cycles in washing machines and different cooking modes in automatic rice cookers;

reduction of energy consumption in air conditioners and refrigerators through the use of variable-speed motor drives.

Unlike airborne applications where control performance, size, and weight are most critical, efficiency and cost are the most important design constraints for home appliance applications, which necessitates the use of different technologies. At last an example of residential applications of the PFC systems is represented by elevator plants, where they represent an effective and cheap solution. 2.3 Boost Converter modelling Fig. 2-10: Circuit diagram for a boost converter. A boost converter works in three different [6] modes, the block diagram for the switching is given in fig. 2-11. The Ip and Vd are the state triggers.

Lb

C outvT RL inv

Rb rsw rc

rd D


19

Fig. 2-11: Block diagram of the switching scheme.

Mode 1: The switch is closed, the inductor is allowed to gain the energy until the inductor current reaches a predefined peak value. In other words the system will remain in this mode if the i≤Ip If this condition is violated the system will switch to mode 2.

Mode 2: The switch is open and i>0, the energy gained by inductor will be transferred to the capacitor. It will remain in this mode until the inductor current becomes zero, the switching control will check the capacitor voltage. It will be switched to mode 1 if the capacitor voltage is less than the reference voltage at that moment, otherwise it will go to a “relaxation mode” (mode 3).

Mode 3: The switch is open and i=0, v≥Vout, this can be viewed as a relaxation mode. The capacitor will transfer its excess energy to the load, and the system will remain in this mode as long as i=0 and v>Vout.

In the last mode the converter works in discontinuous inductor current mode, then the diode become reverse biased. The capacitor energy is lost in the load resistance and the voltage reduces. Once this condition is violated the system will be switched in to the mode 1.

Mode 1 Pi I≤

Mode 2 0i >

Mode 3 0i =

dv V≥

Pi I>

0i = & dv V<

dv V< 0i = &dv V≥


20

A boost converter can be described by its generic modes with the state space equation (2-1). Here the index k denotes the mode. The switching doesn’t influence directly the state, but the Ak, Bk and Ck matrices may get changed. Ck is chosen so that yk can be used as threshold condition in mode k. The external input is assumed to be constant during the mode and can be assumed to be unity without loss of generality. Therefore,

.

k k

k k

x A x By C x=

= ⋅ +

⋅

The state matrix is defined as and the other matrices are:

1

0

10( )

b sw

b

L c

R rL

A

R r C

+⎡ ⎤−⎢ ⎥⎢ ⎥=⎢ ⎥

−⎢ ⎥+ ⋅⎣ ⎦

1

1

0bLB

⎡ ⎤⎢ ⎥= ⎢ ⎥⎢ ⎥⎣ ⎦

( )2

1

1 1

b d

b b

c cL Lb d

L c b L c b L

R rL L

Ar rR RR r

R r C L R r L R C

+⎡ ⎤− −⎢ ⎥⎢ ⎥= ⎢ ⎥⎛ ⎞ ⎛ ⎞

⋅ − ⋅ + − ⋅ +⎢ ⎥⎜ ⎟ ⎜ ⎟+ + ⋅⎢ ⎥⎝ ⎠ ⎝ ⎠⎣ ⎦

2

1

b

cL

L c b

LB

rRR r L

⎡ ⎤⎢ ⎥⎢ ⎥=⎢ ⎥

⋅⎢ ⎥+⎣ ⎦

( )3

0 010

L c

AR r C

⎡ ⎤⎢ ⎥= ⎢ ⎥−

+ ⋅⎢ ⎥⎣ ⎦

3

00

B⎡ ⎤

= ⎢ ⎥⎣ ⎦

bk k

out

iy C

v⎡ ⎤

= ⋅ ⎢ ⎥⎣ ⎦

The Ck for mode 1 and mode 2 are equal to: This is because both have at the

end of the modes the current as threshold.

The Ck matrix in mode 3 is because yk functions as a voltage threshold.

If the boost converter works in continuous mode (CCM) only the mode 1 and mode 2 are possible and by neglecting the stray parameters it’s possible to carry

k=1,2,….n (2-1)

b

out

ix

v⎡ ⎤

= ⎢ ⎥⎣ ⎦

10⎡ ⎤⎢ ⎥⎣ ⎦

01⎡ ⎤⎢ ⎥⎣ ⎦


21

out a simplified mathematical model suitable to describe the behaviour of the boost converter in the most situations. Besides by introducing a commutating function of the power switch the mathematical model of a boost converter assume a compact form as follow reported:

( ) ( )b b b ddv t L i t f Vdt

= + ⋅

where:

01

f⎧

= ⎨⎩

In particular equation (2-2) can be written as follows: ( ) ( )b b

b

di t v tdt L

=

( ) ( ) ( )b b d

b

di t v t v tdt L

−=

Therefore the full control of the PFC current control can be achieved only if the following condition occurs:

( ) ( )d bv t v t>

2.4 Boost Converter controlling In general, the control can be easily performed by using an hysteresis current control or by using a predictive current control strategy. The outer loop regulates the converter output voltage using a PI regulator. In order to enhance the dynamic performance Anti-windup technique is introduced into voltage loop regulators. As well known a digital system, to respect the equivalent analog implementation, is the delay introduced in the control due to the processing time Ts. A solution is to reduce the sampling time, while at the same time the overshoot of the transient response increases drastically. To solve this problem, the anti-windup PI (AW_PI) regulator is adopted with its parameters carefully designed to limit the overshoot so that the transient performance of the controller is improved. The core of a AW_PI regulator is to add a compensation in order to reduce the performance deterioration caused by windup integral.

(switch opened) (switch closed)

(2-2)

(2-3)

(2-4)

→

→

0f =

1f =

(2-5)


22

Fig. 2-12: Basic scheme of a Anti-windup PI regulator.

Ref. Value

Actual Value

Output Value

--

-

+

+

-

++

+

1

iT S

1

tT

K

Anti Wind up gain

Integrator

Chapter 3. Overview of Active Filters

23

CHAPTER 3

OVERVIEW OF ACTIVE FILTERS FOR IMPROVING POWER QUALITY

3.1 Introduction Active filtering as a means for harmonic compensation is becoming a cost effective solution for realizing a harmonic free utility interface for large non-linear power electronic loads such as adjustable speed drives. Non-linear loads such as diode, thyristor converters and cycloconverters, contribute to the degradation of the quality of the supply through the generation of harmonic waveforms and fundamental frequency reactive currents. Further degradations of the quality of the supply are caused by unbalanced three phase currents, sub-synchronous frequency currents with subsequent modulation of the supply voltage waveform and loads that cause sags and surges in the supply voltage profile. Harmonic currents drawn from the supply by the non-linear loads results in the distortion of the supply voltage waveform at the point of common coupling due to the finite supply impedance. Most power electronic loads used in industry today convert the incoming utility AC voltage to an intermediate or final DC voltage. This rectifier function is frequently uncontrolled, realized with an input diode bridge, or may be controlled by using thyristors. The utility interface further depends on the filtering elements used in the system. In the past passive filters [7] consisting of a bank of tuned LC filters and/or a high-pass filter have been broadly used to suppress harmonics because of the low initial cost and high efficiency. However, passive filters had the following disadvantages:

• Source impedance strongly affects filtering characteristics; • Parallel resonance between a source and a passive filter causes

amplification of harmonic currents on the source side at specific frequencies;


24

• A passive filter may fall into series resonance with a source so that voltage distortion produces excessive harmonic currents flowing into the passive filter;

• Passive filters tend to be susceptible to load and line switching transients.

Pure passive filters [8] do not constitute a viable and effective means for harmonic compensation of large industrial loads and in general distribution system loads. Pure passive filter solutions are only justified for high voltage transmission systems for which detailed systems studies are invariably done and engineering effort is only a small fraction of the total system cost. With remarkable progress in the speed and capacity of semiconductor switching devices such as GTO thyristors and IGBTs, active filters consisting of voltage or current-source PWM inverters have been studied and put into practical use because they have the ability to overcome the abovementioned disadvantages inherent in passive filters. However, active filters have the following problems:

• It is difficult to construct a large-rated current source with a rapid current response;

• Initial costs and running costs are high.

A number of low-power electronic-based appliances such as TV sets, personal computers, and adjustable speed heat pumps generate a large amount of harmonic current in power systems even though a single low-power electronic based appliance, in which a single-phase diode rectifier with a DC link capacitor is used as utility interface, produces a negligible amount of harmonic current. Three-phase diode or thyristor rectifiers and cycloconverters for industry applications also generate a large amount of harmonic current. In general, individual low-power end-users and high-power consumers are responsible for limiting the current harmonics caused by power electronic equipment, while electric power companies are responsible for limiting voltage harmonics at the point of common coupling in power transmission and distribution systems. Since the basic principles of active filters were proposed around 1970, attention has been paid to active filters. Moreover, deeper interest in active filters has been spurred by the emergence of insulated-gate bipolar transistors (IGBTs),


25

along with the availability of digital signal processors (DSPs), field-programmable gate arrays (FPGAs), Hall-effect voltage/current sensors, and isolation amplifiers at reasonable cost [9]. Modern active filters are superior in filtering performance, smaller in physical size, and more flexible in application, compared to conventional passive filters using capacitors, inductors and/or resistors. However, the active filters are slightly inferior in cost and efficiency to the passive filters, even at present. The advance of power electronics technology over the last years, along with the theory of instantaneous active and reactive power in three-phase circuits which was presented in 1983, has made it possible to put active filters into practical applications, not only for harmonic compensation with or without reactive power compensation, but also for flicker compensation and voltage regulation. Nowadays, several shunt active filters consisting of voltage-fed PWM inverters using IGBTs or GTO thyristors are operating properly, the capacity or rating of which ranges from 50kVA to 60MVA. All of them have been installed by individual high-power consumers on their own near harmonic-producing loads. Nonlinear loads drawing non-sinusoidal currents from electric utilities are classified into identified and unidentified loads by whether electric utility companies can identify the point and capacity of harmonic-producing loads on distribution systems. Large capacity diode or thyristor rectifiers, cycloconverters, and arc furnaces installed by high and medium voltage consumers are typical identified harmonic- producing loads. On the other hand, single phase diode rectifiers with DC link capacitors are representative unidentified harmonic producing loads, which have been widely used as utility interface in TV sets, personal computers, and so on. Although a single phase diode rectifier generates a negligible amount of harmonic current, the total amount of harmonic current produced by all the single phase diode rectifiers has become dominant rather than non-negligible in power distribution systems at present. No one has paid attention to unidentified harmonic-producing loads except for some of the researchers and engineers in power electronics and power engineering, so that the guidelines or regulations for harmonic mitigation would play an important role. The following [10] table shows an interesting analogy in unidentified sources between harmonic contamination and air pollution.


26

Sources Harmonic pollution Air pollution Unidentified: − TV sets, and personal

computers; − Adjustable speed heat pumps.

− Gasoline fuelled vehicles; − Diesel powered vehicles.

Identified: − Bulk rectifiers; − Cycloconverters; − Arc furnaces.

− Chemical plants; − Coal and oil steam power stations.

Table I : Analogy between harmonic pollution and air pollution 3.2 Classification of active filters

3.2.1 Classification by objective Active filters for improving power quality are classified into two types of active filters. One is active filters which have already been installed by individual electric power consumers on their own near one or more identified harmonic producing loads. Another is active filters which will be installed by electric power utilities on their own substations and/or distribution feeders. The purpose of active filters installed by electric consumers is to compensate current harmonics, current unbalance or negative sequence currents, and voltage flickers. On the other hand, the purpose of active filters installed by electric utilities would be to compensate for voltage harmonics at the point of common coupling in distribution systems, and to damp harmonic propagation caused by resonance between line inductors including leakage inductances of distribution transformers and shunt capacitors for improving power factor in power systems.


27

3.2.2 Classification by system configurations Fig. 3-1 shows [11] a system configuration of a shunt active filter standing alone, which is one of the most basic system configurations. The shunt active filter injects a compensating current into the supply to cancel current harmonics contained on the AC side of a general purpose thyristor rectifier with a DC link capacitor for traction systems. Fig. 3-1: Shunt active filter standing alone.

Fig. 3-2: Series active filter standing alone. Fig. 3-2 shows a system configuration of a series active filter standing alone. The series active filter is connected in series with the supply through a matching

AFi

Diode rectifier

Shunt active filter

Diode rectifier

AFv

Series active filter


28

transformer, so that it is applicable to harmonic compensation for a large capacity diode rectifier with a DC link capacitor. Table II shows comparisons between the shunt and series active filters. This concludes that the series active filter has a “dual” relationship in each item with the shunt active filter.

Shunt active filter Series active filter System configuration Figure 3-1 Figure 3-2 Power circuit of active filter

Voltage fed PWM inverter with current minor loop.

Voltage fed PWM inverter without current minor loop.

Active filter acts as Current source iAF. Voltage source vAF. Harmonic producing load suitable

Diode or thyristor rectifiers with inductive loads, and cycloconverters.

Large capacity diode rectifiers with capacitive loads.

Additional function Reactive power compensation.

AC voltage regulation.

Table II : Comparison of shunt and series active filters standing alone. The following figures show three types of hybrid active and passive filters, the major purpose of which is to reduce initial costs and to improve efficiency. The shunt passive filter consists of one of more tuned LC filters and/or a high-pass filter. Fig. 3-3: Combination of shunt active filter and shunt passive filter.

Thyristor rectifier

Shunt active filterShunt passive filter

iAF


29

Fig. 3-4: Combination of series active filter and shunt passive filter.

Fig. 3-5: Active filter connected in series with shunt passive filter.

The combination with the passive filter makes it possible to significantly reduce the rating of the active filter, because the task of the active filter is not to compensate for harmonic currents produced by the thyristor rectifier but to achieve harmonic damping and to improve the filtering performance of the passive filter when used alone.

Thyristor rectifier


Shunt passive

filter


Thyristor rectifier

Shunt passive filter


30

These hybrid filters provide viable and effective solutions to harmonic filtering of high-power converters. However, they have difficulty in finding a good market because of the necessity of the transformer and the complexity of the passive filter. Fig. 3-6 shows the combination of a shunt active filter and a series active filter. The major purpose of the series active filter is harmonic isolation between the sub transmission system and the distribution system, and voltage regulation. An example of a basic unified power quality system having the only function of harmonic compensation is taken in the following. The series active filter, which keeps harmonic currents from flowing in and out of the distribution feeders, is controlled to present zero impedance for the fundamental frequency and to act as a resistor with high resistance for the harmonic frequencies. The shunt active filter, which absorbs harmonic currents generated from the feeders, is controlled to present high impedance for the fundamental frequency and to act as a resistor with low resistance for the harmonic frequencies. Fig. 3-6: Combination of series active filter and shunt active filter. The active filters are mainly used as input stage of a single AC drive or as stand-alone unit feeding multiple drives on a common DC bus. In the former case, the active filter is completely integrated inside the drive structure, and also called “Active Front-End Converter”. Thanks to this full integration, the filter can be easily controlled by using the same hardware system used for controlling the drive. Drawbacks are the higher


Primary Distribution Transformer


Feeders

6kV

vAF

iAF iS

vS


31

cost compared to a classical diode rectifier, the necessary chokes in the mains which are bulky, heavy and represent further additional costs [12]. Within the active filter systems, a very important role is represented by the PWM rectifiers. They guarantees the same performances of the traditional active filters (reactive power compensation and THD factor reduction) allowing, at the same time, the control of the DC bus voltage and a bi-directional power flow. This last feature can be very important in high performance AC drives with frequent acceleration and deceleration. Fig. 3-7: Induction motor drive with active Front-End Inverter.

R, L

R, L

R, L

T1 T2 T3 T1m T2m T3m

C Vdc Induction

Motor

DIGITAL CONTROL UNIT

DC reference voltage AC motor speed reference


32

Chapter 4. Dual Boost PFC − Mathematical formulation −

33

CHAPTER 4

DUAL BOOST HIGH PERFORMANCES POWER FACTOR CORRECTION (PFC)

− MATHEMATICAL FORMULATION −

4.1 Introduction The use of Power Factor Correction (PFC) is necessary in order to comply the recent international standards, such as IEC-61000-3-2 and IEEE-519, as already mentioned in the previous chapters,. The PFC can reduce the AC line current harmonics and at the same time increase the energy efficiency allowing a reduction of the utility bills. In literature two different solutions are described in order to control both line current distortion and the power factor: the Power Factor Correction (PFC) circuit and the Front End Inverter (FEI) [13]-[24]. The former is generally used in low power applications, such as single phase residential applications, where a bidirectional power flow is not required. The second, instead, is used in a wide power range and in particular when four quadrant operations are required. In this chapter, starting from the basic circuit of fig. 4-1, two novel dual boost solutions are presented. The proposed PFC is shown in fig. 4-2 and it is based on a dual boost circuit where the first one (switch Tb1 and choke Lb1) is used as main PFC circuit and where the second one (switch Tb2 and choke Lb2) is used to perform an active filtering. Fig. 4-1: Classical PFC circuit.

D5 Lb

C dvT bvacv

D1 D2

D3 D4

iAC

ib

AC main


34

Fig. 4-2: Proposed dual PFC circuit. The purpose of the active filtering performed by the second boost circuit is to increase the quality of the line current and at the same time to reduce the PFC total switching losses. The switching losses reduction effect come from the different values of both the switching frequency and current amplitude of each switch. In particular for the first switch (in the following called main switch) high currents and low switching frequency are used, while for the second switch (in the following called filtering switch) the control algorithm imposes high switching frequency and low current.

4.2 Control Algorithms − Basic concepts Control strategy for a generic electrical system is intended a set of actions capable to detect the time evolution of the electrical quantities and to impose them to follow a desired time evolution. For an electrical drive, DC or AC motor speed/position control strategy, these quantities are the speed and position respectively. In the case of power converter the controlled quantities can be a AC/DC voltage or a current if a current control strategy is performed. In general a control algorithm can be spitted in three functional sub-blocks or control algorithms on the basis a not yet normalized definitions as depicted in the following:

1. Control algorithm; 2. Feeding algorithm; 3. Converter control algorithm.

D6 Lb2

C dvTb1 bvacv

D1 D2

D3 D4

iAC

iPFC

AC main

Tb2

D5 Lb1 ib1

ib2


35

Fig. 4-3: Basic description and splitting of a control algorithm. The control algorithm provide to generate the reference values for the feeding algorithm on the basis of references values imposed to the controller, for example speed or position in the case of an electrical drive or the DC output voltage of a boost converter. The feeding algorithm give the voltage or current values to impose at the considered system or plant in order to follow the time evolution of the reference values coming from the control algorithm. It is important to underline that the feeding control algorithm is the core of a generic implemented control strategy. At last, the converter control algorithm on the basis of the information given by the feeding control algorithm provide to generate a right sequence of firing signals for the management of the used power modules, obviously compatible with the performances and or characteristics of the same used power electronic devices. In particular a major and detailed description of the last two functional blocks is given in the following paragraphs with the reference to proposed and adopted control strategies.

4.3 Dual PFC Modelling With reference to fig.4-2, by considering the PFC working in continuous conduction mode, the following voltage equations are worked out [25] [26]:

Control algorithm

Feeding algorithm

Converter control

algorithm

Control algorithm references

Feeding algorithm references

Imposed voltages or currents

Firing signals for the power converter

Measured or estimated quantities


36

1 1 1 1 1

2 2 2 2 2

1 2

b b b b b b d

b b b b b b d

PFC b b

dv L i R i f vdtdv L i R i f vdt

i i i

⎧ = + +⎪⎪⎪ = + +⎨⎪⎪ = +⎪⎩

where:

( ) ( )sin( )b bv t v t t= ω

1

01bf⎧

= ⎨⎩

2

01bf⎧

= ⎨⎩

the source main voltage and PFC commutation functions respectively represent. In particular, the (4-1) can be written as follows:

1 0bf = 1

1

( ) ( )b b

b

di t v tdt L

=

1 1bf = 1

1

( ) ( ) ( )b b d

b

di t v t v tdt L

−=

2 0bf = 2

2

( ) ( )b b

b

di t v tdt L

=

2 1bf = 2

2

( ) ( ) ( )b b d

b

di t v t v tdt L

−=

where: 1 0bi ≥ 2 0bi ≥

because of the unidirectional AC-DC diode rectifier of fig. 4-2.

if Tb1=1 (switch on) if Tb1=0 (switch off)

if Tb2=1 (switch on) if Tb2=0 (switch off)

(4-5)

(4-6)

(4-1)

(4-2)

(4-3)

(4-4) →

→

→

→


37

4.4 Dual PFC Controlling The control of the PFC currents ib1 and ib2 can be achieved only if the following condition occurs:

( ) ( )d bv t v t>

In particular if the (4-7) is satisfied it is possible to control the derivative of the total PFC current iPFC

1 2PFC b bdi di didt dt dt

= +

4.4.1 Principle of the control strategy The parallel connection of switch mode converter is a well known strategy. The advantages of this approach are: the overall higher efficiency, the reduction of the development cost due to the modular design and the high reliability. For what concern the PFC the interleaved power conversion constitutes one of the most interesting solution. This approach consists in a phase shifting of two or more boost converter connected in parallel and working at the same switching frequency. In fig. 4-4 the input currents of two interleaved PFC are shown. By using this approach the following results can be achieved:

reduction of the current ripple; reduction of conduction losses; size reduction of active and passive components as the boost choke;

The (4-4) and the (4-5) show that a theoretically cancellation of the current i

PFC

ripple is possible. In particular the following conditions have to be verified:

1 2

( ) ( ) ( )b b d

b b

v t v t v tL L

−=

(4-8)

(4-7)

(4-9)


38

2 1

( ) ( ) ( )b b d

b b

v t v t v tL L

−=

with: d2=1-d1

where d1 and d2 the boost duty cycle respectively represents. Unfortunately the

solutions of (4-9) and (4-10) are:

( ) 2 ( )d bv t v t= and 1 2b bL L=

and the application of the above constraints describes only an ideal working condition, fig. 4-5, not feasible in a real industrial application. Fig. 4-4: Input currents of two interleaved PFC. Fig. 4-5: Input current of two interleaved PFC in ideal working condition.

4.4.2 Current hysteresis control algorithm As above described , by using (4-4) and (4-5) the control of the PFC currents ib1 and ib2 can be achieved and, in particular, it is possible to track the desired value

(4-10)

(4-11)

(4-12)

iPFC

ib1

ib2

iPFC

ib1

ib2


39

of both the PFC reference currents evaluated by using the following control scheme : Fig. 4-6: Control scheme of the proposed dual boost converter. In this control scheme the magnitude of the desired PFC current *

PFCi is

determined by using a PI regulator which input is the difference between the reference and actual output voltage. In order to obtain an unity power factor, the argument of the total PFC current is determined by using the argument of the line voltage. Once the desired total PFC current is achieved, two current controls has to be performed for both the PFC circuits. The main PFC is modulated with an hysteresis control by imposing the total PFC current *

PFCi . A large hysteresis band bm allows to achieve low switching

frequency. The filtering PFC reference current is, instead, the difference between *

PFCi and the actual value of ib1. An hysteresis control is also

performed, but using a small hysteresis band bf. By using this approach the main PFC is used to transfer the desired power to the load while the filtering PFC is controlled in order to increase the total PFC current quality.

4.4.3 Predictive Control of Parallel Power Factor Correction In this paragraph is illustrated a novel predictive control, based on the active filtering approach, which is able to replicate the conditions (4-9) and (4-10) without the constraints (4-11) and (4-12). Practically by using an high switching frequency modulation performed on the filtering PFC the control algorithm have to impose, for any input and output voltages, the condition (4-9) and (4-10). In fig.4-6 are shown the input currents of two PFC working with the

i*DC

-

+

-

+

-

+

vDC

V*DC

ib1

ib2

eb bf

bm

T1

T2


40

proposed internal active filtering approach. Of course, by using the proposed approach, it is not possible to completely eliminate the i

PFC ripple, but a not

negligible reduction is achieved.

Fig. 4-7: Input currents of two PFC working with the proposed internal active filtering approach. The tasks of the predictive control can be synthesized as follows:

using the main PFC in order to feed the DC load; using the filtering PFC in order to improve the quality of the main

current. In particular, by using the control scheme depicted in fig. 4-8, the predictive control has to evaluate both the commutating function fb1

and fb2 in order to:

control both the currents ib1

and ib2;

control the switching frequency of main and filtering PFC; Starting from the (4-1) the following set of equation is achieved:

( ) ( ) ( )

( ) ( )

1 ( ) ( )111 1 1 1

1 ( ) ( ) ( )222 2 2 2

( 1) ( 1) ( 2)1 2

( )

( )

n n n n nbb b db b b b

s

n nn n nbb b db b b b

sn n n

PFC b b

Lv n i i R i f v

TL

v n i i R i f vT

i i i

+

+

+ + +

⎧ ⎡ ⎤= − + +⎪ ⎢ ⎥⎣ ⎦⎪⎪ ⎡ ⎤= − + +⎨ ⎢ ⎥⎣ ⎦⎪⎪ = +⎪⎩

where the superscripts (n) and (n+1) denote quantities at the sampling time (n)Ts and (n+1)Ts respectively.

i*PFC

i*b2

ib1

iPFC

(4-13)


41

Unfortunately in the (4-13) the unknown quantities:

( )11n

bi+ ; ( )1

2n

bi+ ; ( )

1n

bf ; ( )2n

bf ; ( 1)nPFCi +

are greater of the equations number. To overcome this problem the following strategy is proposed. The total input current is determinated by using the control scheme depicted in fig.4-8 where the filtering PFC commutation function is evaluated by using a fixed frequency hysteresis current control. Fig. 4-8: Control scheme of the proposed dual boost converter. At this point the (4-13) can be solved because the unknown quantities are only:

( )11n

bi+ ; ( )1

2n

bi+ ; ( )

2n

bf

Starting from the (4-13), after simple manipulations the following prediction of the filtering PFC commutating function is achieved:

( ) ( 1) ( 1) ( ) ( )221 2 2

1( )2 ( )

n n n n nbbPFCb b b b

s bnn

d

L Tsv i i i R iT L

fv

+ +⎡ ⎤− − − −⎢ ⎥

⎣ ⎦=

where:

( 1) ( ) ( ) ( ) ( ) ( )111 1 1 1

n n n n n nbbb b b b d b

s

Li v R i f v i

T+ ⎛ ⎞

= − − +⎜ ⎟⎝ ⎠

(4-14)

(4-15)

i*PFC

-

+

- +

vDC

V*DC

ib1

ib2

bm

T1

T2 ib1 Predictive

control


42

4.5 Dual Boost PFC efficiency analysis One of the main goals of the proposed control algorithm is to introduce improvements in terms of power losses reduction thanks to an Active Filtering (AF) approach. The use of active filtering for this purpose is not new. In [27]-[30] this approach, called Motor Side Active Filtering (MSAF), is used in order to reduce the switching losses of a Voltage Source Inverter (VSI) parallel connection for motor drive applications. The use of the active filtering for the switching losses reduction is based on simple analysis of the linearized switching characteristic of a power device. In order to show the improvement, in terms of efficiency, introduced by the proposed active boost converter filter, the switching power losses have to be analysed. This analysis has made on basis to the considerations reported in the paragraph “1.6 Desired characteristics in power electronic device − efficiency analysis”. By with references to this paragraph it is easy to show that if the required load power is splitted on two different switches, operating with different switching frequency and with different currents, the total efficiency is greatly improved with respect to the case in which a single device is used. In particular in the proposed approach the main PFC (switch T

b1) works with high current and low

switching frequency while the filtering PFC (switch Tb2

) works with low current

and high switching frequency. Practically, by using the proposed algorithms, it is possible to control the quality of the total PFC current and besides control the switching losses sharing. In fact, starting from the (1-1;1-2), the ratio between main and filtering PFC switching losses is:

1 1 1

2 2 2

SW b b

SW b b

P f iP f i

=

where the amplitude of i

b1 is almost equal to the iPFC

one; fb2 is generally four or

five times of fb1 and the amplitude of i

b2 is equal to the error current of the main

PFC.

(4-16)

Chapter 5. Dual Boost PFC – Simulation results –

43

CHAPTER 5

DUAL BOOST HIGH PERFORMANCES POWER FACTOR CORRECTION (PFC) − SIMULATION RESULTS −

5.1 Introduction In this chapter are described the simulation results of the Dual Boost PFC architectures proposed in the previous chapter. For the current hysteresis control scheme, the simulations are made by considering, the implementation of the control strategy on a FPGA devices which, as well know in the literature, offer the advantage of a digital implementation in terms of stability and the performances of an analog circuit. The implementation of the hysteresis control strategy on a traditional DSP/Microcontroller based architecture in order to achieve the same performances of FPGA implementation implies to use a very expensive hardware architecture in order to obtain acceptable and comparable performances with the similar implementation on a low cost FPGA device. Instead the proposed predictive control scheme could be implemented on typical and common DSP/Microcontroller system having a non particular high performances, therefore a low cost hardware platform could be used. More details on the hardware architectures used to implement the proposed control algorithms are given in the next chapter and in the appendix B. The aim of the active filtering approaches, as already mentioned, is to comply to present international regulatory in term of harmonics pollution and at same time to increase the overall efficiency of the used power converter. In particular the objectives of the tests are to evaluate the performances of the proposed approach in terms of:

reduction of the current ripple; reduction of total switching and conduction losses.

The strategy used to obtain the above results is based on the comparison of the dual boost converter performances with the one obtained by using a classical


44

single boost PFC. Obviously the comparison is performed when both the converters work with the same load power and the same current quality. In this way once determined the switching losses the performances of both the converters are compared with the one obtained by using a classical single boost converter topology. In both the cases the current ripple has been evaluated in a single period of the AC main current with the following equations:

2*

0

1 ( ) ( )T

rip pfc pfci i t i t dtT

⎡ ⎤= −⎣ ⎦∫

max% 100rip

ripi

ii

=

where T is the AC mains period, i

rip is the mean value of the current ripple and

the desired value of the boost current. 5.2 Dual Boost PFC Simulation 5.2.1 − Current hysteresis control scheme − In order to perform a digital implementation of the control scheme shown in fig. 5-1, an FPGA device has been chosen. The proposed control scheme has been widely tested in simulation for a preliminary validation. In particular, a complete simulation of both the power electronic systems and of the control code has been performed by using the Matlab® Simulink® and the Altera DSP Builder® tools. Fig. 5-1: Control scheme of the proposed dual boost converter.

i*DC

-

+

-

+

-

+ vDC

V*DC

ib1

ib2

eb bf

bm

T1

T2

(5-1)

(5-2)


45

It has to underline that the use of the Altera® DSP Builder® allows to preliminary simulate the algorithm and then to program directly the FPGA starting from the Simulink® code. Obviously this approach is effective only if all the control components, included the digital and analog I/O, are properly simulated. Therefore the first simulation step is the reproduction of all the analog signals and their quantization process. In fig. 5-2 the Simulink® signals conditioning and A/D conversion code are shown.

Fig. 5-2: Simulink® signal conditioning and A/D conversion The former is composed by a gain block, which takes into account the current transducer constant (Lem Gain), and an offset equal to 2.5V used to allow an A/D conversion of both positive and negative quantities. A random number generator is also included to simulate the noise related to the signal conditioning circuit. The A/D conversion simulation code starts with a 5V saturation and a zero-order hold block is used to simulate the A/D converter Sample and Hold. According to the used 10 bit A/D converter datasheet, a conversion time of 2.5 μs has been chosen. A quantizer block simulates the A/D quantization error, Qe, evaluated by using the following well-known relation:

_5 0.0049

10242ref

e conversion bits

VQ = = =

where Vref is the A/D reference voltage. Therefore, the digital conversion gain and the following offset transform the quantized signal into a fractional [12]:[8] data bit. Once the A/D conversion

(5-3)


46

block has been tested, the FPGA control algorithm can be included in the Simulink® simulation. In fig. 5-3 the hysteresis current control performed by using the Altera® DSP Builder® is shown. The implemented algorithm for the generic power converter switch is:

( ) ( 1)n nx x −= *

( ) ( )*

( ) ( )

n n

n n

i i b

i i b

⎧ < +⎪⎨

> +⎪⎩

( ) 0nx = *

( ) ( )( )n ni i b> +

( ) 1nx = *

( ) ( )( )n ni i b< −

where:

x hysteresis output (i.e. switch command); i actual current; i* reference current; b hysteresis band;

and where with the subscript n the generic nth A/D conversion is denoted.

Fig. 5-3: Hysteresis current control performed by using Altera® DSP Builder® In particular, the hysteresis control is based, for each power switch, on two comparator (a_greater_b and a_less_b) which output drives the multiplexer (n-to-1 multiplexer). In particular, the first input (input 0) is selected if the on

(5-4)

(5-5)

(5-6) if

if

if


47

condition (5-4) is satisfied while the second and the third input are selected if the conditions (5-5) and (5-6) are respectively satisfied. The output port represents the firing signal of the power switch. In fig. 5-4 the main PFC current obtained with an hysteresis band of 5A is shown. It can be seen that an asymmetrical hysteresis band has been used. By means of equations (4-4);(4-6) reported in the previous chapter, in fact, is possible to control the derivative of both the main and filtering PFC currents but it is not possible to compensate negative errors of the main PFC current. Thus, to avoid that the quantity eip1 becomes negative the lower value of the main PFC hysteresis band has been set to zero. Fig. 5-5 shows a detail of the main PFC current, while in fig. 5-6 the filtering PFC current obtained with an hysteresis band of 1A is reported. As it is possible to see the amplitude of this current is 5A which is the amplitude of the main PFC current hysteresis band. The effect of the filtering current come clear in fig. 5-7 where a detail of main and filtering current is plotted. In fig 5-8 the total PFC current is shown. In this last graph a not negligible reduction of the current ripple is achieved. The ripple amplitude of the total PFC current is equal to 1A; which is the amplitude of the filtering current hysteresis band.

0

5

10

15

20

25

30

35

0 0.0025 0.005 0.0075 0.01

time [s]

Mai

n PF

C C

urre

nt [

A]

Fig.5-4: Main PFC current.

Reference current

Main PFC current


48

0

5

10

15

20

25

30

35

0.00375 0.00405 0.00435 0.00465 0.00495

time [s]

Mai

n PF

C C

urre

nt [

A]

Fig. 5-5: Main PFC current detail

0

5

10

15

20

25

30

0 0.0025 0.005 0.0075 0.01

time [s]

Filte

ring

PFC

Cur

rent

[A]

Fig.5-6: Filtering PFC current.

Main PFC inductor: 3.6 mH Filtering PFC inductor: 0.6 mH Output filter Capacitor: 1100 µF DC load: 200 Ω

Table I: System parameters.

Reference current

Main PFC current


49

0

5

10

15

20

25

30

35

0.00375 0.00405 0.00435 0.00465 0.00495

time [s]

Mai

n an

d Fi

lteri

ng P

FCcu

rren

ts [

A]

Fig.5-7: Detail of main and filtering PFC currents.

0

5

10

15

20

25

30

35

0 0.0025 0.005 0.0075 0.01

time [s]

PFC

Boo

st C

urre

nt [

A]

Fig.5-8.: Total PFC current. 5.2.2 – Predictive control scheme – In order to obtain a preliminary validation on the whole system several

simulations, based on the Simulink® Power toolbox, have been performed. The tests have been made with an AC supply voltage of 220 V @ 50 Hz and a current of 30A.

Filtering PFC current

Main PFC current


50

The fig. 5-9,5-10 and 5-11 show the dual boost PFC current obtained with the following conditions:

main PFC: 20kHz hysteresis current control; filtering PFC: 20 kHz predictive control; total PFC current of 30A.

-36

-24

-12

0

12

24

36

0 0.005 0.01 0.015 0.02

time [s]

AC M

ain

Cur

rent

[A]

Fig. 5-9: AC Line current.

0

6

12

18

24

30

36

0 0.0025 0.005 0.0075 0.01

time [s]

Mai

n PF

C C

urre

nt [

A]

Fig. 5-10: Main PFC current.


51

0

6

12

18

24

30

36

0 0.0025 0.005 0.0075 0.01

time [s]

Filte

ring

PFC

Cur

rent

[A]

Fig.5-11: Detail of filtering PFC current. As it is possible to see the most part of the power required by the load is provided by the main boost converter while the effect of the filtering converter is to reduce the ripple of the AC line current.

0

6

12

18

24

30

36

0 0.001 0.002 0.003

time [s]

Cur

rent

[A]

Fig. 5-12. Detail of main and filtering PFC currents. Fig 5-12 shows a detail of the system currents. In particular it is possible to see that the main converter works with a switching frequency of 6 kHz and a current of 30A. The filtering converter instead works with a current of 5A and a switching frequency of 37 kHz.

main current

filtering current


52

In fig. 5-13 is shown the current obtained by using the classical single boost converter. In this case, in order to obtain the same current quality the converter have to works with a current of 30A at the switching frequency of 20 kHz.

-36

-24

-12

0

12

24

36

0 0.005 0.01 0.015 0.02

time [s]

AC M

ain

Cur

rent

[A]

Fig. 5-13: AC Line current with a single boost converter operating with a classical predictive control strategy.

0

5

10

15

20

25

30

0 10 20 30 40 50 60 70 80 90 100

Drain-source current [A]

Switc

hing

dis

sipa

tion

[mJ/

puls

e]

Fig. 5-14: Switching energy, turn on turn off energy, vs. drain-source current of the SK 60 GAL 123.

EOn

EOFF


53

To determine the switching losses, the switching energy versus the drain-source

current characteristic of the Semikron®

SK 60 GAL 123, shown in fig. 5-14, has been used. The parameters of the dual boost converter are shown in the table II.

Main PFC inductor: 6.0 mH Filtering PFC inductor: 2.0 mH Output filter Capacitor: 1100 µF DC load: 100 Ω

Table II: System parameters. 5.3 Considerations The efficiency analysis performed by using the above mentioned characteristic in both the cases shows:

Current hysteresis control scheme a power losses reduction of 60 % about. In the case of single boost converter operation mode the switching power losses are 117W, instead, in the case of dual boost converter operating mode the global switching power losses are 47 W.

Predictive control scheme a power losses reduction of 55.1 %. In the case of single boost converter operation mode the switching power losses are 49W, instead, in the case of dual boost converter operating mode the global switching power losses are 27 W. The simulation results shown in this chapter confirm the validity and the feasibility of the proposed two PFC active filtering control strategies. In the shown simulations has been considered only the switching losses of a power device, the conduction power losses, because the use of the ideal power electronic devices, have been neglected. In the next chapter experimental results will be shown, the differences respect to simulations results are due to different operating conditions of the active filters, to the presence of the conduction losses and of the used not ideal power devices.


54

Chapter 6. Dual Boost PFC – Experimental results –

55

CHAPTER 6

DUAL BOOST HIGH PERFORMANCES POWER FACTOR CORRECTION (PFC) − EXPERIMENTAL RESULTS −

6.1 Introduction In this chapter are described the experimental results of the Dual Boost PFC architectures proposed in the previous chapters. For the current hysteresis control scheme, the implementation has been made by using an Altera® Cyclone® I EP1C6Q240C6 FPGA device. Instead the proposed predictive control has been implemented by using a Texas Instruments® TMS320F2812 DSP microcontroller based. In both the cases, by using the proposed power sharing control algorithms, based on active filtering approach, a near unity power factor is achieved. Moreover a not negligible reduction of switching losses, therefore, of the total device losses is achieved. 6.2 Experimental layout description In the following depicted experimental layouts, except for the used control unit and the power devices, the technique of voltage sensing and of current sensing is the same. In both the implemented control strategies the sensed currents are the main PFC current, the filtering PFC current and optionally, only in order to validate the tests the AC line current is sensed. To perform the experimental tests is strictly necessary to acquire the AC line voltage or the boost voltage in order to generate the modulo sine function needed for “building” the reference current at input of the adopted feeding algorithm. To keep the output voltage to a desired value is necessary to acquire also the output DC voltage.


56

In order to sense the currents the LEM® LA25 NP Hall effect current transducers have been used and to sense the voltages the LEM® LV25 P Hall effect voltage transducers have been used. For detailed usage of this transducers family consult the appendix A. The used Hall effect transducers mounted, as described in the appendix A, have the following main characteristics:

the current transducers have a range of the output voltage is 0 to 7.5V for the sensed input current range 0 to 25A.

in the case of voltage transducers the output voltage range is 0 to 8V for the applied input voltage range 0 to 500V.

The A/D converters present on TI® TMS320F2812 can acquire only positive voltages until 3V, while, the A/D converters mounted on Altera® EP1C6Q240C6 FPGA evaluation board can acquire only positive voltages until 5V. In both the circumstances, additional analog circuits are needed in order to fit the voltage of built sensing system to the acceptable voltage value for the A/D units of both the used control units. In order to acquire AC electrical signal the built additional analog conditioning signal system perform also a shift to positive voltages only. For what concern the AC line voltage a zero detect routine has been set up in order to generate the reference modulo sine function needed for the implemented predictive control strategy. In order to perform this operation, different solutions have been investigated and adopted in the case of dual boost PFC with a double hysteresis control scheme, implemented by using the FPGA device. In this case the zero detect of the AC line voltage has been performed via hardware by using a discrete IC National Semiconductor® LM139/LM339, or equivalent, that generates a positive voltage when the sensed voltage is positive and a null voltage, depending by adopted circuital configuration, when the sensed voltage assume negative values. As well mentioned in the previous chapter the “core” of the proposed control strategy has been developed by using Altera® DSP Builder® tool. The modulo sine reference math function is generated by detecting negative to positive AC line voltage transition by means the analog built-up comparator. This operation can be performed in the following mode:


57

• By building a look up table, this solution offers the simplicity of the implementation, in contrast an a large amount of memory location is required to do this. The number of memory locations increase when a less execution code time Ts is requested by the implemented control strategy.

• By using the well know CORDIC theory, this approach is very efficient respect to look up table approach, a sine or cosine function is generated with a few and flexible code instructions.

• At last, in our case, the absolute value of sine function has been built up by using a polynomial approximation, this approach has been the most efficient way to built the requested function when the signed fractional number representation is adopted.

Altera® DSP Builder® tool is able to manage integer numbers and fractional numbers, the use of fractional numbers depend greatly, in terms of device area occupation, of the used FPGA device. In our case a Cyclone® I EP1C6Q240C6 FPGA device has been used, by intrinsic limitation due to this device, optimal results has been obtained by using signed fractional numbers in the form 12:8, 12 digits reserved for signed integers value and 8 digits for the value less than the unity. For mode details on the used control units it useful refer to appendix B. Integer numbers could be adopted but by paying the price of the use of tedious and well known scaling techniques. By adopting integer numbers or by adopting fractional numbers in the format 12:8 [FPGA device] a loss of numerical resolution is unavoidable, but, for the implemented control algorithms this numerical resolution loss has not great influence on the performances of implemented algorithms. In order to obtain better performances, like a common floating point μP, but exploiting the well know characteristic offer by a FPGA device, is in progress the development of the implementation of the IEEE 754 floating point standard on FPGA devices. In particular a collection of various mathematical function has been already developed and tested, but using a non standard floating point representation, called sfloat_24 by the author, 24 bit short floating point numbers, in contrast to single precision number (32 bit) and double precision floating point numbers (64 bit) widely used in every calculus units. The choice of a 24 bit floating numbers has been made by the limited number of logic cells


58

available on the Cyclone® I EP1C6Q240C6 device. For furthermore information on the implementation of sfloat_24 math coprocessor on a FPGA device it useful refer to the appendix C. 6.3 Dual Boost PFC 6.3.1 – Current hysteresis control scheme – The performance of the proposed dual boost PFC has been experimentally investigated by using the 200 W prototype shown in fig. 6-1, where the control unit is the Altera® Cyclone® I FPGA while the power electronic circuits have been based on the Power Mosfet IR® SPP11N60S5 and on the IR® diode 30EPH06. Unfortunately the Cyclone® I EP1C6Q240C6 evaluation board has not provided of an analog to digital (A/D) unit section, therefore, in order to acquire the analog signals proportional to sensed voltages and main PFC and filtering PFC currents, an analog to digital board based on 10 bit National Semiconductor® AD1061CN A/D converters has built up and connected to used FPGA device. As described in the previous chapter this A/D converter, by the evaluation of the quantizer error and by its high speed, is widely suited for the proposed experimental layout, from it’s datasheet this A/D converter executes a conversion in only 2 µS, the main task time execution of the control algorithm has been set to 2.5 µS. The main PFC choke and the filtering PFC choke are equal to 3.6 mH and 0.6 mH respectively. The FPGA used in the experimental setup implements the following functions: to execute the control algorithm, shown in the previous chapter, and in particular perform a quasi-analog current control by using the code of fig.6-2; service of the A/D converter; shutdown the PFC in the case of overcurrent or overvoltage. The A/D handshaking code with a generic FPGA device can be written or by using the Altera® DSP Buider tool or by using the VHDL language, with the low level programming mode an optimal code can be carry out in terms of device area occupation. By programming in VHDL language it’s possible to develop an optimized code necessary to perform all the required tasks. By using the Altera® DSP Builder tool it’s most easy to implement a generic code but less efficient code, either in the area occupation device and either optimization terms, is obtained. By using the VHDL code portability problem between operating


59

platforms is also removed, in fact the same code can be executed on FPGA device provided by any manufacturer.

Fig. 6-1. An experimental dual boost converter prototype board.

Fig. 6-2: Hysteresis current control performed by using Altera® DSP Builder®

The graphic code shown in fig.6-2 is equivalent to write few instructions in VHDL code as: SoftwInt1: process(virtual_clk_net) begin if(virtual_clk_net'event and virtual_clk_net='1') then if(ad_main_value_net<(iref_net_main-banda_iste_net_m)) then sw_cmd_net<='1'; end if; if(ad_main_value_net>iref_net_main) then sw_cmd_net<='0'; end if; end if; end process SoftwInt1;


60

The handshaking of the used A/D converters with the used FPGA device has been implemented by writing the following code, its obviously has been written taking in count the technical specifications as reported in the datasheet.

ad_process : process(aux_adwr_net, ad_main_int_net) begin if(aux_adwr_net<='0' and ad_main_int_net<='0') then ad_main_rd_net<=aux_adwr_net; ad_main_value_net(9 downto 0)<=ad_main_input_net(9 downto 0) after 50ns; end if; end process ad_process; This code fragment, for example, manage a single A/D converter, for the management of a multiple and same time A/D conversion it is almost the same except to add other few variables. The obtained experimental results are reported in figs. 6-3;6-5. In fig. 6-3 the AC line current, the main PFC current (ib1) and the filtering PFC current (ib2) respectively are shown. In this test the main PFC hysteresis band (bm) is 0.5A while the filtering PFC hysteresis band (bf) is set to 0.15A. This test validates the proposed active filtering approach; in particular it shows that the filtering PFC current (fig. 6-3c) allows to compensate the not negligible ripple of the main PFC current (fig. 6-3b). In particular the average value of both the main and filtering PFC switching frequency is 4kHz and 23kHz respectively. In fig. 6-4 the same test is performed by using a main PFC hysteresis band of 0.25A. Also in this case it is possible to obtain a high quality line current but obviously an increase of the main PFC switching losses has been paid. Fig. 6-5 shows the oscilloscope screenshot of the test reported in fig. 6-4. Several tests has been performed with different values of both the hysteresis bands bf and bm in order to evaluate their effect on the system efficiency.


61

-3

-2

-1

0

1

2

3

0 0.005 0.01 0.015 0.02

AC m

ain

curr

ent [

A]

0

0.5

1

1.5

2

2.5

3

0 0.005 0.01 0.015 0.02

Mai

n PF

C cu

rren

t [A]

0

0.5

1

1.5

2

2.5

3

0 0.005 0.01 0.015 0.02

time [s]

Filte

ring

PFC

curr

ent [

A]

Fig. 6-3: AC main current (a), main PFC current (b), filtering PFC current (c) obtained with a main hysteresis band of 0.5A.

(a)

(b)

(c)


62

-3

-2

-1

0

1

2

3

0 0.005 0.01 0.015 0.02

AC M

ain

curr

ent [

A]

0

0.5

1

1.5

2

2.5

3

0 0.005 0.01 0.015 0.02

Mai

n PF

C C

urre

nt [

A]

0

0.5

1

1.5

2

2.5

3

0 0.005 0.01 0.015 0.02

time [s]

Filte

ring

PFC

Curr

ent [

A]

Fig. 6-4: AC main current (a), main PFC current (b), filtering PFC current (c) obtained with a main hysteresis band of 0.25A.

(a)

(b)

(c)


63

Fig. 6-5: Oscilloscope screenshot of main PFC current (a); filtering PFC current (b); AC line current (c); total boost PFC current (d). In particular the switching losses vs. the current ripple of the proposed dual boost PFC is compared with the one of a classical single boost PFC. In fig. 6-6 a thermal image of the tested circuit working in single boost mode (the filtering PFC is disabled) is shown. As it is possible to see the power switch temperature reaches 80.3°C while the temperature of the same switch, working in dual boost mode and at the same operating condition (current ripple, current amplitude and DC bus voltage) is 57.4°C (see fig. 6-7). The temperature difference is determined by the switching losses reduction achieved by using the proposed dual boost circuit. In particular a total losses reduction of 17% (main and filtering switching and conduction losses) has been evaluated by using a calibrated heat sink method. This method consists in the experimental determination of a thermal calibration curve that allows to evaluate the total device/converter losses (switching and conduction losses) simply by reading the component temperature. To determine this thermal calibration curve, by using a low power source, several DC currents have been injected in the power device and, for each test current, after the system reached the thermal equilibrium, the device temperature, the power device terminal voltage Vc and the injected current Ic have been measured.


64

At the steady state the dissipated power: d C CP V I=

is stored and plotted as function of the device temperature in order to determine the thermal calibration curve.

Fig. 6-6: Thermal image of the tested circuit working in single boost mode (a);

device temperature transient (b).

Fig. 6-7: Thermal image of the tested circuit working in dual boost mode.


65

In fig. 6-8 the above described thermal calibration curve is shown. Moreover, by using this method it is also possible to determine the device conduction losses as function of the device collector current, which is reported in fig. 6-9. It is possible to see that, by means of the proposed approach, a 45% reduction of the device losses is achieved.

00.5

11.5

22.5

33.5

44.5

5

0 50 100 150

Device temperature [°C]

Dev

ice

loss

es [

W]

Fig. 6-8: Device thermal characteristic.

00.5

11.5

22.5

33.5

44.5

5

0 0.5 1 1.5 2 2.5Device current [A]

Dev

ice

loss

es [

W]

Fig. 6-9: Device conduction losses.


66

6.3.2 – Predictive control scheme – The experimental tests have been performed by using a 2 kW prototype board shown in fig.6-10, the control algorithm is implemented on a Texas

Instruments®

TMS320F2812 DSP platform. This hardware platform is widely suitable for to execute all the required tasks, as well known, it has all the necessary peripherals for implementing the proposed control scheme, only a conditioning board has been built in order to fit the sensed analog signal proportional to the acquired voltages and currents in to range 0 − 3 V provided by the integrated 12 bit analog to digital converter sub system.

Fig. 6-10. Experimental 2kW dual boost converter prototype board. In fig. 6-11 are shown the currents waveforms in the case of dual boost converter topology, instead, in fig. 6-12a,b are shown the analogous results in the case of a single PFC operating mode, the total PFC current is 15A max. In fig. 6-12c a detail of main PFC current and filtering PFC current is shown in order to illustrate the active filtering principle.


67

-20

-10

0

10

20

0 0.005 0.01 0.015 0.02

AC m

ain

curr

ent [

A]

0

4

8

12

16

20

0 0.0025 0.005 0.0075 0.01

Mai

n PF

C cu

rren

t [A]

0

4

8

12

16

20

0 0.0025 0.005 0.0075 0.01

time [s]

Filte

ring

PFC

cur

rent

[A]

Fig. 6-11: AC main current(a), main PFC current (b) and Filtering PFC

current (c).

(a)

(b)

(c)


68

-20

-10

0

10

20

0 0.005 0.01 0.015 0.02

AC m

ain

curr

ent [

A]

0

4

8

12

16

20

0 0.0025 0.005 0.0075 0.01

time [s]

PFC

curr

ent [

A]

0

4

8

12

16

20

0 0.001 0.002 0.003 0.004

time [s]

Cur

rent

[A]

Fig. 6-12: AC main current (a), Boost current (b), in the case of single PFC

operating mode; active filtering principle illustration (c).

(a)

(b)

main PFC current

filtering PFC current

(c)


69

In the fig. 6-13 is shown the heat conduction path from a region in a generic silicon device to the ambient, in this figure is also reported the stationary thermal equivalent circuit. The total thermal resistance from the junction to the ambient (ja) is given by:

THja THjc THcs THsaR R R R= + +

The resulting junction temperature, assuming a power dissipation Pd is:

( )j d THjc THcs THsa aT P R R R T= + + +

in analogy with electric circuits. If there are parallel paths for heat flow, then the thermal resistances are combined in exactly manner as electrical resistors in parallel. Fig. 6-13: Steady-state heat flow and thermal resistance in a multiple layer structure including a (a) heat sink and (b) an equivalent circuit based on thermal resistance.

(a)

Chip Tj

Case Tc

Ambient temperature Ta

Isolation pad

Heat sink Ts

(b)

junction

case sink

ambient Rthjc Rthcs Rthsa

Tj Tc Ts Ta P

(6-1)

(6-2)


70

Manufacturers of power devices put great emphasis on keeping the thermal resistance as economically low as possible. This means keeping the length of all heat flow as short as possible, it also means that the cross sectional area should be as large as possible consistent with other design requirements such as minimizing parasitic capacitance. The package should be made of material with high thermal conductivity. In high power device, the package may be mounted on a heat sink that is either air cooled or even water cooled. With these types of efforts, it is possible to achieve junction to case thermal resistance, RTHjc, of less than one degree centigrade per watt.

In our case the power switches have been mounted on a Meccal® P250 40A (length: 270 mm) extruded heat sink and operating with no forced air. By using the heath sink characteristic, the R

TH,n value has been determined. In fig. 6-14 a

thermal image of the tested circuit working in single boost mode (the filtering PFC is disabled) is shown. As it is possible to see the power device temperature reaches 58°C while the temperature of the same device, working in dual boost mode and at the same operating condition (current ripple, reference current amplitude and DC bus voltage) is 47°C (see fig. 6-15). In both the cases the ambient temperature is 27°C. The dissipated power has been determined by taking into account of thermal equivalent circuit of the global system composed by both the power switches and the chosen heat sink. The PFC global losses, evaluated during the test of fig. 6-11, (converter operating in dual boost mode by using the proposed control scheme) are 57W. Instead, the global power losses (switching and conduction power losses) when the PFC converter works in single boost mode are 89 W (test shown in fig.6-12a,b). In fig. 6-16 is reported the system thermal characteristic where, in graphic manner, is highlighted the difference, in terms of the global power losses, in the case of dual boost PFC operating mode and in the case where a single PFC is working.


71

Fig. 6-14. Thermal image of the tested circuit working in single boost mode.

Fig. 6-15. Thermal image of the tested circuit working in dual boost mode.


72

0

20

40

60

80

100

0 10 20 30 40 50 60 70

Temperature [°C]

Glo

bal p

ower

loss

es [

W]

Fig. 6-16: System thermal characteristic. This means that a total losses reduction of 36% (main and filtering switching and conduction losses) has been obtained. The results confirm the validity of the proposed PFC scheme.

Dual boost PFC

Classical PFC

Chapter 7. Dual Boost PFC − SRS for elevators −

73

CHAPTER 7

HIGH PERFORMANCES SUPERCAPACITOR RECOVERY SYSTEM INCLUDING POWER

FACTOR CORRECTION (PFC) FOR ELEVATORS 7.1 Introduction Recent residential applications of electrical drives have to be characterized by high performances in terms of efficiency and compliance to international standards, as already mentioned in the previous chapters. In particular, in the elevator field, the market requires apart from the respect of the above standards both an increase of the drive efficiency and a reduction of the maximum power demand from the utility. The achievement of the above targets deeply influences the structure of the required conversion system. In particular, an interface circuit which performs the power quality control and at the same time increases the drive efficiency has to be used. Starting from the power quality control the use of front-end inverter allows easily to achieve power quality control [31]-[39]. This solution allows eliminating the brake resistor, but it often does not offer a real economic advantage for the end user because many utilities do not permit to capitalise the savings due to the energy recovery. An interesting alternative solution can be represented by the use of two different circuits: a Power Factor Correction (PFC) [40]-[48] for the power quality control and a supercapacitor energy storage system to both increase the motion system efficiency and at the same time eliminate the brake resistor. Besides this solution can be easily used to control the power demand from utility and consequently reduce the cost both of the utility connection and of the kWh. The use of supercapacitors in the electrical drive field is not new [49]-[54]. As it is well-known, supercapacitors represent a valid storage solution with an energy density which is more than 100 times the one of a standard capacitor. Thanks to their characteristics, they can be used to increase the overall drive efficiency. In particular, energy can be stored during breaking operations and used during motor ones with a reduction of the energy absorbed from the mains. It is important to underline that, even if standard lead acid batteries have an energy


74

density at least 10/15 times more than supercapacitors, the lasts present better performances in terms of specific power, with the advantage of a high charge-discharge efficiency (0.85¸0.98) and more than 500.000 life cycles without performance deterioration.

7.2 Conversion system description In fig. 7-1 the supercapacitor recovery system including a classical PFC scheme, is shown. However, the use of a classical PFC circuit introduce an increases of the overall switching losses and, therefore, a reduction of the system efficiency. To limit this problem a solution based on the adoption of a dual boost PFC scheme, shown in fig. 7-2, is proposed. This scheme is composed by two classical PFC working in parallel and controlled in order to obtain a switching losses reduction, and, at the same time, high quality currents, as widely described in the previous chapters. Fig. 7-2 shows the proposed conversion system, which is composed by a diode rectifier, a dual PFC circuit and a buck-boost converter used to interface the supercapacitor recovery system. Fig. 7-1: SRS including a classical single boost PFC.

C DCv

outvacv

Ci

di

pfci

pfcL pfcD

pfcT

SCv

Supercapacitors recovery system.

Cv

bi

1bT 1bD

2bT2bD

bL bR

bC


75

Fig. 7-2: SRS including the proposed dual boost PFC. The mathematical formulation of the PFC circuit has been already and widely done in the chapter 4. The control can be easily performed by using, for both the PFC circuits, an hysteresis current control strategy or by using a predictive current control based on the step-by-step integration of the dual boost converter voltage equations. In the case of topology shown in fig. 7-1 a predictive control algorithm can be carried out by simply solving step by step to respect the boost current the voltage equation of the well known single PFC boost topology. 7.3 Supercapacitor Recovery System Always with reference to fig.7-2, the mathematical model of the energy recovery circuit can be expressed as a function of switches Tb1 and Tb2 status. In particular, by introducing the buck-boost commutation function as follows [55]:

10bbf ⎧

= ⎨⎩

if Tb1=1 (switch on) Tb2=0 (switch off) if Tb1=0 (switch off) Tb2=1 (switch on)

(7-1)

CDCv outv

pfcmibtoti

acv

pfcmL

pfcfL

pfcmD

pfcfDpfcfi

pfcmT pfcfTbi

SCv

Supercapacitors recovery system

sCi

1bT 1bD

2bT2bD

bL bR

bC


76

Fig. 7-3 : proposed control scheme. the supercapacitor recovery circuit mathematical model become:

( ) ( ) ( ) ( )sc bb d b sc b scdv t f v t R i t L i tdt

− = +

Where, obviously, in order to avoid short circuit, Tb1 and Tb2 cannot be set on at the same time. 7.4 PFC buck-boost control algorithm The proposed control algorithm is based on the power balance of the overall system. By using the notation of fig. 7-2, the instantaneous input power is:

( ) ( ) ( )b b bp t v t i t=

If both the diode rectifier and the PFC losses are neglected, rel. (7-3) becomes:

( ) ( ) ( ) ( ) ( ) ( )b b b d btot pfcp t v t i t v t i t p t= = =

*( )dv t

( )dv t( )dcv t

( )di t( )dP t

*p fci+

-

0

1( ) ( )

pT

d

p

p t d tT

⋅∫

( )d pP nT

1

gv

pfci

compi

,maxpfci

*boosti

*bucki

*sci

g

sc

vv

+-

+

+

+

+

(7-2)

(7-3)

(7-4)


77

The instantaneous power injected by the supercapacitor buck-boost converter and the one absorbed by the drive are, respectively:

( ) ( ) ( )b d bp t v t i t=

( ) ( ) ( )d d dp t v t i t=

while the instantaneous power shared by the filtering capacitor C is:

( ) ( ) ( )c d cp t v t i t=

where: 1( ) ( )d cv t i t dtC

= ∫

A further simplification can be achieved by considering the mean values of the above quantities over a period Tp equal, for example, to 10ms. In this case, the power balance within a generic period [(n-1)Tp, nTp] becomes:

( )

( 1) ( 1)

1 1( ) ( ) [ ( )( ( ) ( ) ( ))]p p

p

P P

nT nT

d nT d d d tot b Cp pn T n T

P v t i t dt v t i t i t i t dtT T

− −

= = + + =∫ ∫

( ) ( ) ( )P P Ppfc nT b nT C nTP P P= + +

At this point, if the following condition is verified:

( ) ( ) ( )p p pd nT pfc nT b nTP P P= +

the voltage across the DC-bus capacitor C is kept constant. To achieve this, the control algorithm depicted in fig. 7-3 is used. In this scheme, the magnitude of the PFC input current: Fig. 7-4: Dual boost PFC control algorithm

(7-5)

(7-6)

(7-7)

(7-8)

(7-9)

*pfci

-

+

-

+

ib1

ib2

eb bf

bm

T1

T2


78

1 2pfc b bi i i= +

which represents the network current, is determined by using the (7-6). In particular, in normal operating conditions, i.e. when the load power is smaller than the maximum network power Pmax, the ipfc current is evaluated by imposing:

( ) ( )p Ppfc nT d nTP P=

If the load power request exceeds the maximum network power, the supercapacitor subsystem supplies the required exceeding power, in order to limit the input power below Pmax. This task is achieved by means of a current control. By indicating with ipfc,max the input current, corresponding to Pmax, the proposed control enables the supercapacitor boost converter each time the load current is greater than ipfc,max. In particular, the current exceeding this value ipfc,max is used as reference for the supercapacitor boost converter (i*

boost of fig. 7-3). In the same way, if the ipfc current is negative, it is used as reference for the supercapacitor buck converter (i*

buck of fig. 7-3), in order to recharge the supercapacitor bank. However, to take into account also the converter power losses, an additional PI controller on the DC bus voltage is added. The compensation current icomp allows to keep constant the DC bus voltage. 7.5 PFC Modulation algorithm Starting from the amplitude of the total PFC current, evaluated by using the control scheme of fig. 7-3, the instantaneous reference PFC current can be determined by using a classical zero crossing detection scheme. The proposed double boost PFC circuit, shown in fig. 7-2, allows to greatly reducing the switching losses if the following strategy is adopted:

use of two different switching frequency for both the first boost PFC circuit (main PFC) and the second one (filtering PFC);

control the filtering PFC in order to perform an active filtering of the main PFC current.

(7-10)


79

The above described strategy for the switching losses reduction is not new and it is described in [56]-[59] with reference to a three phase VSI (Voltage Source Inverter). Another interesting example of multiple PFC circuit is described [60] where two or more complete PFC circuit (including the diode rectifier) are connected in parallel. It has to underline that the proposed strategy, differently from the one described in [52], perform the active filtering directly on the DC side of the diode rectifier. The used control algorithm is derived from the one described in the chapter 4 and is shown in fig. 7-4. To perform a current control of the supercapacitor recovery system, equation (7-2) can be integrated step by-step and the modulation function fbb can be carried out as follows:

( ) ( ) ( ) ( 1)

( 1)( )

( )s s s s

s

s

bsc nT b sc nT sc nT sc n T

sbb n T

d nT

Lv R i i iTf

v

−

+

− − −=

7.6 Simulation and experimental results The proposed control scheme shown in fig. 7-3 has been deeply tested in simulation for a preliminary validation. In particular, a complete simulation of both the power electronics system (converters and drive) and the mechanical elements has been arranged. In tab. I all the parameters of the simulated plant are described. Besides, the maximum main power has been limited to 3kW. The simulated elevator is equipped with a gearless PM (Permanent Magnet) brushless machine with a mechanical rated velocity of 7 rad/s which correspond to an elevator velocity of 1m/s. The imposed elevator mechanical transient is shown in fig. 7-5 while fig. 7-6 shows the mechanical power fed by the drive. As fig. 7-6 and fig. 7-7 shown, the mechanical power became greater than 3kW; hence, the supercapacitor recovery system has to provide the energy represented by the gray area of fig. 7-7 in order to limit the main power to 3kW.

(7-11)


80

Fig. 7-5: Elevator mechanical transient.

Fig. 7-6: Elevator mechanical power.

Fig. 7-7: Power balance during the transient of fig. 5 drive power (a);

main power (b); supercapacitor current (c).


81

The proposed control algorithm provides the necessary power, as clearly shown in fig.7-7, where the source power and the supercapacitor power are respectively shown. In fig. 7-8 the supercapacitor voltage is reported, here, in particular, it is possible to see how the supercapacitor voltage decreases during the elevator motoring step and increases during the braking.

Fig. 7-8: Supercapacitor voltage.

Several tests has been performed with different values of both the hysteresis band bf and bm. In fig. 7-9 a comparison with the classical PFC scheme of fig. 7-1 is proposed.

Fig. 7-9: Current ripple vs. switching losses: proposed dual boost PFC (a); classical PFC current (b).


82

In particular the switching losses vs. the current ripple of the proposed dual boost PFC is compared with the one of a single boost PFC. In order to obtain different current quality a variation of the hysteresis band has been performed. In particular for what concern the proposed dual boost PFC a fixed value of bm (5A) and a variable filtering hysteresis band (0.75A <bf< 1.5A) has been used. The experimental results fully confirms the simulated tests. Fig. 7-10 shows a detail of the proposed dual boost PFC currents where the amplitude of the main PFC current is 1.6 A and the amplitude of the filtering current is 0.6 A. In fig. 7-11 the heat sink temperatures of both the proposed dual boost PFC and of the classical single boost PFC respectively are shown.

Fig. 7-10: Detail of main PFC current (a); main PFC modulation signal (b);

filtering PFC current (c); filtering PFC modulation signal (d).

Fig. 7-11: Heat sink temperatures.


83

Motor parameters Pole pairs 16 Nominal torque 800 [Nm] Rated current 12.5 [A]

Elevator parameters Velocity 1.0 [m/s] Maximum load 800 [Kg]

Supercapacitor Cell capacitance 4.7 [F] Cell voltage 2.5 [V] Series connections (ns) 48 Parallel connections (np) 2 Total capacitance 0.2 [F] Bank voltage 100 [V]

Tab. I: Parameters of the simulation and experimental set-up.


84

Chapter 8. Conclusions and future developments

85

CHAPTER 8

DISCUSSIONS This chapter will summarize the results obtained in the previous chapters and will discuss possible future developments of the proposed dual boost PFC architecture, in industrial and residential applications. At last will discuss also some possible improvements to the single PFC converter topology.

8.1 Experimental results In the chapters 5 and 6 two novel applications of the active filtering approach have been proposed. Both the approaches are based on the combination of two PFC converters feeding an high power load. In both the cases the active filtering approach is used to compensate the effects due to low operating switching frequency of main boost converter that mainly feeds the high power load. The improvements introduced by the proposed solutions are a reduced switching losses and an improved quality of the AC line current. Simulated, chapter 5, and experimental tests, shown in the chapter 6, confirm the feasibility of the proposed approaches. In particular, by using the proposed controls approaches , a not negligible reduction of the power device global losses is achieved. The thermal images shown in the chapter 6, in particular, show the overall improved efficiency respect to classical PFC topology. By adopting the current hysteresis control (FPGA implementation) or the predictive control strategy (DSP/Microcontroller implementation) in the case of single PFC architecture the power device is more stressed respect to the adoption of the proposed control strategies. The comparison of the proposed control solutions respect to similar single PFC configurations obviously have been made by considering that the operating conditions in both the cases are the same. The systems work with the same AC line voltage, the same load conditions and with the same AC current line ripple.


86

The choice of control algorithm, current hysteresis control scheme or predictive control strategy, depends by the choice of the control unit in order to perform all control and diagnostics tasks. The FPGA devices, for example, are well suitable to implement a current hysteresis control scheme. The FPGA devices, as well known in the literature can execute all the requested tasks in very small execution time Ts respect to a classical microcontroller or DSP. The FPGAS offer the stability of a typical digital implementation on a standard microprocessor and the performances comparable to an analog implementation. As well known the digital systems have the following fundamental properties [61]:

• Insensitivity to environment. Digital systems, by they nature, are considerably less sensitive to environmental conditions than analog systems. For example, an analog circuit’s behaviour depends on its temperature. In contrast, digital system’s operations does not depend on its environment – whether in the snow or in the desert, a digital system delivers the same response.

• Insensitivity to component tolerances. Analog components are manufactured to particular tolerances – a resistor, for example, might to be guaranteed to have a resistance within 1 percent of its nominal value. The overall response of an analog system depends on the actual values of all the analog components used. As a result, two analog systems of exactly the same design will have slightly different responses due to slight variations in their components.

In the chapter 7, a novel supercapacitor recovery system combined with a PFC (Power Factor Correction) circuit is proposed. The aim of the proposed solution is to increase the overall drive efficiency and, at the same time reduce the maximum input power coming from the main. This solution is particularly indicated for motion systems, such as elevator plant. Besides, a predictive control algorithm has been proposed, which allows to perform a high performances power flow control between the network and the storage unit. All the simulated and experimental results confirm the validity of the proposed approach.


87

8.2 Future developments In this paragraph will be reported only few examples of the possible future developments of the research activity reported in this work. The proposed PFC structures could be used and/or integrated in other power electronic systems, as an UPS for example. The following solution could be adopted: Fig. 8-1: Basic scheme of an hypothetic UPS based on the proposed dual PFC

architectures. This configuration operates as dual PFC active filter when the AC line voltage is present and its behaves as dual boost active filter when a black out happens. The adopted control strategy, step by step, detects the AC line voltage presence, in the negative case the Tbat switch will be closed and the power structure works simply as dual boost converter. In both the cases the active filtering approach is adopted. When the AC line voltage returns the adopted control strategy provides to restore the normal dual PFC filtering operating mode. In the following an oscilloscope screenshot shows all the system currents when the system works in DC mode.

C

Control strategy

Inverter DC bus

pfcmT

bati

REFVbatD

batT

acv DCv

Ci

pfcmL

pfcmi

pfcmD

outv

outvpfcmi

batv

pfcfT

pfcfL

pfcfi

pfcfD

pfcfi

Lr


88

Fig. 8-2: Experimental results: detail of main boost current (a), filtering current (b) and total battery pack current (c). Improvements could be made also to SRS (Supercapacitor Recovery System) discusses in the previous chapter by introducing the management of a battery pack in order to provide energy to system when the AC line supply fails or when the network is not capable to satisfy the energy requirement of an elevator plant, for example. The energy storage is mainly composed by supercapacitor bank, an added battery pack can be used in order to increase the motion system flexibility. The same energy storage system can be also used in order to reduce the power demand from the utility, and consequently to reduce the cost of the utility connection. In particular, the supercapacitor bank allows to feed short-time peak power during load transient, avoiding the batteries to be overcharged. In this way, the batteries life is longer and the system performances increases. The supercapacitor voltage adaption circuit is made, as already mentioned, by a buck-boost converter adoption, and its control algorithms is optimized not only for increasing the system efficiency, but also to control the instantaneous power at the mains and from the batteries, according to the PFC control algorithm.

(a)

(b)

(c)


89

In the following figures are reported the simplified schemes of the proposed solution either in the case of single PFC stage is used and in the case where a dual PFC architecture is adopted. Fig.8-3: Proposed energy conversion management scheme. Fig. 8-4: Proposed energy conversion management scheme, based on dual PFC architecture. The basic control scheme reported in fig.8-4 represents, clearly, the evolution of the control strategy discusses in the chapter 7. The proposed control schemes based on a multiple storage systems, in particular the topology based on the SRS, could be implemented by using a FPGA device in order to manage the PFC structure and a DSP for the management of the

C DCv outv

pfcmibtoti

acv

pfcmL

pfcfL

pfcmD

pfcfDpfcfi

pfcmT pfcfTbi

SCv


sCi

1bT 1bD

2bT 2bD

bL bR

bC

Batteries system batLbatR

batD

btotibatv

C DCv

outvacv

Ci

di

pfci

pfcL pfcD

pfcT

SCv


Cv

bi

1bT 1bD

2bT2bD

bL bR

bC

Batteries system

batLbatRbatD

batTbatv


90

others power device used in the system. In order to improve the overall system performances, at present, is developing a solution that provide only a FPGA device in order to perform all the requested tasks, control algorithm and diagnostic functions, without the usage of an additional control unit such a µP. Improvements, in terms of switching power losses, could be made also by adopting the classical single PFC converter topology. In fact, at first impact, a possible improvement could be done by adopting a variable switching frequency control strategy in function of the of the sampled instantaneous AC line/boost current. Being the switching power losses a quasi-linear function of the switch current and commutation frequency, a linear law can be adopted in order to calculate the switching frequency fC to be imposed on the base of the sampled instantaneous value of the AC line or boost current The switching frequency could be limited between a minimum value fC,min and a maximum value fC,max , chosen with reference to the considered application and to the power devices manufacturer suggestions. In other word when the amplitude of the current is high, a lower switching frequency could be selected; on the contrary, when the amplitude of the current is low higher switching frequencies could be selected. This solution could be adopted only if a predictive control strategy is used. Another way to improve the performances of a single PFC converter is by using a soft switching technique as Zero Voltage Switching (ZVS) one. As well known a ZVS technique as suitable for high frequency converters in contrast with the Zero Current Switching (ZCS) that is not capable to solve the problem of high switching loss due to capacitive turn-on, therefore, its is suitable for converters operating at low switching frequency. By creating a ZVS condition for the device turn on, the switching losses due to the discharging of junction capacities are eliminated [62]. The basic principle of a ZVS or ZCS technique is that to allow the used power device to perform a switching operation with, almost theoretically, with a null power losses. The major difficult of these techniques is they are strongly depended to applied load to power converter, in order to implement a ZVS or ZCS technique more complex algorithms are needed to develop respect to the well known solution widely reported in the literature. The proposed ZVS technique has been developed by referencing to following principle scheme:


91

Fig. 8-5: Basic scheme of a resonant boost converter operating in ZVS mode. where the Lr and Cr are the added components in order to realize the desired resonance operating mode of the switch T. Several papers are found in the literature where the authors works on the basis of the particular operating modes that in some circumstances are not satisfies. By removing these hypothesis and by referencing at following scheme: Fig.8-6: Equivalent circuit of resonant ZVS boost converter. it is possible to carry out the following set of differential equations can be solved respect to the terminal voltage of the used power switch.

Lb

bv oVCr

Lr Rb Rr

cv

ci

Libi

bb b b b c

Lc r L r O

b r L

cc

div R i L vdtdiv R i L Vdt

i i idvi Cdt

= + + = + + = + =

Lb

C DCv outvT

D

Rload Cr

Lr


92

The unique hypothesis is that the output voltage of the converter is constant, this is true for the most industrial applications. A simplified mathematical formulation of a ZVS boost converter can be made by assuming constant also the boost current in a generic sample time Ts. In the last case the above system of differential equations can be reduced by a degree. The developed ZVS technique has given good results in the open loop mode of the controlling of power converter, the difficult on a practical industrial application is due on the closed loop mode implementation. A possible and low cost hardware platform suitable to perform the last two described control strategies on the classical single PFC architecture could be the TI TMS320F2812 DSP. This platform is capable to execute a control strategy code with a variable execution time Ts evaluated step by step by the same control algorithm executed every Ts. This operation can be performed by setting in proper manner the timer registers of one of two Event Manager A/B blocks present on the mentioned DSP, for furthermore details see the DSP datasheet or the appendix B. This operation ensure that a periodic task associated to a generic timer interrupt service routine is executed with a variable execution time Ts as requested by the above proposed control strategies. 8.3 Conclusions The improvements introduced by the proposed solutions is mainly a reduced global power losses respect to the single boost PFC at same operating conditions. At same time a better quality of the AC line current is achieved according to the present regulations in terms of harmonic pollution. A reduction of the power losses could be obtained also adopting the single PFC topology by operating with a variable switching frequency proportional to the value of the absorbed current. Another possible way to reduce the power device losses is by using a ZVS technique.

Appendix A

93

APPENDIX A

HALL EFFECT TRANDUCERS MAIN FEATURES AND

BASIC MOUNTING CONSIDERATIONS A.1 Introduction In this appendix will be discusses the fundamentals steps of the Hall effect transducers usage. They have been used in the experimental tests described in the chapters 6 and 7. The used Hall effect transducers are:

• LEM® LA 25 NP used for the current sensing; • LEM® LV 25 P used for the voltage sensing;

in the following also basic principle mounting schemes are reported. The above mentioned Hall effect transducers have been suitable for all the performed experimental tests, in fact, the maximum value of the acquired currents has been 15A and the maximum voltage value has been 470V on DC bus of the used converters. Their characteristics are available from the LEM® manufacturer datasheet (Available at LEM® website, for example). A.2 LA 25 NP Hall effect current transducer The chosen transducer can be used to acquire currents until 25A, the max acquired current depends by the connection between pins 1..5 and 6..10 as depicted in the datasheet. The output voltage is proportional to primary side sensed current.

Fig. A-1: Basic scheme of a current transducer mounting.

1-5

6-10

+

+

- M

VOut

+15V

0V

-15V

Rm

Out

In

1 2 3

LA 25 NP

TL 082

-

Appendix A

94

By connecting together the pins 1..5 and together the pins 6..10 and by mounting a precision resistor Rm at secondary side of the transducer with a value of 301 Ω, the instrumental constant [Output voltage-Input current ratio] is equal to 3.3226. The determination of this value has been made on the basis the following considerations:

11000nK = depends on the connection mode of 1..5 and 6..10 power pins.

therefore:

out m n PV R K I=

where: Ip is the sensed current, if Ip=1A the output voltage is 0.301Ip,

the ratio of the built transducer system is 1 3.32260.301aK = = .

A.3 LV 25 P Hall effect voltage transducer The chosen transducer can be used to sense voltages until 470 V. The range of the sensed voltage depends by the choice of primary Rp and by secondary Rm precision resistors respectively. The output voltage is proportional to primary side measured voltage, the resistors have chosen by referencing always to datasheet guidelines. Fig. A-2: Basic scheme of a voltage transducer mounting. The primary resistor of 47K is chosen in order to limit the primary side current to 10mA, on the basis of the datasheet specifications, and by choosing a Rm resistor value of 301Ω, fig.2, it is possible to sense voltages in the range ±470V. The instrumental constant [Input voltage-output voltage ratio] is equal to 62.46.

(A-1)

+HT

-HT

Rm

Out

In Rp LV 25 P

Vp

+

1 3

TL 082

- 2 VOut

+15V

0V

-15V

+

M -

Appendix A

95

The determination of this value has been made on the basis the following considerations:

25001000nK = and Rm=301 Ω

the output voltage is given by;

m n pout

p

R K VV

R=

where Vp is the sensed voltage, if Vp=1V the output voltage is Vout=0.016Vp, the

ratio of the built transducer system is 1 62.460.016vK = = .

In both the above figs is present the operational amplifier TL082, mounted as voltage follower, that acts as a buffer.

(A-2)

Appendix A

96

Appendix B

97

APPENDIX B

HIGH PERFORMANCES DUAL BOOST PFC CONTROL UNITS

− MAIN FEATURES − B.1 Introduction In this appendix will be illustrated the mean features of the control units used to implement both the versions of Dual Boost PFC converter topology. For furthermore details of the used control units it’s recommended to visit the following websites:

• http://www.altera.com in order to obtain a complete description of Cyclone I family FPGA devices [Dual Boost PFC : Current hysteresis control scheme].

• http://www.ti.com in order to obtain a complete e detailed description of TMS320F2812 DSP device [Dual Boost PFC : Predictive control strategy].

B.2 ALTERA® Cyclone I EP1C6Q240C6 The Cyclone® device family offers the following main features:

• 2,910 to 20,060 Les; • Up to 294,912 RAM bits (36,864 bytes); • Supports configuration through low-cost serial configuration device; • Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards; • Support for 66 and 33 MHz, 32 and 64 bit PCI standard; • High-speed (640 Mbps) LVDS I/O support; • Up to two PLLs per device provide clock multiplication and phase

shifting;

Appendix B

98

In the application discussed in the chapter 6 a Cyclone® I EP1C6Q240C6 device has been used having the following main features:

Total logic elements: 5980; Total memory bits: 92160; Total available user pins for the I/O management: 185;

In particular the used FPGA device has mounted on a UP3 kit board having the following main features:

Powerful board for FPGA designs: o EP1C6Q240 (or EP1C6Q240) device; o EPCS1 configuration device; o Supports IP-based design both with and without a microprocessor;

Industry-standard interconnection: o USB 2.0-compliant (full & low speed); o Two RS 232 ports; o Parallel port (IEEE1284); o PS/2 port;

Memory subsystem: o 1 Mbytes of SRAM; o 2 Mbytes of FLASH; o 2 Kbytes of I2C PROM (expandable);

Multiple clocks for system design; JTAG configuration; Expansion headers for greater flexibility and capacity:

o 5V Santa Cruz Long Expansion Card Header provides 72 I/O pins for the development of additional boards (providing various functionality);

Additional user interface features: o One user-definable 4-bit switch block; o Four user-definable push button switches and one global reset switch; o Four user-definable LEDs; o One 16x2 character display LCD Module; o I2C real time clock;

Appendix B

99

B.3 TI® TMS320F2812 The main features of this 32 bit fixed point control unit are the following:

High-Performance Static CMOS Technology: o 150 MHz (6.67 ns cycle time); o Low power (1.8 V Core @135 MHz, 1.9 V core @150 MHz, 3.3 V I/O) design;

High-Performance 32 bit CPU (TMS320C28x): o Harvard bus architecture; o Fast interrupt response and processing;

On-Chip Memory: o Flash devices: up to 128K x 16 Flash; o ROM devices: Up to 128K x 16 ROM; o L0 and L1: 2 Blocks of 4K x 16 Each Single-Access RAM (SARAM); o H0: 1 Block of 8K x 16 SARAM; o M0 and M1: 2 Blocks of 1K x 16 Each SARAM;

External Interface (2812): o Up to 1M total memory; o Programmable wait states; o Programmable read/write strobe timing;

Three 32-Bit CPU-Timers; Motor Control Peripherals:

o Two Event Managers (EVA, EVB) compatible to 240xA devices; Serial Port Peripherals:

o Serial Peripheral Interface (SPI); o Two Serial Communications Interfaces (SCIs), Standard UART;

12-Bit ADC, 16 Channels: o 2 x 8 Channel input multiplexer; o Two sample-and-hold; o Single/simultaneous conversions; o Fast conversion rate: 80 ns/12.5 MSPS;

Up to 56 General Purpose I/O (GPIO) pins;

Appendix B

100

For the implementation of the control strategy described in the chapter 4 have been used:

4 A/D conversion channels; 1 CPIO pin for the current hysteresis control of the filtering PFC; 1 PWM output in order to manage the predictive control of main PFC; 1 Interrupt with a Ts=50μS based on Timer1 of EVA [Event Manager A];

the code, either in the case of single PFC converter and either in that of dual PFC converter management, has been written in ANSI C by using the TI® Code Composer Studio IDE development environment.

Appendix C − FPGA s_float24 math library

101

APPENDIX C

IEEE 754 STANDARD FLOATING POINT ARITHMETIC

FPGA MATH LIBRARY IMPLEMENTATION C.1 Introduction Although fixed point arithmetic may be usually employed in many numerical problems through the use of proper scaling techniques, this approach can become complicated and sometimes result in less efficient code than is possible using floating point methods. Floating point arithmetic is essentially equivalent to arithmetic in scientific notation to a particular base or radix. C.2 Storage layout description This standard [63]-[64] defines mainly four formats for floating-point numbers, of which two are commonly used (single and double). In single-precision numbers, there is a one-bit sign, 23 bits in the mantissa (an implicit 24th bit is the leading 1 in all mantissas, which is not stored), and the 8 bit exponent has a range from –126 to 127 with a bias of 127. In double-precision numbers, there is a 1 bit sign, 53 bits of precision in the mantissa (52 bits and one implied leading 1 bit), with an exponent that ranges from –1022 to 1023 with a bias of 1023. The following table shows the storage layout for single (32 bit) and double (64 bit) precision floating-point values, the number of bits for each field are shown (bit ranges are in square brackets):

Sign Exponent Fraction/Mantissa Bias

Single Precision 1 [31] 8 [30…23] 23 [22…00] 127 Double Precision 1 [63] 11 [62…52] 52 [51…00] 1023

Table I: IEEE 754 standard storage layout.


102

When the sign bit is 0 its denotes a positive number, 1 denotes a negative number. Flipping the value of this bit change the sign of the number. An exponent of zero means that 127 is stored in the exponent field. A stored value of 200 indicates an exponent of (200-127), or 73. For reasons discussed later, exponents of -127 (all 0s) and +128 (all 1s) are reserved for special numbers. In order to understand how the IEEE 754 standard works several examples are reported with reference to a single precision (32 bit) number. As above mentioned a floating point number is composed by three fundamental fields:

S E E E E E E E E F F F F F … F F F

Exponent field [8] Fractional part of Mantissa field [23] Fig. C-1: Bit word storage layout of a generic floating point number. A generic value “V” of a number represented by the 32 bit word may be determined as follows:

• if EXP=255 and f is nonzero, then V=NaN ("Not a Number") • if EXP=255 and f is zero and S is 1, then V=-Infinity • if EXP=255 and f is zero and S is 0, then V=Infinity • if 0<EXP<255 then the generic number can be represented in the form:

( 1) 2s eN f= −

with: 1

0( )2

nk

kf a k

−−

=

= ∑ ; 1.M f= and EXP e BIAS= +

• if EXP=0 and f is zero and S is 1, then V=-0 • if EXP=0 and f is zero and S is 0, then V=0

therefore:

(C-1)

(C-2)


103

Sign bit EXP field Fractional part Meaning 0 00000000 00000000000000000000000 0 1 00000000 00000000000000000000000 -0 0 11111111 00000000000000000000000 Infinity 1 11111111 00000000000000000000000 -Infinity 0 11111111 00000100000000000000000 NaN 1 11111111 00100010001001010101010 NaN

Table II: Special values provided by the IEEE 754 standard. The finite positive and finite negative numbers furthest from zero (represented by the value with 254 in the EXP field and all 1s in the fraction field) are ±(1-2-23)×2128 ≅ ±3.4028235×1038.

Sign bit EXP field Fractional part Meaning 0 10000000 00000000000000000000000 2=>+1*2128-127*1.0 0 10000001 10100000000000000000000 6.5 =>+1*2129-127*1.101 1 10000001 10100000000000000000000 -6.5 => -1*2129-127*1.101 * 00000000 00000000000000000000001 ±2-22*2-127=±2-149 * 00000001 00000000000000000000000 ±2-126≈±1.18*10-38 * 11111110 11111111111111111111111 ±(2-2-23)*2127≈±3.4*1038

Table III: Examples of IEEE 754 (32 bit) numbers representation. In general the exponent is biased by 1(2 ) 1N − − , where N is the number of bits

used for the exponent field. For a double precision floating number, where the bits of the exponent field is 11 the bias is given by 11 1(2 ) 1 1023− − = .

An example of non standard floating point number representation is given by the case of a generic number is stored in [65] a 24 bit width word, where the MSB is the sign bit, the following 7 bits represents the exponent field and the remainder bits (16) is the fractional part of the mantissa. In this particular case the bias is given by 7 1(2 ) 1 63− − = , this reduced floating point non standard representation

is particularly useful when the FPGA device is not sufficiently capable to implement one of the standard floating point number.


104

In the following is briefly described the basic formulation of the four basic elementary arithmetic operation: sum, difference, multiplication and division between two given numbers. At last is only reported the analytical formulation of trigonometric function based on the well known CORDIC [66] theory. The implementation of the FPGA math coprocessor IEEE 754 standard compliant has be done by using the VHDL language in order to remove the well known problem of the code portability. The choice of the VHDL language has been done in particular to carry out a optimized and flexible code. The sfloat_24 non standard floating point number library, at present, is still in development phase. A beta release has been already tested, giving good results, on the implementation on single PFC converter either with a current hysteresis control and either with a predictive control strategy, therefore on a FPGA device has been implemented also a “true” PI regulator in the same manner on equivalent μP implementation. By using a 24 bit floating point (sfloat24) arithmetic the loss of precision respect to the use of standard single precision number is not particularly significant in ordinary mathematical computational tasks, the significant limitation is due only by the reduced number range representation in the field of real numbers [ 189.2 10≈ ± ⋅ ] respect to standard floating point number representation.

C.3 Basic Arithmetic Operators C.3.1 Floating point Adder/Subtractor Given the following numbers:

• ( 1) 2 1.AS eAA AN f= − the value of eA in the exponent bit field is just

represented with AEXP eA BIAS= + and the mantissa as 1.A AM f= ;

• ( 1) 2 1.BS eBB BN f= − the value of eB in the exponent bit field is just

represented with BEXP eB BIAS= + and the mantissa as 1.B BM f= ;


105

The sum and/or difference can be expressed as:

A BR N N= ±

( 1) 2 1. ( 1) 2 1.A BS SeA eBA BR f f= − ± −

C.3.2 Floating point Multiplier Given two usual generic numbers NA and NB their product can be expressed as:

A BR N N=

2 1. 1.eA eBR A BR S f f+=

where

R A BS S XOR S=

REXP eA eB BIAS= + +

1. 1.R A BM f f= ⋅

The algorithm basically works on the well known exponents proprieties and on few bit shift operations. C.3.3 Reciprocal of a given number/ Floating point divider Given a number in the usual, already showed form its reciprocal is equal to:

1( 1) 2 1.S eR

f=

−

with:

REXP e BIAS= − + or 1REXP e BIAS= − − + if the fractional part of mantissa

field is not null in this case the mantissa is given by: 1

RMM

=

(C-10)

(C-11)

(C-3)

(C-4)

(C-5)

(C-6)

(C-7)

(C-8)

(C-9)


106

and the sign is the same of the input number. The operation of division between two given number as the product of the one of the given numbers and the reciprocal of the other number. In similar manner can be implemented the full divider, the implementation is based on the following equations:

( 1) 2 1.( 1) 2 1.

A

B

S eAA

S eBB

fRf

−=

−

R A BS S XOR S=

REXP eA eB BIAS= − +

1.1.

AR

B

fMf

=

The algorithm can carried out by exploiting the well known exponent proprieties and performing the division of two number mantissas in the similar manner as above shown. C.4 Trigonometric functions Often trigonometric functions are used in embedded applications, examples of this include the motion control field, filtering and waveform synthesis. For waveforms with few output points per cycle (for example one output point per degree) a lookup table will often suffice, instead for waveforms with many output points per cycle the lookup table approach is often unfeasible because of the large amount memory requirements. It would appear from the above that where many points are required on a waveform it would be more practical to compute points on the waveform in real time when required. This raises the question of how to compute trigonometric functions efficiently. Various methods exist. These include Taylor Series; various curve fitting algorithms and the CORDIC [66] (COordinate Rotation DIgital Computer) algorithm. The CORDIC algorithm often offers the most elegant solution to the problem, and it is astounding in its simplicity of implementation, efficiency and elegance.

(C-12)

(C-13)

(C-14)

(C-15)


107

The CORDIC algorithm provides an iterative method of performing vector rotations by arbitrary angles using only shift and adds. The algorithm, credited to Volder, is derived from the general rotation transform:

'

'

cos sincos sin

x x yy y x

= Φ − Φ

= Φ + Φ

which rotates a vector in a Cartesian plane by the angle Φ. These can be rearranged so that:

'

'

cos [ tan ]cos [ tan ]

x x yy y x

= Φ − Φ

= Φ + Φ

If the rotation angles are restricted so that tan( ) 2 i−Φ = ∓ , the multiplication by

the tangent term is reduced to simple shift operation. Arbitrary angles of rotation are obtainable by performing a series of successively smaller elementary rotations. If the each iteration i, is which direction to rotate rather than whether or not to rotate, then the cos( )iδ term becomes a constant,

because cos( ) cos( )i iδ δ= − . The iterative rotation can now be expressed as:

1

1

[ 2 ]

[ 2 ]

ii i i i i

ii i i i i

x K x y d

y K y x d

−+

−+

= ⋅ − ⋅ ⋅

= ⋅ + ⋅ ⋅

where:

1

2

1cos(tan 2 )1 2

1

ii i

i

K

d

− −

−= ≈

+= ∓

Conversion between this angular system and any other can be accomplished using a look-up. A better conversion method uses an additional adder-subtractor that accumulates the elementary rotation angles at each iteration. The elementary angles can be expressed in any convenient angular unit. Those angular values are supplied by a small lookup table. The angle accumulator adds a third difference equation to the CORDIC algorithm:

(C-16)

(C-17)

(C-18)

(C-19)


108

11 tan (2 )i

i i idϑ ϑ − −+ = − ⋅

The CORDIC equations are:

1

1

11

2

2

tan (2 )

ii i i i

ii i i i

ii i

x x y d

y y x d

i dϑ ϑ

−+

−+

− −+

= − ⋅ ⋅

= + ⋅ ⋅

= − ⋅

where 1id = − if 0iϑ < , +1 otherwise.

(C-20)

(C-21)

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About the author

In collaboration with the professors A. Del Pizzo and C. Attaianese he developed two interactive simulation software, under Windows platform, concerning the DC and AC electrical drives. Since 1996 he works in collaboration with Prof C. Attaianese at Department of Automation, Electromagnetism, Computer Science and Industrial Mathematics of University of Cassino (Italy). He was involved, from 1997 to 1998, in the research activity concerning the development of robust control algorithms on DC motors. He, afterward, from 1999 to 2005, was involved in several research activities concerning the development of new vectorial control strategies of Induction Motors and Permanent Magnets Motors and their implementation on DSP platforms. He also was involved, in the year 2002, for the development and consequent µP implementation of an algorithm concerning the “on line” electrical parameters identifications of Induction Motors. He is working since 2006 in the field of Power Electronic, in particular for the development of new predictive control strategies concerning the Active Filters. He is the author of several scientific publications concerning the above mentioned research activities.

Fernando Parillo was born in Casagiove, Italy, in 1964. He received the Dr. Eng. degree in Electrical Engineering from the University “Federico II” of Naples in 1993. The title of his experimental thesis in Electrical Machines was “Electrical Parameters Identification of Asynchronous three-phase Motors ". He worked since 1993 to 1995 at the Department of Electrical Engineering, University of Naples, then headed by Professor E. Pagano.

dual boost high performances power factor correction (pfc ... xxi/tesi parillo... · dual boost...

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