January 2012 Doc ID 022507 Rev 1 1/22

AN4015Application note

Dual-BTL class-D audio amplifier demonstration boardbased on the TDA7498E

IntroductionThe purpose of this application note is to describe:

■ how to connect the TDA7498 demonstration board

■ how to evaluate the performance of the demonstration board using the electrical curves

■ how to avoid critical issues in the PCB schematic and layout of the TDA7498E

The TDA7498E represents a new generation of analog input class-D devices from STMicroelectronics and is housed in a PSSO36 package. It is able to deliver 160 W +160 W in stereo configuration with VCC = 36 V and a 4 Ω load(a).

Figure 1. TDA7498E demonstration board

a. All of the results and graphs included in this document are measured using Audio Precision equipment.

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Contents AN4015

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Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Test conditions and connections of the demonstration board . . . . . . . 5

2.1 Power supply and interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Schematic diagram and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Test curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Design guidelines for PCB schematic and layout . . . . . . . . . . . . . . . . 14

6.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.1 Main driver for the selection of components . . . . . . . . . . . . . . . . . . . . . 14

6.1.2 Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.3 Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AN4015 List of figures

Doc ID 022507 Rev 1 3/22

List of figures

Figure 1. TDA7498E demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2. TDA7498E demonstration board connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 3. TDA7498E schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 4. PCB layout - top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 5. PCB layout - bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 6. PCB layout - top and bottom sides plus components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 7. THD+N vs. power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 8. THD+N vs. frequency (ref = 1 W at 1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 9. DNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 10. FFT (0 dBr at 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 11. Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 12. Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 13. Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 14. Pout vs. VCC and THD level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 15. Snubber filter - solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 16. Snubber filter - solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 17. Dumping network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 18. Frequency shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 19. Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 20. Snubber network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 21. VCC decoupling electrolytic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 22. ROSC - component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 23. Filter capacitors for SVR, VREF, SVCC, VSS and VDDPW. . . . . . . . . . . . . . . . . . . . . . . . 19Figure 24. Input signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 25. Signal ground and power ground routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Overview AN4015

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1 Overview

The following terms used in this application note are defined as follows:

● THD+N vs. Pout: Total Harmonic Distortion (THD) plus noise versus output power

● THD+N vs. Freq: Total Harmonic Distortion plus noise versus frequency curve

● S/N Ratio: Signal-to-noise ratio

● DNR: Dynamic range

● FFT: Fast Fourier Transform Algorithm (method)

● XTalk: Channel separation L to R, or R to L channel crosstalk

The equipment used includes the following:

● Audio Precision 2722A + AES-17 filter + DCX+ AUX-0025 filter

● DC power supply

● Digital oscilloscope (Tektronix TDS5054B)

● Differential voltage probe (LeCroy AP031)

● Current probe (Tektronix TCP300)

Reference documents include:

● TDA7498E datasheet

● Schematic diagram

● PCB layout

● Test curves

AN4015 Test conditions and connections of the demonstration board

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2 Test conditions and connections of the demonstration board

2.1 Power supply and interface connection1. Connect PSU to the VCC terminal block

2. Connect the analog input cable to the RCA connectors on the demonstration board, the other side must be connected to a signal source such as the Audio Precision analog outputs or a DVD player

2.2 Output configurationThe TDA7498E demonstration board has been configured in 2-channel BTL output.

2.3 ConnectionsThe board terminals (top view of demonstration board) are visible in Figure 2.

Figure 2. TDA7498E demonstration board connections

Left Load Right Load

Analog input

Single-endedinput/differentialinput modeselection

Standby and mutecontrols

Gain selection

Schematic diagram and PCB layout AN4015

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3 Schematic diagram and PCB layout

Figure 3. TDA7498E schematic

AN4015 Schematic diagram and PCB layout

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Figure 4. PCB layout - top side

Figure 5. PCB layout - bottom side

Schematic diagram and PCB layout AN4015

8/22 Doc ID 022507 Rev 1

Figure 6. PCB layout - top and bottom sides plus components

AN4015 Electrical characteristics

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4 Electrical characteristics

Referring to Figure 3: TDA7498E schematic, the Left (L) and Right (R) channels are the output for a stereo configuration. VCC = +36 V, Gain 23.6 dB; Tamb = 25.5 °C; InputFreq = 1 kHz; RefLevel = 1 W (0 dBr), Load = 4 Ω (resistive dummy load).

Table 1. Electrical characteristics

THD+N vs. power Pout = 1 W 0.0555%

IOCP 12 A

SNRNo filter -74.3 dB

AW - filter -77.5 dB

DNRNo filter -94 dB

AW - filter -98 dB

Xtalk 1 kHz -85.9 dB

Test curves AN4015

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5 Test curves

Figure 7. THD+N vs. power

Figure 8. THD+N vs. frequency (ref = 1 W at 1 kHz)

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Red Solid 2 Anlr.THD+N Ratio Left Vcc=36V; Load=4ohm; 1kHz; Ch L1 3 Blue Solid 2 Anlr.THD+N Ratio Left Vcc=36V; Load=4ohm; 1kHz; Ch R

0.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5

%

1m 4002m 5m 10m 20m 50m 100m 500m 1 2 5 10 20 50 100 200W

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Red Solid 2 Anlr.THD+N Ratio Left Vcc=36V; 1W@1kHz; Ch L1 2 Blue Solid 2 Anlr.THD+N Ratio Left Vcc=36V; 1W@1kHz; Ch R

0.01

1

0.02

0.05

0.1

0.2

0.5

%

20 20k50 100 200 500 1k 2k 5k 10kHz

AN4015 Test curves

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Figure 9. DNR

Figure 10. FFT (0 dBr at 1 W)

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Red Solid 2 Anlr.THD+N Ratio Left Vcc=36V_1kHz_4 ohm; Ch L1 2 Blue Solid 2 Anlr.THD+N Ratio Left Vcc=36V_1kHz_4 ohm; Ch R2 1 Green Solid 2 Anlr.THD+N Ratio Left Vcc=36V_1kHz_4 ohm; Ch R - AW Filter2 2 Black Solid 2 Anlr.THD+N Ratio Left Vcc=36V_1kHz_4 ohm; Ch L - AW Filter

-80

-20

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

dB

-60 +0-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5dBr

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Red Solid 2 Fft.Ch.1 Ampl Left Vcc=36V; Ref: 1W@1kHz: Ch L1 2 Blue Solid 2 Fft.Ch.2 Ampl Right Vcc=36V; Ref: 1W@1kHz: Ch R

-150

+0

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr B

-150

+0

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dBr A

20 20k50 100 200 500 1k 2k 5k 10kHz

Test curves AN4015

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Figure 11. Crosstalk

Figure 12. Linearity

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Red Solid 2 S2C.Anlr.Crosstalk Left Vcc=36V; 1W; 4ohm; (Ch L on)1 2 Blue Solid 2 S2C.Anlr.Crosstalk Left Vcc=36V; 1W; 4ohm; (Ch R on)

-120

+0

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

dB

20 20k50 100 200 500 1k 2k 5k 10kHz

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 220

20.5

21

21.5

22

22.5

23

23.5

24Gain Linearity

Input Level [V]

Gai

n [d

B]

LeftRight

AN4015 Test curves

Doc ID 022507 Rev 1 13/22

Figure 13. Bandwidth

Figure 14. Pout vs. VCC and THD level

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Red Solid 2 Anlr.Level A Left Vcc=36V; 1W; Ch L1 2 Blue Solid 2 Anlr.Level B Right Vcc=36V; 1W; Ch R

-3

+1

-2.5

-2

-1.5

-1

-0.5

+0

+0.5

dBr B

-3

+1

-2.5

-2

-1.5

-1

-0.5

+0

+0.5

dBr A

10 50k20 50 100 200 500 1k 2k 5k 10k 20kHz

ColorSweep Trace Line Style Thick Data Axis Comment

1 1 Cyan Solid 2 Anlr.Level A Left Pout vs. Vcc; Load=4ohm; THD=1%2 1 Green Solid 2 Anlr.Level A Left Pout vs. Vcc; Load=4ohm; THD=10%3 1 Blue Solid 2 Anlr.Level A Left Pout vs. Vcc; Load=4ohm; THD=20%4 1 Red Solid 2 Anlr.Level A Left Pout vs. Vcc; Load=4ohm; THD=30%

20

200

40

60

80

100

120

140

160

180

W

+10 +40+12.5 +15 +17.5 +20 +22.5 +25 +27.5 +30 +32.5 +35 +37.5Vdc

Design guidelines for PCB schematic and layout AN4015

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6 Design guidelines for PCB schematic and layout

6.1 Schematic

6.1.1 Main driver for the selection of components

● Absolute maximum rate (input VCC supply): 40 V

● Bypass capacitor 100 nF in parallel to 1µF for each power VCC branch. Dielectric X7R is suggested.

● Coil saturation current must be compatible with the peak current of application

6.1.2 Decoupling capacitors

There are two different ways to use the decoupling capacitors:

● The decoupling capacitor(s) can be shared among channels; the layout must be designed to implement a "star route" for the VCC paths.

● One decoupling capacitor can be used for each channel. It is mandatory that each decoupling capacitor be placed as close as possible to the IC pins. This solution is implemented on the TDA7498E demonstration board.

6.1.3 Output filter

● Snubber network: the key function of a snubber network is to absorb energy from the inductive component in the power circuit (the output coils and the speaker). The purpose of the snubber RC network is to dissipate the unnecessary high pulse energy, such as a high voltage spike, in the power circuit which is dangerous to the system.

● Main filter (low-pass filter): The purpose of the main filter is to remove the carrier frequency (≈310 kHz) and to cut off the frequency higher than the audible range of 20 kHz. The LPF filter is implemented by a passive Butterworth topology. In order to have a clean and flat frequency response, it is mandatory to design the filter to fix the cutoff frequency a little bit above 20 kHz.

● Damping network: The purpose of the damping network is to avoid the high-frequency oscillation issue on the output circuit. When the load is disconnected from the amplifier, the frequency response of the main filter is not flat and there is the possibility of adding gain in a frequency band. The damping network also improves the THD performance. The damping network can also avoid the inductive effect of the PCB tracks when the system is working at high frequency with PWM.

AN4015 Design guidelines for PCB schematic and layout

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Snubber filter

The snubber circuit must be optimized for the specific application. Starting values are 330 pF in series to 22 ohm. The power dissipation of this network (resistor) depends on the power supply, frequency and capacitor values using following formula:

This power is dissipated on the series resistance.

Figure 15. Snubber filter - solution 1

To increase the efficiency, it is possible to use two equal snubber networks toward GND. In this case, the formula to evaluate power is:

This power is dissipated on the resistance.

Figure 16. Snubber filter - solution 2

P C f 2 V⋅( )2⋅ ⋅=

C126330p

R4422

INxA

INxB

P C f 2 V2⋅ ⋅ ⋅=

C127330p

C130330p

R4522

R46

22

INxA

INxB

Design guidelines for PCB schematic and layout AN4015

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Dumping network

The C-R-C is a dumping network. It is mainly intended for high inductive loads and for common-mode noise attenuation.

Figure 17. Dumping network

PWM output frequency shifting for AM band radio sensitivity improvement

Using a logic control signal (FS) from MCU or from a DSP (3.3 V) it is possible to modify the PWM output frequency.(b)

Figure 18. Frequency shift

b. For the PWM frequency calculation formula please refer to the datasheet.

AN4015 Design guidelines for PCB schematic and layout

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6.2 Layout● Solder 100 nF and 1µF bypass ceramic capacitors as close as possible to the related

IC pin

● To avoid the effect due to the parasitic inductive coil generated by the copper wires, it is suggested to use the ceramic capacitor to balance the reactance. It's mandatory to place the ceramic capacitor as close as possible to the related pins. The distance between the capacitor to the related pins is recommended to be within 5 mm.

Figure 19. Decoupling capacitors

● Solder the snubber networks as close as possible to the related IC pin. A high level spike may occur if the snubber network is placed too far from the pins. It's recommended that the distance from the snubber network be within 3 mm which takes into consideration the width of the copper wire.

Figure 20. Snubber network

Ground pin and Vcc pin of100 nF and 1μF capacitorsshould be connected to the related IC pin directly

Snubber network

Design guidelines for PCB schematic and layout AN4015

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● Use electrolytic capacitors first to separate the VCC branches. A "star route" for the VCC supply is suggested to avoid interference between the channels such as when one channel is idle while the other channel is working with a full load. In applications with high output power, another approach is to filter the two channels separately. This solution is implemented in this demonstration board.

Figure 21. VCC decoupling electrolytic capacitors

● ROSC network: Place the RC filter for the ROSC pin close to the IC

Figure 22. ROSC - component placement

R-C network forROSC

AN4015 Design guidelines for PCB schematic and layout

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● Place the filter capacitors for SVR, VREF, SVCC, VSS and VDDPW close to the IC.

Figure 23. Filter capacitors for SVR, VREF, SVCC, VSS and VDDPW

● Input signal routing

Figure 24. Input signal routing

Filter capacitors forVREF, SVCC andVSS

Filter capacitorsfor VDDS andVDDPW

Filter capacitor for SVR

Design guidelines for PCB schematic and layout AN4015

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● Signal ground and power ground routing: the signal ground should be connected to the bulk capacitor negative terminal via a dedicated copper track; no vias must be present in the connection path.

Figure 25. Signal ground and power ground routing

AN4015 Revision history

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7 Revision history

Table 2. Document revision history

Date Revision Changes

09-Jan-2012 1 Initial release.

AN4015

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