dvcon final program 2012...3 past chair tom fitzpatrick mentor graphics corp. 18 whistle post ln....

www.dvcon.org

Sponsored by

Media Sponsors:

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For more than a decade, the Design and Verifi cati on Conference has provided engineers with the latest knowledge and trends to help them overcome the challenges of modern

system and circuit design. From technology and standards to techniques and methods, DVCon 2012 conti nues the traditi on of delivering quality informati on to our audience.

As we did last year, the organizers of DVCon 2012 used the att endee survey to help guide the program. Off ering Monday and Thursday tutorials was overwhelmingly popular in 2011, so we brought these to you once again. A noti ceable change, based on your requests, will be that the technical program and panels do not overlap with the exhibits.

We’ve worked diligently over the last few months to bring you high-quality papers, tutorials, panels, vendor exhibits, lunch programs, and a keynote speech this week. We hope to meet, and even surpass, your expectati ons.

Technical SessionsAgain this year, the number of paper submissions exceeded the number of submissions from the previous year. The Technical Program Committ ee is impressed with the quality of the submissions, so we have added additi onal sessions to bring you as many of the best papers as possible during the two-day technical program (you did tell us that adding an extra day to the conference

wasn’t a good idea, so we stayed with last year’s format). Voti ng for the best paper will again be the privilege of the conference att endees.

TutorialsDVCon’s tutorials provide an in-depth focus into topics you’ll likely fi nd interesti ng and benefi cial. Please view the tutorial descripti ons in the program or website to fi nd the best session for you.

Exhibits The vendor exhibits conti nue to be popular, allowing you an opportunity to see the latest products, soluti ons, and services from more than thirty companies. You will be able to talk with informed representati ves and ask them hard questi ons about their off erings. Giveaways and prizes add a fun element to the show.

Keynote Session and Industry Leaders PanelThe keynote speaker for this year’s DVCon will be Dr. Aart de Geus, CEO of Synopsys. If you’ve ever heard him speak, you’ll know that he gives an energeti c, broad view of the world as it is and where it’s headed. His keynote features the topic of systemic collaborati on, and he’ll tell you some principles for success in IC design.

We again have a panel of industry leaders, moderated by JL Gray of Verilab and “Cool Verifi cati on” fame. Hearing about the challenges these leaders have faced and overcome should be of interest to all, whether you’re new to IC design and verifi cati on or a pro.

Finally, if you’re involved in design and verifi cati on of today’s advanced ICs and you’ve never been to DVCon, I am glad you have made 2012 the year to join us.

General Chair’s Welcome

Table of ContentsKaren BartlesonSynopsys, Inc.2012 General Chair

Welcome to DVCon!

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Table of ContentsGeneral Chair’s Welcome ......................................................... 1Steering Committ ee.................................................................. 3Program Committ ee ................................................................. 4Conference Sponsor ................................................................. 5Voti ng Instructi ons ................................................................... 6Monday at a Glance .............................................................. 7NASCUG Meeti ng ..................................................................... 8Tutorials: 1 - 2 ...................................................................... 9-10Lunch Presentati on ................................................................. 11Tutorials: 3 - 4 .................................................................... 12-14Monday Colocated Meeti ng ................................................... 15Tuesday at a Glance ............................................................ 16Sessions: 1 - 3 .................................................................... 17-18Poster Session ......................................................................... 19Sessions: 4 - 6 .................................................................... 20-21Lunch Presentati on ................................................................. 22Panel Session .......................................................................... 23

Wednesday at a Glance ...................................................... 24Sessions: 7 - 9 .................................................................... 25-26Poster Session ......................................................................... 27Sessions: 10 - 12 ................................................................ 28-29Lunch Presentati on ................................................................. 30Keynote Address ..................................................................... 31Panel Session .......................................................................... 32Accellera Systems Initi ati ve Award ......................................... 33Thursday at a Glance .......................................................... 34Tutorials 5 - 6: .................................................................... 35-36Lunch Presentati on ................................................................. 37Tutorials 7 - 8 ..................................................................... 38-39DVCon Expo ................................................................... 40-58Event Sponsors ....................................................................... 59Hotel Floorplan ....................................................................... 65Exhibiti ng Companies ............................................................. 66

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Past Chair Tom FitzpatrickMentor Graphics Corp.18 Whistle Post Ln.Groton, MA 01450978-448-8797tom_fi [email protected]

General Chair Karen BartlesonSynopsys, Inc.1125 Point of The Pines Dr.Colorado Springs, CO [email protected]

Conference ManagerKathy EmblerMP Associates, Inc.1721 Boxelder St., Ste. 107Louisville, CO [email protected]

Program Chair Ambar Sarkar, Ph.D.Paradigm Works, Inc.300 Brickstone Sq.Andover, MA [email protected]

Finance ChairLynn BannisterAccellera Systems Initi ati ve1370 Trancas St., Ste. 163Napa, CA [email protected]

Accellera Systems Initi ati ve Marketi ng Representati veThomas LiSpringSoft , Inc.1732 North First Street, Suite 200San Jose, CA 95112408-961-4460thomas_li@springsoft .com

Accellera Systems Initi ati ve Representati veYati n TrivediSynopsys, Inc.700 East Middlefi eld Rd.Mountain View, CA 94043650-584-5000yati [email protected]

Program Vice ChairShankar Hemmady Synopsys, Inc.700 East Middlefi eld Rd. Mountain View, CA [email protected]

Publicity/Marketi ng ChairBarbara Benjamin HighPointe Communicati ons14359 SE Donatello LoopHappy Valley, OR [email protected]

Tutorial/Panel ChairStanley J. Krolikoski, Ph.D.Cadence Design Systems, Inc.2655 Seely Ave.San Jose, CA 95134 408-944-7260 [email protected]

Steering Committ ee

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Program Committ eeMark AzadpourSeagate Technology, LLC

Rajesh BawankuleNokia Siemens Networks

Dan BenuaSynopsys, Inc.

Jayaram BhaskereSilicon Corp.

Shalom Bresti ckerIntel Corp.

Ben ChenCavium, Inc.

Cliff ord E. CummingsSunburst Design, Inc.

Charles DawsonCadence Design Systems, Inc.

Joanne DeGroatOhio State Univ.

Harry FosterMentor Graphics Corp.

Ning GuoParadigm Works, Inc.

Kaiming HoFraunhofer-Gesellschaft

Phu HuynhCadence Design Systems, Inc.

Alfonso IniguezMicrochip Technology, Inc.

Neyaz KhanMaxim Integrated Products, Inc.

Joonyoung KimIntel Corp.

Kelly LarsonNVIDIA Corp.

Andrew “Paul” Marriott Verilab, Inc.

Gordon McGregor Verilab, Inc.

Don MillsMicrochip Technology, Inc.

Byeong MinSamsung

Nagi NaganathanLSI Corp.

Bindesh PatelSpringsoft , Inc.

Dave RichMentor Graphics Corp.

Erik SeligmanIntel Corp.

Nimalan SivaCisco Systems, Inc.

Stuart SutherlandSutherland-HDL, Inc.

Benjamin TingXilinx, Inc.

Robert Troy ON Semiconductor

Greg TumbushTumbush Enterprises, LLC

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Conference SponsorAccellera Systems Initi ati ve, the proud sponsor of DVCon, is an independent organizati on with the mission to provide design and verifi cati on standards required by

systems, semiconductor, IP and design tool companies to enhance a front-end design automati on process. We collaborate with our community of companies, individuals and organizati ons in delivering the standards that lower the cost to design commercial EDA, IC and embedded system soluti ons. As a result of its partnership with the IEEE, Accellera Systems Initi ati ve standards are transferred to the IEEE Standards Associati on for formalizati on and ongoing change control. Accellera Systems Initi ati ve: A New Synergy for StandardsSystem, soft ware, and semiconductor design are converging to meet the increasing challenges to create complex integrated circuits and system on chips. This convergence has brought to the forefront the need for a single organizati on to facilitate the creati on of system-level, semiconductor design, and verifi ca-ti on standards. Leading industry standards associati ons Accel-lera and the Open SystemC Initi ati ve (OSCI) merged in 2011

to form a single organizati on, Accellera Systems Initi ati ve, to address the needs of the system and semiconductor designers who must fi nd new and smarter ways to create and produce increasingly complex chips. The new organizati on will evolve to create more comprehensive standards that benefi t the global electronic design community. MembershipAccellera Systems Initi ati ve’s members directly infl uence development of the most important and widely used standards in electronic design. Member companies protect and leverage their investment in design languages through their funding of a proven, eff ecti ve and responsible organizati on. In additi on, our members have a higher level of visibility in the EDA industry as acti ve parti cipants in Accellera Systems Initi ati ve-sponsored acti viti es and as contributors to its decisions, which impact the EDA industry. For a full list of technical acti viti es that are supported by Accellera Systems Initi ati ve, and for informati on on how to join us, please visit our website at www.accellera.org.

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DVCon Best Paper Voti ng Instructi onsAs a full conference or one-day only registrant, you are enti tled to vote for the “DVCon Best Paper” award. The Att endees are the judges!

Now enjoy the convenience of voti ng from your PC, mobile device, or at a designated voti ng stati on located by the DVCon registrati on area.

Best Paper Voting - FAQQ: I accidentally voted on a paper that I did not mean to. Can I redo my vote?A: Yes, you can change your vote on any paper, at anyti me before 3:45pm on February 29th.

Q: The online voti ng shows that I have voted on papers which I did not vote on. What does this mean and how do I undo it?A: This means that at some point your Badge ID voted on those papers. If you suspect someone else is using your Badge ID you should go to the Registrati on Desk to be assigned a new ID.

Just Follow These Steps

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3

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Go to htt p://vote.dvcon.org

Enter your Badge ID & First Name

Vote on the papers you have att ended

See the winner at 4:30pm on Wednesday, February 29th, in the Oak/Fir Ballroom following the panel

DVConBest Paper 2012ote

Sponsored by:

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Monday, February 27

Registrati onBayshore Foyer

7:00am - 5:00pm

Self-Parking Discounted Fee$7.00 per day with

no in/out privileges

Colocated Meeti ngEDAC Emerging Companies

Oak Ballroom6:30 - 9:00pm

MondayOak Ballroom Fir Ballroom Pine Ballroom

Colocated Event: NASCUG Users Group

Meeti ng XVII

Tutorial 2 :UVM: Ready, Set, Deploy!

Sponsored Luncheon:Town Hall Lunch with the Accellera Systems Initi ati ve

Pine Ballroom

Tutorial 1: An Introducti on to

IEEE 1666-2011, the New SystemC Standard

Tutorial 2 :UVM: Ready, Set, Deploy!

Tutorial 3:An Introducti on to

the Unifi ed Coverage Interoperability Standard

Tutorial 4: Verifi cati on and Automati on Improvement Using IP-XACT

IP-XACT TM

Time: 8:00am

9:00am

10:00am

11:00am

12:00pm

1:00pm

2:00pm

3:00pm

4:00pm

5:00pm

6:00pm

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Monday, February 27

NASCUG Users Group Meeti ng XVII

The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC user experiences among industry, research and universiti es. NASCUG operates independently but works in collaborati on with the Accellera Systems Initi ati ve to provide open forums for promoti ng informati on exchange. Our goal is to make SystemC end-users more eff ecti ve through shared knowledge, user interacti on and collaborati on. Find out more and register for NASCUG events at www.nascug.org.

Room: Oak Ballroom Time: 8:30am - 12:00pm

8:30 - 9:00 AM Registrati on and Conti nental Breakfast

9:00 - 12:00 PMWelcome, Agenda, & NASCUG Introducti onTor Jeremiassen, Texas Instruments, Inc., USA

Accellera Systems Initi ati ve:A New Synergy for Standards What does C++2011 mean to SystemC?David C. Black, Doulos, USA

Synchronizati on between a SystemC based off -line restbus simulator and a Hardware-In-the-Loop FlexRay networkGilles Bertrand Defo, Univ. of Paderborn, Germany

Extending Fixed Sub-Systems at the TLM Level - Experiences from the FPGA WorldFrank Schirrmeister, Cadence Design Systems, Inc., USA

A Generic Language for Hardware & Soft ware, Are We There Yet? An Explorati ve Case Study Examining the Usage of SystemC for Multi core ProgrammingSushil Menon, Univ. of Pennsylvania, USA

Closing Remarks / DrawingJack Donovan, Duolog Technologies Ltd.

NASCUG is one of many events at of Accellera Systems Initi ati ve Day 2012

8:30 am - 12:00 pmNASCUG Users Group Meeti ng XVIIFree to industry professionals

12:00 pm - 1:00 pmTown Hall Lunch with Accellera Systems Initi ati ve1:30 pm - 5:00 pmDVCon Tutorial: “An Introducti on to IEEE P1666-2011, the New SystemC StandardFee and separate registrati on with DVCon required

AGENDA

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Monday, February 27

• New constructs which give more fl exibility and control when pausing and restarti ng the scheduler.

• The new sc_vector class, which is powerful mechanisms for coding regular structures.

• The new features that facilitate the use of SystemC with multi ple operati ng system threads, paving the way to exploiti ng multi core architectures for SystemC simulati on.

• Other technical enhancements to SystemC, including event lists, named events, fi ltering reports based on verbosity, and control over the number of processes that can write to a signal.

• Enhancements to TLM-2.0 which permit more fl exible use of the generic payload att ributes.

In additi on, this tutorial will provide an introducti on to the forthcoming draft Confi gurati on Standard which targets the confi gurati on of SystemC models. Key classes in the standard, which include parameters, brokers and accessors, will be described, and the use of the Confi gurati on Standard to perform common tasks such as creati ng, initi alizing, updati ng, monitoring, hiding and locking parameter values will be demonstrated.Speaker(s):

John Aynsley - DoulosDavid C. Black - DoulosTor Jeremiassen - Texas Instruments, Inc.

Tutorial 1 • An Introducti on to IEEE 1666-2011, the New SystemC Standard

Room: Oak Ballroom Time: 1:30 - 5:00pmOrganizer(s):

John Aynsley - Doulos

The latest version of the IEEE 1666 Standard SystemC Language Reference Manual, published early in 2012, represents the marriage of the SystemC and TLM-2.0 libraries into a single standard, together with some signifi cant improvements to SystemC relevant to both modeling and synthesis. This tutorial will be your fi rst chance to see the new features of SystemC and TLM-2.0 presented in full now the new standard has been published, including a behind-the-scenes insight into the moti vati on behind the changes. We will also present examples illustrati ng the new features in acti on using the latest version of the OSCI Proof-of-Concept SystemC simulator, which is compliant to the new IEEE standard.This tutorial represents a unique chance to improve your understanding of SystemC as well as giving you a kick start with the new language standard, and is not a presentati on on tool features. Topics to be taught in detail include:

• The new process control extensions to SystemC, which provide more fl exibility when using SystemC to model abstract schedulers and abstract clock gati ng, which unify the old thread and clocked thread constructs, and which give more fl exibility when using SystemC for hardware synthesis.

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Monday, February 27

This tutorial will appeal to new SystemVerilog users taking their fi rst steps into constrained random verifi cati on as well as to power users looking to take advantage of the most recent developments in UVM. Working knowledge of SystemVerilog (IEEE 1800) and familiarity with at least one simulator is assumed.

Speaker(s):Tom Fitzpatrick - Mentor Graphics Corp.Kathleen Meade - Cadence Design Systems, Inc.Adiel Khan - Synopsys, Inc.Stephen D’Onofrio - Paradigm Works, Inc.John Aynsley - DoulosMark Strickland - Cisco Systems, Inc.Vanessa Cooper - Verilab, Inc.John Fowler - Advanced Micro Devices, Inc.

Peter J. D’Antonio - The MITRE Corp. Justi n Refi ce - Advanced Micro Devices, Inc.

Room: Fir Ballroom Time: 8:30am - 5:00pm

Organizer(s): Dennis Brophy - Accellera Systems Initi ati ve Stanley Krolikoski - Accellera Systems Initi ati veYati n Trivedi - Accellera Systems Initi ati ve

Universal Verifi cati on Methodology (UVM) as a standard and an open-source library has been available for more than a year. It conti nues to gain adopti on across the verifi cati on community.

This tutorial will be presented by expert verifi cati on methodology architects and engineers. It will begin with an introducti on to UVM, concepts of structured verifi cati on methodology, base classes, resource confi gurati on management, error handling and report generati on. The tutorial will conti nue with the UVM register package, including how to create and manage sti mulus and checking at the register level. The morning session will conclude with a review of all of the topics, showing how they fi t together in a complex SOC verifi cati on environment.

Introducti on of these fundamental concepts will be followed by several real-life user experiences including lessons learned in preparing transiti on to UVM, architecti ng reusable testbenches, debug techniques and use of TLM 2.0 in real verifi cati on environments.

Tutorial 2 • UVM: Ready, Set, Deploy

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Monday, February 27

Room: Pine Ballroom Time: 12:00 - 1:00pm

SPONSORED LUNCHEON: Town Hall Lunch with the Accellera Systems Initi ati ve

Join us at lunch to celebrate the emergence of the Accellera Systems Initi ati ve. This “town hall” meeti ng will have no presentati ons, but rather will feature you, the forward-looking front-end standards community, exchanging ideas on the future of the new organizati on. Stan Krolikoski, DVCon Tutorial and Panels Chair and Secretary of the Accellera Systems Initi ati ve, will host this lively meeti ng in conjuncti on with Accellera Systems Initi ati ve Offi cers, Board Members and Technical Working Groups Chairs.

The main topic for this Town Hall discussion will be:

“What will success for the Accellera Systems Initi ati ve look like?”

There are many facets to this questi on, for example:• New standards that should be pursued• Synergies that ought to be exploited between existi ng or emerging standards• Relati onships with or expansion into adjacent technology areas, e.g., the Embedded SW world• Extension of User Groups acti vity across all of our standards

Come prepared to discuss these and other factors that will put the Accellera Systems Initi ati ve on a path to success that will eclipse even the stellar achievements of its two predecessors, Accellera and OSCI.

Sponsored by:

Monday Lunch Presentati on

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Monday, February 27

Tutorial 3 • An Introducti on to the Unifi ed Coverage Interoperability Standard

Organizer(s): Dr. Ambar Sarkar - Paradigm Works, Inc.

Presented by the members of the UCIS Committ ee.

Coverage metrics are criti cal to measuring and guiding design verifi cati on. As designs have grown, increasingly advanced verifi cati on technologies, methods and additi onal metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verifi cati on, but one step in the right directi on is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way.

The Unifi ed Coverage Interoperability Standard (UCIS) is a new Accellera standard for an applicati on programming interface (API) that facilitates the creati on of such a unifi ed coverage database that allows for interoperability of coverage data across multi ple tools from multi ple vendors.

This presentati on provides an overview of UCIS and its API and how users plan to enhance their verifi cati on fl ows using it. We provide a survey of many of the coverage metrics commonly used and how they are modeled in UCIS. The informati on that users will be able to access through UCIS will allow them to write their own

Room: Pine Ballroom Time: 1:30 - 3:00pmapplicati ons to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.

This presentati on is intended for verifi cati on practi ti oners and tool developers alike and serves as both an introducti on and a survey of UCIS.

Speaker(s):Dr. Richard Ho - D. E. Shaw ResearchDr. Ambar Sarkar - Paradigm Works, Inc.

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Monday, February 27

The tutorial is composed of 4 main sub-secti ons, followed by a poster session open to all.

- Improving Verifi cati on effi ciency using IP-XACT - (3:30pm-4:00pm) Presenter: John Swanson, Synopsys, Inc.

• This secti on introduces some of the main ways that IP-XACT can be used to improve verifi cati on effi ciency and IP quality.

- User Presentati on: Verifi cati on and Automati on Improvement Using IP-XACT - (4:00pm-4:30pm) Presenter: Kamlesh Pathak, STMicroelectronics

• This secti on introduces a user perspecti ve on how the industry is using IP-XACT to enable higher producti vity and quality verifi cati on fl ows.

- IP-XACT and UVM - (4:30pm-5:00pm) Presenter: David Murray, Duolog Technologies Ltd.

• Many aspects of the HW/SW interface can be described using IP-XACT. This presentati on introduces some of the IP-XACT HW/SW interface constructs and shows how these can be used to provide automati on for UVM register packages allowing very effi cient HW/SW interface verifi cati on through UVM.

Room: Pine Ballroom Time: 3:30 - 6:30pm

Organizer(s): Rohit Jindal - STMicroelectronics

What is IP-XACT?

IP-XACT was created by the SPIRIT Consorti um and is now part of Accellera. IEEE 1685, the IP-XACT standard describes an XML Schema for meta-data documenti ng Intellectual Property (IP) used in the development, implementati on and verifi cati on of electronic systems and an Applicati on Programming Interface (API) to provide tool access to the meta-data. This schema provides a standard method to document IP that is compati ble with automated integrati on techniques.

Scope of the tutorialImproving the producti vity of IP-based design is essenti al. This tutorial focuses on providing an opportunity to learn more about IP-XACT and how this standard can be used to enhance your IP based design and verifi cati on fl ow.

Tutorial 4 • Verifi cati on and Automati on Improvement Using IP-XACT

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Monday, February 27

Room: Pine Ballroom

Tutorial 4 (cont.)

- IP-XACT Extensions - (5:00pm-5:30pm) Presenter: Sylvain Duvillard, Magillem Design Services

• As the scope IP-XACT usage increases, is it is someti mes necessary to add extensions onto IP-XACT. This secti on shows how easy it is to extend IP-XACT to capture diff erent data domains and introduces some of the emerging extensions that are currently being standardized.

- Poster Presentati ons - (5:30pm - 6:30pm) • Many companies are providing automati on soluti ons based on

the IP-XACT standard. This secti on enables you to check out all the current off erings from EDA companies. Refreshments provided.

Speaker(s):John Swanson - Synopsys, Inc., Kamlesh Pathak - STMicroelectronics David Murray - Duolog Technologies Ltd. Sylvain Duvillard - Magillem Design Services

IP-XACT TM

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Monday, February 27

Room: Oak Ballroom Time: 6:30 - 9:00pm

Session Chair: Paul McLellan - Green Folder

Organized by the EDAC Emerging Companies Committ ee.

EDA companies oft en address hardware/soft ware co-design from a hardware point of view. ie, how can soft ware developers run their soft ware on this representati on of a chip that was designed on our tools. This viewpoint oft en overlooks the real concerns of soft ware developers. Today, since soft ware is the fastest growing and the largest engineering content of a SoC/ASIC design, it is ti me for the EDA industry to understand the needs and concerns of the soft ware industry. This panel att empts to address these needs and concerns.

The panel is organized by Paul McLellan, an EDA industry: guru, veteran, analyst and author. He has extensive experience in IC design, soft ware development and system virtualizati on. In parti cular he was VP marketi ng at VaST (since acquired by Synopsys) and Virtutech (since acquired by Wind River/Intel). The panelists include soft ware engineering managers who are responsible for SoC/ASIC soft ware development at major corporati ons. Aft er the panelists discuss their issues, there is a 30 minute audience questi on and answer session.

Sponsored By:

Colocated Meeti ng - Hardware/Soft ware Co-Design from a Soft ware Perspecti ve

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Tuesday, February 28


7:00am - 6:30pm



Oak Ballroom Fir Ballroom San Jose/Santa Clara Room

Opening Session • Oak Ballroom

Session 1: Low-Power Techniques

Session 2: UVM Techniques

Session 3: SystemC and Beyond

Poster Session 1/Coff ee Break • Gateway Foyer

Session 4: Verifi cati on Benchmarking

and Effi ciencySession 5:

Formal TechniquesSession 6:

Mixed-Signal Verifi cati on

Sponsored Luncheon: Earn Your Degree in the Low-Power Arts and Sciences

Pine/Cedar Ballroom

Industry Leaders Panel:The Resurgence of Chip Design

Exhibits • Bayshore Ballroom • 3:30 - 6:30pm

Time: 8:00am

9:00am

10:00am

11:00am

12:00pm

1:00pm

2:00pm

3:00pm

TuesdayWe invite you to join us

for a recepti on in the Bayshore Ballroom:

5:00 - 6:00pm

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Session 1 • Low-Power TechniquesRoom: Oak Ballroom • Time: 9:00 - 10:30am

Session Chair: Charles Dawson - Cadence Design Systems, Inc.

1.1 Low-Power SoC Verifi cati on: IP Reuse and Hierarchical Compositi on Using UPF Amit Srivastava, Rudra Mukherjee, Erich Marschner,

Chuck Seeley - Mentor Graphics Corp.Sorin Dobre - Qualcomm, Inc.

1.2 The Case for Low-Power Simulati on-to-Implementati on Equivalence Checking

Himanshu Bhatt , John Decker, Hiral Desai - Cadence Design Systems, Inc.

1.3 Is Power State Table (PST) Golden? Ankush Bagotra, Neha Bajaj,

Harsha Vardhan Dasagrandhi - Synopsys, Inc.

Session 2 • UVM TechniquesRoom: Fir Ballroom • Time: 9:00 - 10:30am

Session Chair: Neyaz Khan - Maxim Integrated Products, Inc.

2.1 Easier SystemVerilog with UVM: Taming the Beast John Aynsley - Doulos2.2 OVM & UVM Techniques for On-the-Fly Reset Muralidhara Ramalingaiah, Boobalan Anantharaman -

Cypress Semiconductor Corp.2.3 Register This! Experiences Applying UVM Registers Sharon Rosenberg, Adam Sherer, Kathleen Meade -

Cadence Design Systems, Inc.

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Session 3 • SystemC and BeyondRoom: San Jose/Santa Clara Room • Time: 9:00 - 10:30am

Session Chair: Joanne DeGroat - Ohio State Univ.

3.1 A SystemC Library for Advanced TLM Verifi cati on Marcio F.S. Oliveira, Christoph Kuznik,

Wolfgang Mueller - Univ. of PaderbornWolfgang Ecker, Volkan Esen - Infi neon Technologies

3.2 Hardware/Soft ware Co-Verifi cati on Using Specman and SystemC with TLM Ports

Horace Chan, Brian Vandegriend - PMC-Sierra, Inc.3.3 Designing, Verifying, and Building an Advanced L2

Cache Subsystem Using SystemC Thomas Tessier, Dan Ringoen, Hai Lin,

Eileen Hickey - Paneve, LLCSteven Anderson - Forte Design Systems

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Room: Gateway Foyer Time: 10:30 - 11:00am

Poster Session 1

Session Chair: Shankar Hemmady - Synopsys, Inc.

1.1 SystemVerilog Checkers: Key Building Blocks for Verifi cati on IP

Dmitry Korchemny, Erik Seligman, Laurence Bisht - Intel Corp.

1.2 PSL/SVA Asserti ons In Spice Donald J. O’Riordan, Prabal K. Bhatt acharya -

Cadence Design Systems, Inc.1.3 The Missing Link: The Testbench to DUT Connecti on Dave Rich - Mentor Graphics Corp.1.4 Blending Multi ple Metrics from Multi ple Verifi cati on

Engines for Improved Producti vity Darren Galpin - Infi neon Technologies Darron K. May, Thomas Ellis (Speaker only) -

Mentor Graphics Corp.1.5 Chef’s Special - An Effi cient Verifi cati on Recipe for

Maximizing Producti vity While Using a Third Party Verifi cati on IP

Bhavik M. Vyas - Marseille Networks, Inc. Abhisek Verma, Amit Sharma, Varun Sundaran -

Synopsys, Inc.

1.6 Data Mining Techniques to Improve Verifi cati on Effi ciency and Predict Verifi cati on Closure

Jithendra Madala, Chijioke Anyanwu - MIPS Technologies, Inc., Anupam Bakshi, Niti n Ahuja - Agnisys, Inc.

1.7 Effi cient Distributi on of Video Frames to Achieve Bett er Throughput

Kiran Maiya - Synopsys, Inc.Suruchi Jain, Bhavik M. Vyas - Marseille Networks, Inc.

1.8 Keeping Score - Techniques for Scoreboard Design and Development

Gordon Allan - Mentor Graphics Corp.1.9 Creati ng a Complete Low Power Verifi cati on Strategy

Using the Common Power Format and UVM Robert J. Meyer, Joel B. Artmann - Medtronic, Inc.1.10 An Integrated Framework for Power-Aware Verifi cati on

Harsh Chilwal, Manish Jain, Bhaskar Pal - Synopsys, Inc.1.11 New Challenges in Verifi cati on of Mixed-Signal IP

and SoC DesignLuke Lang, Qi Wang (Speaker Only), Christi na Chu - Cadence Design Systems, Inc.

1.12 Random Stability - Don’t Leave it to Chance!Avidan Efody, Rich Edelman - Mentor Graphics Corp.

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Session 4 • Verifi cati on Benchmarking and Effi ciencyRoom: Oak Ballroom • Time: 11:00am - 12:30pm

Session Chair: Cliff ord Cummings - Sunburst Design, Inc.

4.1 Yikes! Why is My SystemVerilog Testbench so Slow? Frank Kampf - IBM Corp.,

Justi n Sprague, Adam Sherer - Cadence Design Systems, Inc.

4.2 How I Learned to Stop Worrying and Love Benchmarking Functi onal Verifi cati on!

Michael G. Bartley, Mike Benjamin - Test and Verifi cati on Soluti ons

4.3 Keeping Up with Chip - The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Effi cient

Stuart Sutherland - Sutherland Hdl, Inc.Tom Fitzpatrick - Mentor Graphics Corp.

Session 5 • Formal TechniquesRoom: Fir Ballroom • Time: 11:00am - 12:30pm

Session Chair: Erik Seligman - Intel Corp.

5.1 Exhausti ve Latch Flow - Through Verifi cati on with Formal Methods

Baosheng Wang, Sean Ater, Baris Piyade, Brian McMinn, Borhan Roohipour - Advanced Micro Devices, Inc.

Antonio Celso Caldeira, Jr., Bill Au, Rageev Ranjan - Jasper Design Automati on, Inc.

5.2 Shaping Formal Traces Without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine Using Formal Verifi cati on

David N. Goldberg, Adriana Maggiore, David J. Simpson - Ubicom

5.3 X-Propagati on Woes: Masking Bugs at RTL and Unnecessary Debug at the Netlist

Lisa J. Piper, Vishnu C. Vimjam - Real Intent, Inc.

21


Session 6 • Mixed-Signal Verifi cati onRoom: San Jose/Santa Clara Room • Time: 11:00am - 12:30pm

Session Chair: Nagi Naganathan - LSI Corp.

6.1 From Spec to Verifi cati on Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design

Neyaz Khan - Maxim Integrated Products, Inc.Yaron Kashai - Cadence Design Systems, Inc.

6.2 Analog Transacti on Level Modeling for Verifi cati on of Mixed-Signal Blocks

Alexander W. Rath, Volkan Esen, Wolfgang Ecker - Infi neon Technologies AG

6.3 Experience with OVM and Mixed-Signal Verifi cati on of an Impedance Calibrati on Block for a DDR InterfaceHarry Wang - Microsemi Corp., Wessam El-Naji, Kenneth M. Bakalar, - Mentor Graphics Corp.

22


Tuesday Lunch Presentati onRoom: Pine/Cedar Ballroom Time: 12:30 - 2:00pm

SPONSORED LUNCHEON: Earn Your Degree in the Low-Power Arts and Sciences

Teams that have completed low-power projects know that simply describing the structures in a power-format fi le does not guarantee working silicon. There is science in the tools that accurately process the power format and there is art in creati ng a power-aware verifi cati on methodology.

With the advent of power-aware structures, physical att ributes are being forced on the hardware-descripti on languages (HDLs) that were designed as abstracti ons of those very att ributes. While this conundrum may appear to be solved with tools that process the power-format fi le without error and produce nice waveforms, the second-order aff ects can give rise to subtle bugs.

How domains are ramped and/or shutdown, how feed-through is managed, and where isolati on cells are located can lead to false positi ves in verifi cati on and bugs in silicon. Managing these second-order issues with accurate verifi cati on engines and formal equivalence between the functi onal verifi cati on and implementati on fl ows is the low-power science.

The art in low-power verifi cati on is in the methodology. That art starts with the shift from simulati ng just the few directed tests associated with each legal power mode to making every verifi cati on regression power-aware because any one of them could trip a power mode. It expands to the generati on of low-power asserti ons, the use of formal techniques, and the creati on of a low-power verifi cati on plan directly from the power format itself.

Cadence and user experts will lead verifi cati on engineers and managers in a lively low-power discussion and confer degrees in the low-power arts and sciences at the conclusion of the luncheon.

Sponsored by:

23


Industry Leaders Panel SessionRoom: Oak/Fir Ballroom Time: 2:30 - 3:30pm

The Resurgence of Chip Design

Moderator(s): JL Gray - Verilab, Inc.

Over the course of the last decade, many technologists claimed that in the future, the most important part of a new product would be soft ware, not the underlying hardware. Hardware would be a commodity. Everyone would write unique soft ware on top of off the shelf hardware to create a value add. The relevance of chip design, and career prospects for chip designers would be limited.

But what actually happened was quite diff erent. Large technology fi rms have hired ever-growing teams of engineers to design the custom chips criti cal to the success of their upcoming products. Building your own ASIC is oft en the only way to reach the desired power, performance, and cost goals.

The DVCon 2012 Industry Leaders Panel will focus on bett er understanding the trends driving this resurgence.

Panelist(s):Ted Vucurevich - CEO of Enconcert

John Costello - VP of IC Design at Altera Gary Smith - founder and Chief Analyst Gary Smith EDA Jim Hogan - Founding Partner at Vista Ventures LLC

24

Wednesday, February 29

Best Paper Award Presentati on

Oak/Fir Ballroom4:30pm

Sponsored by:


7:00am - 7:00pm



Wednesday

Oak Ballroom Fir Ballroom San Jose/Santa Clara Room

Session 7: Verifi cati on and Debugging Tips

Session 8: Getti ng to

Coverage Closure

Session 9: UVM in a

Multi -Platf orm World

Poster Session 2/Coff ee Break • Gateway Foyer

Session 10: UVM Sti mulus Generati on

Session 11: Verifi cati on Case Studies

Session 12: SystemVerilog Tips

and Techniques

Sponsored Luncheon: Industry Leaders Verify with Synopsys

Pine/Cedar Ballroom

Keynote Address: Aart de Geus, Synopsys, Inc.Systemic Collaborati on: Principles for Success in IC Design

Coff ee Break • Gateway FoyerPanel: Build or Buy: Which is the Best Practi ce for

Hardware-Assisted Verifi cati on?

Exhibits • Bayshore Ballroom • 4:30 - 7:00pm

Time: 8:00am

9:00am

10:00am

11:00am

12:00pm

1:00pm

2:00pm

3:00pm

4:00pm

We invite you to join us for a recepti on in the

Bayshore Ballroom:4:30 - 5:30pm

25


Session 7 • Verifi cati on and Debugging TipsRoom: Oak Ballroom • Time: 8:00 - 10:00am

Session Chair: Dan Benua - Synopsys, Inc.

7.1 Advanced Techniques for AXI Fabric Verifi cati on in a Soft ware/Hardware OVM Environment

Galen Blake - Altera Corp., Steve Chappell, Jay O’Donnell - Mentor Graphics Corp.

7.2 Failure Triage: The Neglected Debugging Problem Sean Safarpour, Yu-Shen Yang, Evean Qin -

Vennsa Technologies, Inc.Brian Keng - Univ. of Toronto

7.3 Memory Debugging of Virtual Platf orms with TLM 2.0 George F. Frazier, Neeti Bhatnagar, Qizhang Chao,

Tuay-Ling K. Lang - Cadence Design Systems, Inc.7.4 A 30-Minute Project Makeover Using

Conti nuous Integrati on J.L. Gray, Gordon C. McGregor - Verilab, Inc.

Session 8 • Getti ng to Coverage ClosureRoom: Fir Ballroom • Time: 8:00 - 10:00am

Session Chair: Gordon McGregor - Verilab, Inc.

8.1 Relieving the Parameterized Coverage Headache Christi ne Lovett , Bryan Ramirez,

Stacey Secatch - Xilinx, Inc. Michael Horn - Mentor Graphics Corp.8.2 Bringing Conti nuous Domain into

SystemVerilog Covergroups Prabal K. Bhatt acharya, Donald J. O’Riordan, Swapnajit

Chakraborti , Vaibhav Bhutani - Cadence Design Systems, Inc., Scott Litt le - Intel Corp.

8.3 Systemati cally Achieving CDC Verifi cati on Closure Based on Coverage Models and Coverage Metrics

Ashish Hari, Yogesh Badaya - Mentor Graphics Corp.8.4 Graph-IC Verifi cati on Dennis Ramaekers - ST-Ericsson

Gregory Faux - STMicroelectronics

26


Session 9 • UVM in a Multi -Platf orm WorldRoom: San Jose/Santa Clara Room • Time: 8:00 - 10:00am

Session Chair: Greg Tumbush - Tumbush Enterprises, LLC

9.1 Melti ng Verifi cati on Pot: Integrati ng RVM/VMM and UVM - A Practi cal Guide and Lessons Learned

Mark Azadpour - Seagate Technology, LLC9.2 Experiences in Migrati ng a Chip-Level Verifi cati on

Environment from UVM EA to UVM 1.1Sasidhar Dudyala, Manikandan S., Srishan Thirumalai, Dave Stang, Ashish Kumar - LSI Corp.

9.3 e/eRM to SV/UVM - Mind the Gap, But Don’t Miss the TrainAvidan Efody, Michael Horn - Mentor Graphics Corp.

9.4 Addressing HW/SW Interface Quality Through Standards

David Murray, Sean Boylan - Duolog Technologies Ltd.

27


Poster Session 2

Session Chair: Shankar Hemmady - Synopsys, Inc.

2.1 Metrics in SoC Verifi cati on: Not Just for Coverage Anymore Andreas Meyer, Harry D. Foster - Mentor Graphics Corp.2.2 UVM Do’s and Don’ts for Eff ecti ve Verifi cati on Sharon Rosenberg, Kathleen Meade -

Cadence Design Systems, Inc.2.3 Verifi cati on of Clock Domain Crossing Jitt er and

Meta-Stability Tolerance Using Emulati on Ashish Hari, Suresh Krishnamurthy, Yogesh Badaya,

Amit Jain - Mentor Graphics Corp.2.4 Registering the Standard: Migrati ng to the

UVM_REG Code BaseSachin Patel - Broadcom Corp.

Adiel Khan, Amit Sharma - Synopsys, Inc.2.5 Tips for Developing Performance-Effi cient

Verifi cati on Environments Varun S (Speaker Only) - Synopsys, Inc., Prashanth Srinivasa,

Sarath Chandrababu Valapala - LSI Corp.

2.6 Advanced Techniques for ARM L2 Cache Verifi cati on in an Accelerated Hardware and Soft ware Environment

Jay O’Donnell - Mentor Graphics Corp. Rob Pelt - Altera Corp.2.7 Leveraging ESL/TLM System Verifi cati on in RTL via UVM Ashok Mehta - Taiwan Semiconductor

Manufacturing Co., Ltd. Albert Chiang, Wei-Hua Han - Synopsys, Inc.2.8 Comprehensive Register Descripti on Languages David C. Black, Doug Smith - Doulos2.9 SoC Verifi cati on Using OVM: Leveraging OVM

Constructs to Perform Processor Centric Verifi cati on Cedric Macadangdang, Michael Castle (Speaker Only), Paul

Yue - Raytheon Company2.10 Dynamic and Scalable OVM Sti mulus for

Accelerated Functi onal Coverage Michael Castle - Raytheon Company

Room: Gateway Foyer Time: 10:00 - 10:30am

28


Session 10 • UVM Sti mulus Generati onRoom: Oak Ballroom • Time: 10:30am - 12:30pm

Session Chair: Mark Azadpour - Seagate Technology, LLC

10.1 There’s Something Wrong Between Sally Sequencer and Dirk Driver - Why UVM Sequencers and Drivers Need Some Relati onship Counseling

Mark Peryer - Mentor Graphics Corp.10.2 ACE’ing the Verifi cati on of a Coherent System

Using UVM Parag Goel, Amit Sharma, Romondy Luo, Ray Varghese,

Acharya Satyapriya - Synopsys, Inc.Peer Mohammed - Mindspeed Technologies, Inc.

10.3 Conscious of Streams Jeff rey A. Wilcox, Stephen D’Onofrio -

Paradigm Works, Inc.10.4 Confi guring Your Resources the UVM Way! Parag Goel, Amit Sharma - Synopsys, Inc.

Rajiv Hasija - Samsung

Session 11 • Verifi cati on Case StudiesRoom: Fir Ballroom • Time: 10:30am - 12:30pm

Session Chair:Joonyong Kim - Intel Corp.

11.1 Exquisite Modeling of Verifi cati on IP: Challenges and Recommendati onsAnuradha I. Tambad, Subashini Rajan, Imran Ali, Prashanth Srinivasa, Shivani Upasani - LSI Corp.

Adiel Khan (Speaker Only) - Synopsys, Inc.11.2 Supplementi ng Simulati on of a Microcontroller Flash

Memory Subsystem with Formal Verifi cati onAbdelouahab Ayari - Mentor Graphics Corp.

Othmane Bahlous - Infi neon Technologies AG 11.3 A Practi cal Approach to Measuring and Improving the

Functi onal Verifi cati on of Embedded Soft wareStephane Bouvier, Nicolas Sauzede - STMicroelectronicsFlorian Letombe, Julien Torrès, George Bakewell - SpringSoft , Inc.

11.4 Autocurati on: An Implementati on of a Conti nuous Integrati on System Employed in the Development of AMD’s Next-Generati on Microprocessor Core

Wei Foong Thoo, David A. Burgoon - Advanced Micro Devices, Inc.

29


Session Chair: Harry Foster - Mentor Graphics Corp.

12.1 SystemVerilog Asserti on Linti ng: Closing Potenti ally Criti cal Verifi cati on HolesLaurence Bisht, Dmitry Korchemny, Erik Seligman - Intel Corp.

12.2 Soft Constraints in SystemVerilog: Semanti cs and Challenges

Mark Strickland, HanLi Joseph Zhang - Cisco Systems, Inc., Jason Chen, Dhiraj Goswami, Alexander Wakefi eld - Synopsys, Inc.

12.3 Bett er Living Through Bett er Class-Based SystemVerilog Debug

Rich Edelman, Raghu Ardeishar, John Amouroux - Mentor Graphics Corp.

12.4 Holisti c Automated Code Generati on: No Headache with Last-Minute Changes

Klaus Strohmayer, Norbert Pramstaller - Dialog Semiconductor

Session 12 • SystemVerilog Tips and TechniquesRoom: San Jose/Santa Clara Room • Time: 10:30am - 12:30pm

30


Wednesday Lunch Presentati onRoom: Pine/Cedar Ballroom Time: 12:30 - 1:45pm

SPONSORED LUNCHEON: Industry Leaders Verify with Synopsys

Synopsys invites you to join us for lunch and a highly informati ve session covering the latest verifi cati on trends, challenges and soluti ons. You will hear leading industry experts discuss complex real-world verifi cati on challenges and present insights into best practi ces that help address them.

This luncheon provides a valuable opportunity to learn about new innovati ons in verifi cati on technology that enable improved performance and producti vity. If you are a verifi cati on engineer or manager, you won’t want to miss this special event.

Sponsored by:

31


Systemic Collaborati on: Principles for Success in IC DesignMulti -dimensional systemic complexity is now moving across the IC design ecosystem. Simultaneously, trends indicate that the massive amount of soft ware development needed across many domains is changing the way the players in the semiconductor industry understand their fundamental roles. Now, instead of making soft ware to support new hardware, we are increasingly shift ing to a perspecti ve of making new hardware to support the soft ware. The implicati ons of this extend from analog to digital interacti ons and from system to silicon design and verifi cati on challenges. Engineers must struggle to diff erenti ate their products in this rapidly

evolving eco-system. In this presentati on, Dr. de Geus will discuss several universal engineering principles that provide an architecture for how to think about the expanding roles of quality verifi cati on IP, models, and system-level soluti ons in the face of the economic and physical realiti es of advanced design.

Since co-founding Synopsys in 1986, Dr. Aart de Geus has led the growth of Synopsys from start-up synthesis enterprise to a diverse company that is a technology and market leader off ering a complete integrated circuit (IC) design soluti on from concept to silicon. Aart has long been considered one of the world’s leading experts on logic simulati on and logic synthesis. Among the numerous industry honors Dr. de Geus has received was being named Fellow of the Insti tute of Electrical and Electronics Engineers (IEEE) in 1999. He was honored for pioneering the commercial logic synthesis market with the IEEE Circuits and Systems Society Industrial Pioneer Award in 2001 and in 2007 was awarded the IEEE Robert N. Noyce Medal for his “contributi ons to, and leadership in, the technology and business development of Electronic Design Automati on.”

Room: Oak/Fir Ballroom Time: 2:00 - 3:00pm

Keynote Speaker:Aart de Geus Synopsys, Inc.

Keynote Address

32


Room: Oak/Fir Ballroom Time: 3:30 - 4:30pm

Build or Buy: Which is the Best Practi ce for Hardware-Assisted Verifi cati on?

Session Chair: Brian Bailey - Brian Bailey Consulti ng

Organizer(s): Laurie Stanley - Wired Island Ltd.

Emulati on and FPGA-based prototyping are widely used methodologies for system-level validati on of key design modules and fully integrated SoC designs. Both approaches for hardware-assisted verifi cati on (HAV) share many underlying technologies, yet the usage, applicati on, characteristi cs, and tool chain support have been quite diff erent.

Conventi onal emulati on systems employ custom-designed chips or standard FPGAs in special-purpose, dedicated hardware. Soft ware takes advantage of the custom architectures to provide large capacity with relati vely fast compile ti mes for mapping

designs into the hardware system and reasonably good visibility (observability and controllability). However, these systems are prohibiti vely expensive for broad deployment and both ti me-consuming and costly to upgrade to next-generati on chips and equipment.

With FPGA capacity and performance getti ng bigger and bett er, FPGA prototyping is a viable method for in-circuit emulati on using “off -the-shelf” or custom-designed boards. Prototype boards are higher performance and lower cost for deployment across multi ple users, projects or sites and more easily transiti oned to new generati ons. However, implementati on complexity and debug diffi culti es (limited visibility) have typically relegated usage to late in the development cycle.

The gap between these two HAV approaches is narrowing with the emergence of design automati on advancements. These include: soft ware-based methods for providing rich, real-ti me design visibility; interconnect technologies that create a universal

connecti on to both off -the-shelf and custom-designed boards; and specialized soft ware running on standard engineering workstati ons that turns conventi onal FPGA-based prototype boards into full-blown desktop emulators and brings the power of RTL debug on board.

Is this evoluti on in HAV technologies enough to overcome the traditi onal limitati ons of conventi onal emulati on systems and in-circuit emulati on with prototype boards? Does increasing the verifi cati on effi ciency of FPGA-based prototype boards create enough of a paradigm shift to alter the decision of whether to buy or build the next-generati on of emulators that can keep pace with the complexiti es of SoC verifi cati on fl ows?

Panelist(s):Albert Camilleri - Qualcomm, Inc.John Goodenough - ARM, Inc.Yu-Chin Hsu - SpringSoft , Inc.Peter Ryser - Xilinx, Inc.Frank Schirrmeister - Cadence Design Systems, Inc.

Panel Session

33


Accellera Systems Initi ati ve wishes to recognize the outstanding achievements of its Technical Committ ee members by selecti ng an outstanding contributor to our standards development process as a recipient of the Accellera Systems Initi ati ve Technical Excellence Award.

This fi rst annual award recognizes major contributi ons to the development of Accellera Systems Initi ati ve standards. Examples of such contributi ons may include leadership in standardizati on of new technologies, assuring achievement of standards development goals, and identi fying opportuniti es to bett er serve the needs of the industry through standards.

Any member of an Accellera Systems Initi ati ve Technical Committ ee or Working Group is eligible for the award. Candidates are nominated by the industry at large and are endorsed and selected by parti cipants in Accellera Systems Initi ati ve Committ ees.

The recipient of this year’s award will be announced at our annual Design and Verifi cati on Conference (DVCon)

Accellera Systems Initi ati veTechnical Excellence Award

34

Thursday, March 1

Thursday

Siskiyou Ballroom Donner Ballroom

Tutorial 5:Using “Apps” to Take Formal

Analysis Mainstream

Sponsored By:

Tutorial 6: Design & Verifi cati on of

Platf orm-Based, Multi -Core SoCs

Sponsored By:

Sponsored Luncheon: Formal Verifi cati on from Users Perspecti ves

Cascade/Sierra Ballroom

Tutorial 7: Leveraging Formal

Verifi cati on Throughout the Enti re Design Cycle

Sponsored By:

Tutorial 8:New Levels of Verifi cati on IP

Producti vity for SOC Verifi cati onSponsored By:

Time: 8:00am

9:00am

10:00am

11:00am

12:00pm

1:00pm

2:00pm

3:00pm

4:00pm

5:00pm


7:30am - 4:00pm



35

Thursday, March 1

Room: Siskiyou Ballroom Time: 8:30am - 12:00pm

Organizer(s): Joseph Hupcey III - Cadence Design Systems, Inc.

Formal analysis, also known as property checking, is an important technology in functi onal verifi cati on. All major IP and SoC providers use formal analysis as part of their verifi cati on soluti on, but oft en only on specifi c parts of a chip or only by dedicated formal experts.

This is changing rapidly. The “apps” (applicati ons) model, so familiar from consumer electronics, also applies to EDA tools. In the case of formal analysis, there are several apps that are driving mainstream usage. This tutorial presents some of the most important and promising formal apps.

Connecti vity checking provides a way to verify the top-level connecti ons of an SoC, both between the major blocks and between the blocks and the I/O pads. Formal analysis completely automates the process and delivers defi niti ve results.

Demonstrati ng defi niti ve conformance to a standard protocol is possible with an off -the-shelf asserti on-based verifi cati on IP (ABVIP) component. Formal analysis automati cally stress-tests all corner cases of the protocol and checks that all possible combinati ons of operati ons are exercised.

Tutorial 5 • Using “Apps” to Take Formal Analysis Mainstream

Verifi cati on completeness is determined primarily by coverage metrics from simulati on. Formal analysis can greatly assist the process of coverage closure by fi nding ways to reach deep coverage points or, alternati vely, proving that some coverage points are unreachable.

Finally, all of these apps have a common theme in that the user does not have to specify a large quanti ty of asserti ons for success. This tutorial also discusses asserti on synthesis as another “app” that can help formal analysis be easier for the non-expert user.

Speaker(s):Joseph Hupcey III - Cadence Design Systems, Inc.Yunshan Zhu - NextOp Soft ware, Inc.Christopher Komar - Cadence Design Systems, Inc.Vigyan Singhal - Oski Technology, Inc.

Sponsored by:

36

Thursday, March 1

Tutorial 6 • Design & Verifi cati on of Platf orm-Based, Multi -Core SoCsRoom: Donner Ballroom Time: 8:30am - 12:00pm

Organizer(s): Rebecca Granquist - Mentor Graphics Corp.

The era of platf orm-based SoCs has arrived. By increasing the granularity of pre-integrated and reused IP within an SoC platf orm, subsystems allow faster design and delivery of platf orm-based systems. Reusable subsystems represent the next advancement towards ever larger, reusable design functi ons. However, with each step in the size of reusable blocks, the integrati on and system verifi cati on complexiti es expand exponenti ally, from limited parameterizati on to parti al and full programmability. Platf orm-based SoCs target FPGA and traditi onal ASIC implementati ons meeti ng a very wide breadth of market needs for cost, power and performance.

In order to realize the benefi ts of platf orm-based SoCs, users must be able to develop, opti mize, integrate and verify diff erenti ati ng hardware blocks and the soft ware that defi nes the fi nal system. Time-to-market and quality are keys to success. Consumers demand polished products. Soft ware development and validati on must begin on day 1 to avoid costly schedule delays. Multi -core platf orms, with extensible coherent memory, increase the SoC architectural design, integrati on, verifi cati on, and debug challenges. Full system verifi cati on and test must begin early in order to adequately test the full breadth and depth of system architecture and performance and deliver the quality that today’s market demands.

In this tutorial, we will cover the process of defi ning an SoC system based on platf orm subsystem IP, the development and integrati on of hardware accelerati on blocks, analyzing system performance criteria, verifi cati on of the SoC functi onality, the development and validati on of soft ware using virtual prototyping and accelerati on technology and verifi cati on from block to SoC to full system.

Speaker(s):Stephen Bailey - Mentor Graphics Corp.Paul Marti n - ARM, Inc.Bryan Bowyer - Calypto Design Systems, Inc.Mark Peryer - Mentor Graphics Corp.Jim Kenney - Mentor Graphics Corp.Shabtay Matalon - Mentor Graphics Corp.

Sponsored By:

37

Thursday, March 1

Room: Cascade/Sierra Ballroom Time: 12:00 - 1:30pm

Thursday Lunch Presentati on

SPONSORED LUNCHEON: Formal Verifi cati on from Users Perspecti ves

Join us for lunch and an open discussion on how formal technology is being used by design and verifi cati on engineers to miti gate risk in their designs while meeti ng the challenges of ti me-to-market pressures. The lunch will feature a panel of users who will share their experiences with formal technology and how formal has helped them in diff erent facets of their design and verifi cati on methodologies. You will be given the opportunity to ask these formal experts about the results they achieved and their strategies for getti ng the most out of formal technology. Don’t miss this informati ve discussion that will serve as preamble to the tutorial on “Leveraging Formal Verifi cati on Throughout the Enti re Design Cycle” immediately following lunch.

Sponsored By:

38

Thursday, March 1

Tutorial 7 • Leveraging Formal Verifi cati on Throughout the Enti re Design Cycle

Organizer(s): Rob van Blommestein - Jasper Design Automati on, Inc.

The adopti on of formal verifi cati on technologies is increasing as designs become more complex. Unique and powerful formal technologies can break through to go beyond typical formal soluti ons to address a wide range of applicati ons. With these technologies, the benefi ts of formal technology can now been reaped throughout all design and verifi cati on stages including:

• Stand-alone verifi cati on of architectural protocols

• Designer sandbox testi ng for RTL development

• End-to-end data packet integrity

• SoC connecti vity and integrati on verifi cati on

• Root-cause isolati on and full proofs during post-silicon debug

Formal verifi cati on can be a valuable additi on to traditi onal verifi cati on methods. For example, applying formal techniques early in the design cycle to exhausti vely verifying block-level design functi onality can produce higher quality RTL delivered to unit and system level verifi cati on. Att endees will learn about

new formal technologies and fl ows that enable designers and verifi cati on engineers to augment existi ng fl ows. Also included will be discussions about how eff ort applied to one applicati on can be leveraged in others. When applied intelligently, formal technologies can enhance traditi onal design and verifi cati on fl ows to help reduce the risks associated with increasing SoC complexity.

Speaker(s):Lawrence Loh - Jasper Design Automati on, Inc.Norris Ip - Jasper Design Automati on, Inc.

Sponsored By:

Room: Siskiyou Ballroom Time: 1:30 - 5:00pm

39

Thursday, March 1

Room: Donner Ballroom Time: 1:30 - 3:30pmSession Chair:

Neill Mullinger - Synopsys, Inc.

As the number of and complexity of IPs used on SOCs increases, there is a need for Verifi cati on IP (VIP) with improved methodology support, performance, producti vity, ease-of-use, and debug. Reusability of tests and Verifi cati on IP is a major factor for producti vity as verifi cati on progresses through multi ple stages of detailed block verifi cati on, integrati on testi ng, and SOC verifi cati on. This tutorial will walk through the basic steps of installing, instanti ati ng and using advanced verifi cati on IP in a UVM environment. It will show some of the more advance aspects of sequence generators, error injecti on and callbacks using extensive code examples. It will also show how to use many new features to help with planning, coverage, confi gurati on and parti cularly debug that help to ramp on testbench development, quickly fi nd issues and measure progress.

This session will conclude with a 30 minute demonstrati on to show new methods for protocol-based debug.

Speaker(s):Bernie DeLay - Synopsys, Inc.John Elliott - Synopsys, Inc.

Sponsored By:

Tutorial 8 • New Levels of Verifi cati on IP Producti vity for SOC Verifi cati on

40

Agnisys, Inc. .......................................................................................702Aldec, Inc. ...........................................................................................802AMIQ EDA .........................................................................................704Axiom Design Automati on ..............................................604Blue Pearl Soft ware ........................................................................405Breker Verifi cati on Systems, Inc. ...............................................1002Cadence Design Systems, Inc. ....................................................1102Calypto Design Systems, Inc. .......................................................505The Dini Group, Inc. ........................................................................501Doulos ..................................................................................................701Duolog Technologies Ltd. ..............................................................302EDACafe ..............................................................................................301Esencia Technologies ......................................................................504EVE ........................................................................................................602Forte Design Systems .....................................................................404Innovati ve Logic, Inc. ......................................................................1104

Denotes fi rst ti me exhibitor

Bayshore Ballroom, Tuesday, February 28 - 3:30-6:30pmBayshore Ballroom, Wednesday, February 29 - 4:30-7:00pm

Expo Hours:

The DVCon Expo 2012 consists of vendors displaying the latest in Hardware Descripti on Languages, Hardware Verifi cati on Languages, and EDA tools for the design and verifi cati on of electronic systems and integrated circuits.

Jasper Design Automati on, Inc. .................................................601Mentor Graphics Corp. ..................................................................801Methodics, Inc. .................................................................................403Missing Link Tools, LLC. .................................................................605NextOp Soft ware, Inc. ....................................................................402Oski Technology, Inc. ......................................................................805Paradigm Works, Inc. .....................................................................1003PerfectVIPs .........................................................................................904Real Intent, Inc. ................................................................................902Semifore, Inc. ....................................................................................1004Sibridge Technologies ....................................................................1005SmartPlay ...........................................................................................804SpringSoft , Inc. .................................................................................401Synopsys, Inc. ....................................................................................1105Vennsa Technologies, Inc. .............................................................502Verifi c Design Automati on ...........................................................705Wafer Space .......................................................................................905

41

Exhibitor Floor Plan We invite you to join us for a

recepti on in the Bayshore Ballroom:


5:00 - 6:00pm

Wednesday,February 29

4:30 - 5:30pm

42

Agnisys, Inc.Booth # 702

www.agnisys.com

Agnisys off ers a suite of aff ordable design and verifi cati on tools for SoC, FPGAs and IP designers that enhance collaborati on, design re-use and producti ve team-based design methods. IDesignSpec automates creati on of register and memory maps guaranteeing higher quality and consistent results across team members. IVerifySpec is a soluti on for verifi cati on planning and audits that exposes verifi cati on holes driving faster verifi cati on closure. IAssertSpec eases the adopti on of asserti on based verifi cati on methodologies by guiding asserti on development while ensuring the asserti ons are consistent with the design specifi cati ons.

Aldec, Inc.Booth # 802 www.aldec.com

A global Verifi cati on Soluti ons provider for nearly 30 years, Aldec off ers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verifi cati on, Design Rule Checking, IP Cores, DO-254 Functi onal Verifi cati on and Military/Aerospace soluti ons. Stop by to learn how Aldec tools support the latest methodologies including VHDL, Verilog and SystemVerilog; OVM/UVM and VMM; Code and Functi onal Coverage; DSP Co-Simulati on (MATLAB® & Simulink®), Emulati on (Hardware-Assisted Verifi cati on) and more.

43

AMIQ EDA Booth # 704

www.amiq.com

AMIQ EDA provides soluti ons that help engineers increase design and verifi cati on producti vity. Its Design and Verifi cati on Tools (DVT) platf orm is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. DVT enables effi cient code writi ng, navigati on, debugging, and documentati on. It works with all major simulators and supports UVM, OVM, and VMM. The SystemVerilog Testbench Linter is a code analysis tool that fl ags suspicious language usage. It allows companies to implement their own specifi c guidelines and employ best coding practi ces. For further informati on visit: www.dvteclipse.com.

Axiom Design Automati onBooth # 604

www.axiom-da.com

Axiom Design Automati on, the clear leader in Multi -Cpu SystemVerilog simulati on, will showcase DesignerUVMtm, its latest ground breaking UVM debug environment. Built on top of MPSim SystemVerilog simulator’s ti ghtly integrated debugging environment, it has added signifi cant new capability for developing and debugging UVM testbenches. DesignerUVM features include the ability to view UVM Schemati c from the component hierarchy, check and create port connecti vity, trace port drivers and receivers and trace any signal from a virtual interface to the real interface and through RTL. Visit us in Booth 604 to see DesignerUVM demo.

44

Breker Verifi cati onSystems, Inc.Booth # 1002

brekersystems.com

Breker, the SoC Verifi cati on Company, is setti ng the bar for SoC verifi cati on. Its TrekSoC product is the fi rst commercially available tool that automates test generati on for multi -threaded, multi -cpu SoCs. TrekSoC easily verifi es system integrati on and hook-up confi gurati ons, but also enables smartbuilding of aggressive and sophisti cated tests for the deeper challenges of concurrent coherent multi -threaded capabiliti es. In producti on use at top semiconductor companies, TrekSoC integrates easily into your current environment while providing powerful graphical visualizati on and analysis.

Blue Pearl Soft wareBooth # 405

www.bluepearlsoft ware.com

Blue Pearl Soft ware is a privately held EDA (Electronic Design Automati on) company that develops soft ware to improve producti vity of semiconductor chip design. Blue Pearl provides high performance, innovati ve, automated tools to generate and validate criti cal ti ming and functi onal informati on early in the design cycle. Designers using Blue Pearl’s soluti ons can lower design risk, improve the quality of results, save ti me and reduce the cost of their chip design process.

45

CadenceDesignSystems, Inc. Booth # 1102 www.cadence.com

Cadence enables global electronic design innovati on and plays an essenti al role in the creati on of today’s integrated circuits and electronics. Customers use Cadence soft ware, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunicati ons equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offi ces, design centers, and research faciliti es around the world to serve the global electronics industry. More informati on about the company, its products, and services is available at www.cadence.com.

®Calypto Design Systems, Inc.Booth # 505 www.calypto.com

Calypto Design Systems empowers designers to create the highest quality and lowest power ASIC and FPGA hardware by providing best-in-class power opti mizati on, functi onal verifi cati on and synthesis products. These include PowerPro, SLEC and Catapult. These three product families off er soluti ons for the ESL Hardware Implementati on Flow, ranging from C/C++/SystemC high level Synthesis to power-opti mized RTL (Register Transfer Level). The Calypto soluti on is the most comprehensive ESL Implementati on Flow in the market. Come visit our booth for live demonstrati ons and more informati on.

46

DoulosBooth # 701

www.doulos.com

Doulos develops and delivers best-in-class training soluti ons and know-how for electronic system design and verifi cati on, covering standard languages and methodologies for system, hardware, and embedded soft ware designers. For more than 20 years Doulos has contributed to the success of more than 2,000 companies across over 50 countries. The natural partner for leading tool and technology companies, Doulos provides both public and private classes in North America, Europe and India and delivers on-site, team-based training in any locati on globally.

The Dini Group, Inc.Booth # 501

www.dinigroup.com

Dini Group was established in 1995 as a consulti ng company. While developing ASICs for various clients they saw the need for cost eff ecti ve logic emulati on platf orms and developed several of them. In 1998 they started selling these platf orms to ASIC developers and FPGA system users. From their offi ces in La Jolla, Dini Group employees have supplied over seven billion ASIC gates.

47

Duolog Technologies Ltd.Booth # 302

www.duolog.com

Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integrati on. We enable our customers to deliver integrated systems more quickly and cost eff ecti vely than their competi tors. Our innovati ve products and soluti ons allow for maximum producti vity and control throughout the enti re SoC lifecycle.

EDACafe Booth # 301

www.edacafe.com

Thousands of IC, and system designers visit EDACafé.com to learn about the latest company news and research the latest design tools and services. As the #1 EDA portal it att racts more than 75,000 unique visitors each month and leverages TechJobsCafe.com to bring you targeted job opportuniti es. EDACafé reaches out to more than 30,000+ EDA professionals with its daily CaféNews. EDACafe will be doing video interviews of industry executi ves at its DVCon booth. Please visit to hear all the conference buzz.

48

EVEBooth # 602

www.eve-team.com

EVE off ers a selecti on of hardware-assisted verifi cati on soluti ons, from accelerati on and fast emulati on to easy-to-use prototyping with the most cycles per dollar. Its products shorten the verifi cati on cycle of complex chips and electronic systems design and work with Verilog, SystemVerilog and VHDL-based simulators. ZeBu (for zero bugs) is accessible to SoC engineers and embedded soft ware developers and used throughout the design cycle by groups with modest budgets. Designs target a variety of fast-paced markets, including networking, communicati ons, multi -media, graphics, computer and consumer.

EsenciaTechnologiesBooth # 504

www.esenciatech.com

Esencia Technologies is a leading ASIC/FPGA IP and design service company. Our goal is to be the preferred partner for digital signal processing IP cores and design soluti ons, from concept to silicon. Esencia Technologies off ers a DSP IP core portf olio that stands out among the best in the market. We also off er turn-key design services from product specifi cati on to GDS2 and beyond. Our team has completed projects in leading process nodes for Fortune 500 companies as well as start-ups.

49

Forte Design SystemsBooth # 404

www.ForteDS.com

Forte Design Systems is a leading provider of soft ware products that enable design and verifi cati on at a higher level of abstracti on. Its innovati ve SystemC synthesis technology and intellectual property off erings allow design teams creati ng complex electronic chips and systems to improve design results while reducing their overall design and verifi cati on ti me. More than half of the top 20 worldwide systems and semiconductor companies use Forte’s products in producti on today for ASIC, SoC and FPGA design. For more informati on, visit www.ForteDS.com

Innovati ve Logic, Inc.Booth # 1104 www.inno-logic.com

Innovati ve Logic is the leading provider of reusable standard based IP soluti ons as well as high quality and reliable design services in ASIC, FPGA, and Embedded Systems Design. Our fl exible business model allows you to choose onsite, off site, or off shore consulti ng. We have experti se in Logic Design & Verifi cati on, Design for Testability (DFT), Circuit Design, Physical Design & Verifi cati on, Board Design, and FPGA Design. Innovati ve Logic is headquartered in Santa Clara, CA and has state of art Design Centers in Bangalore, India. For details, please visit our website at www.inno-logic.com.

50

Jasper Design Automati on, Inc.Booth # 601

www.jasper-da.com

Jasper Design Automati on delivers industry-leading EDA soft ware soluti ons for semiconductor design, verifi cati on, and reuse, based on state-of-the-art formal technology. Jasper soluti ons cover a wide range of applicati ons including formal property verifi cati on, RTL development, SoC integrati on, architecture validati on, post-silicon debug, verifi cati on IP, and property synthesis. Customers include worldwide leaders in wireless, consumer, computi ng, and networking electronics. Jasper technology has been an integral part of over 150 successful chip deployments. Visit us at DVCon – booth 601.

Mentor Graphics Corp.Booth # 801 www.mentor.com

Mentor Graphics delivers the most comprehensive and unifi ed advanced verifi cati on portf olio available: including Questa® for high performance simulati on and debug, verifi cati on management and coverage closure, low-power verifi cati on with UPF, CDC, Formal Verifi cati on, accelerated functi onal coverage, processor-based hardware verifi cati on and Veloce® for high-performance system verifi cati on. This portf olio combined with Mentor’s Vista™ ESL platf orm allows design and verifi cati on at higher levels of abstracti on. This comprehensive soluti on supports OVM and UVM. For more informati on visit www.mentor.com.

51

Missing Link Tools, LLCBooth # 605

www.missinglinktools.com

Missing Link Tools provides soft ware and services to accelerate your ti me to market and give you confi dence in your design. MLT’s verifi cati on management tool suite, EVOLVE, provides an Agile framework to manage all aspects of your verifi cati on & design - source control, tests, regressions, releases, coverage and testplans. With EVOLVE you can identi fy areas that need more testi ng, prevent schedule slippage, and tape out sooner. MLT’s customers see a 7-15X ROI for their investments with EVOLVE. Contact Missing Link Tools today for a demonstrati on: [email protected]

Methodics, Inc.Booth # 403 www.methodics.com

Methodics, Inc. is a leading provider of design data management (DM) tools that improve the effi ciency and collaborati on of integrated circuit (IC) design. Its SoC Integrator system is the fi rst integrated platf orm for managing SoC realizati on, reducing the ti me, complexity and costs involved in IP-based design approaches. Its DM tools integrate industry-standard soft ware confi gurati on management (SCM) tools, such as the Perforce® and Subversion® version control systems into the hardware design environment to provide a more effi cient global collaborati on experience. The privately held company has offi ces in the USA, Europe and Asia. For further informati on, visit www.methodics.com.

52

NextOp Soft ware, Inc.Booth # 402

www.nextopsoft ware.com

NextOp Soft ware, Inc. is focused on delivering asserti on-based verifi cati on soluti ons that allow design and verifi cati on teams to uncover bugs, expose functi onal coverage holes, and increase verifi cati on observability. NextOp’s BugScope full-chip asserti on synthesis soluti on is the fi rst product to automati cally generate whitebox asserti ons and functi onal coverage properti es in SVA, PSL and Verilog to drive progressive, targeted verifi cati on; these properti es are used to drive more eff ecti ve verifi cati on in existi ng simulati on, formal and emulati on fl ows.

Oski Technology, Inc.Booth # 805 www.oskitech.com

Oski Technology is the only IC verifi cati on services company to be focused on formal verifi cati on. With 20 years of experience, Oski has pioneered a unique methodology to deliver complete verifi cati on soluti ons that transform the approach to RTL verifi cati on, properly integrati ng formal into traditi onal simulati on-based and coverage-driven fl ows using simulati on-based metrics to defi ne formal coverage, increasing verifi cati on coverage and signifi cantly reducing schedule. Oski oft en fi nds corner-case bugs almost impossible to detect with simulati on. Oski’s customers include Cisco, Cypress, NVIDIA, Rambus, Xilinx.

53

PerfectVIPsBooth # 904 www.perfectvips.com

PerfectVIPs is a world-leading provider of Verifi cati on IP (VIP), delivering the fastest and most eff ecti ve verifi cati on soluti ons for interface, storage and mobile applicati ons – PCIe, USB, Ethernet, SAS, SATA, ONFi and more. Helping customers “Design Fast, but Verify Faster”, PerfectVIPs accelerates the verifi cati on process and delivers higher quality, reliability and producti vity while lowering risk, cost and verifi cati on delays to complex designs. Tools include verifi cati on engines, BFMs, test suites, checkers, scoreboards and more… PerfectVIPs brings together a global team with strong domain experti se, deep verifi cati on experience and superior customer services.

Paradigm Works, Inc.Booth # 1003

www.paradigm-works.com

Paradigm Works is a recognized provider of Chip Development (Design and Verifi cati on) Consulti ng Services, as well as Electronic Design Automati on Free Open Source Soft ware (EDA FOSS) and Supported EDA Soft ware. Paradigm Works IP and Services help to reduce development costs, quicken ti me-to-revenue, improve quality, and minimize schedule risk. Paradigm Works is headquartered in Andover, Massachusett s, serving leading global semiconductor and electronic systems clients around the world.

54

Semifore, Inc.Booth # 1004

www.semifore.com

Semifore Inc., “The Addressmap Experts,” provides the CSRSpec language and the CSRCompiler, a complete register design soluti on for hardware, soft ware, verifi cati on, and documentati on. Collaborati vely manage your design from a single source specifi cati on. CSRSpec, SystemRDL, IP-XACT, or Spreadsheet inputs generate: Verilog and VHDL RTL; Verilog, or C headers; Perl, IEEE IP-XACT; System Verilog for UVM, VMM and OVM; HTML web pages; and Word or Framemaker documentati on. Only Semifore gives your enti re team a complete, correct, up-to-date register design ecosystem.

Real Intent, Inc.Booth # 902

www.realintent.com

Real Intent is the leading provider of soft ware products that accelerate Early Functi onal Verifi cati on and Advanced Sign-off Verifi cati on of electronic designs. The company provides comprehensive Clock Domain Crossing soluti ons for ensuring synchronizati on between on-chip IP cores, as well as advanced RTL Analysis and Sign-off soluti ons for detecti ng and eliminati ng potenti al complex failure modes of today’s highly integrated SoCs. Real Intent’s products lead the market in high performance, capacity, report accuracy and comprehensiveness. For more informati on, please visit www.realintent.com.

55

SmartPlayBooth # 804

www.smartplayin.com

SmartPlay Inc. is a leading design services company with experti se in digital, analog, wireless soft ware and system design. SmartPlay’s design verifi cati on experti se assists its clients in developing verifi cati on environments for complex, multi million gate SoCs, thereby shortening the design cycle.With a team of 600+ employees and 6 design centers, SmartPlay is a preferred design services partner for several Fortune 500 and mid-sized semiconductor companies working on Graphics, Mobile, Multi media and Processor technologies. It has been rated among the Top 5 semiconductor companies in the Silicon India SI100 list in 2011. More details can be found on www.smartplayin.com

Sibridge TechnologiesBooth # 1005

www.sibridgetech.com

Sibridge Technologies provides innovati ve value added IP leveraged soluti ons for design, verifi cati on, and embedded systems development to worldwide semiconductors and electronic product companies. Sibridge off ers a large portf olio of design and verifi cati on IPs. The VIP portf olio comprises of PCI Express Gen 1.1/2.0/3.0, Ethernet 10M/100M/1G/10G/40G/100G, USB 2.0/3.0, MIPI, SATA II, AMBA3/4 AXI, AMBA2 AHB/APB, I2C, UART and SPI. Developed in nati ve SystemVerilog with opti onal support for OVM/VMM/UVM, the VIPs enable fi rst ti me right ASIC/FPGA soluti ons.

56

Synopsys, Inc.Booth # 1105 synopsys.com

Synopsys supplies the global electronics market with the soft ware, IP, prototyping and services used in semiconductor design, verifi cati on, validati on and manufacturing. Synopsys’ comprehensive soluti ons deliver powerful capabiliti es to solve increasingly diffi cult challenges across numerous verifi cati on domains and provide criti cal links to higher levels of verifi cati on & validati on at all levels. This winning mix of technology, models, integrators, best practi ces and ecosystem enables you to be more producti ve and bring compelling products to market more rapidly than ever before.

SpringSoft , Inc.Booth # 401

www.springsoft .com

SpringSoft specializes in unique automati on technologies for design and verifi cati on. The Verdi™ Automated Debug System cuts debug ti me in half, The Siloti ™ Visibility Automati on System speeds up simulati on, and the Certi tude™ Functi onal Qualifi cati on System ensures verifi cati on quality. The ProtoLink™ Probe Visualizer is a new verifi cati on soluti on that dramati cally increases design visibility and simplifi es debug of custom-designed and off -the-shelf FPGA-based protoype boards. Visit us at our booth to learn more about SpringSoft and our technology.

57

Vennsa Technologies, Inc.Booth # 502

www.vennsa.com

Accelerate Root-Cause and Triage DebuggingVennsa OnPoint™ is the industry’s fi rst and fully automated debugging environment. Root cause analysis and error triage of regression failures have been painful manual debugging tasks, unti l now. OnPoint’s breakthrough technology automati cally diagnoses verifi cati on failures and reports the source of errors to the user. It also generates a unique signature to automati cally bin regression failures based on their root cause. OnPoint improves producti vity dramati cally. It saves months of manual debugging eff ort and guarantees faster design closure.

Verifi c Design Automati onBooth # 705 www.verifi c.com

Verifi c Design Automati on has provided (System)Verilog and VHDL front-ends (parsers, analyzers, and elaborators) to EDA and semiconductor computers for many years. With more than 50 licensees worldwide, Verifi c’s parsers are being found in applicati ons ranging from simulati on and formal verifi cati on to logic synthesis and asserti on verifi cati on. With its newly minted Perl interface, Verifi c’s parsers are now also readily available for use by non C++ programmers. Whether you like Perl or C++, with Verifi c you can build your own SystemVerilog tools.

58

Wafer Space Booth # 905

www.waferspace.com

Wafer Space provides highly diff erenti ated design services (RTL to GDSII), design of complex VIP’s and methodology consulti ng for leading edge semiconductor companies. Wafer Space has a world-class engineering team with extensive experience in chip design and fl ow automati on. Wafer Space’s engineers have successfully completed many complex multi -million gate designs. Our key diff erenti ators are Turnkey Design Services using our proprietary fl ows, extensive chip design experience and experti se in project management. Wafer Space has offi ces in Bangalore, India and Portland, Oregon, USA.

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