dvr-310-s & dvr-510h-s training guide...dvr-310-s & dvr-510h-s training guide technical...
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DVR-310-S & DVR-510H-STraining Guide
Technical Training Department1925 East DominguezLong Beach, CA
3.
DVR-310-S BLOCK DIAGRAM
Overall Block Diagrams
4.
Overall Block Diagram for the last year’s modelDVR-7000
DDCEAudery
MPEGVideo Enc.
& Dvcodec
DVxcel AudioA/D
DVD-ROMEnc.
R3-Chip
H.A.A2-Chip
AVDecoderAV-1Chip
Tuner/Line
in
AudioD/A
CPU
Y/C/Comp Video Out
Audio Analog Out
MainCPU
Tuner/FL Control CPU
DVD-ROM Dec.& D-Servo
M63
PU&Mech.
GraphicsEngine
Vaikilt
DVD-ROMDec.
By-Chip
SR
AM
FLA
SH
SD
RA
M
FLA
SH
Writer
VIPGeorge
ATA I/F
Slalom
LDDrv.
DMAI/F
Ouroboros
VQE-5
1394Phy.
1394 Link ceLynx
1394(DV)
SRC
DIF Out (Coax,Opt.)Audio I/F
aprilia(2/2)
Audio I/Faprilia (1/2)
Y/Cb/Cr Video Out
INPUTOUTPUT
Dolby Digital AC3Consumer Encoder
Sampling RateConverter
Video A/D
IEEE1394
Video D/ANR, Progressive
Video Cont.GUI
ATAPI I/FAudio Cont.MAIN ASSY TUMJ ASSY
FL
5.
Overall Block DiagramDVR-310-S
AudioA/D Tuner
/Linein
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW DriveVideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
MAIN ASSY
TUMJ ASSY
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
INPUTOUTPUT
1394Phy.
1394 LinkDV-codec
SRCSampling Rate
Converter
IEEE1394
FL
6.
Overall Block DiagramDVR-510H-S
AudioA/D Tuner
/Linein
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW DriveVideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
MAIN ASSY
TUMJ ASSY
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
INPUTOUTPUT
1394Phy.
1394 LinkDV-codec
SRCSampling Rate
Converter
IEEE1394
Hard Disk Drive
FL
7.
SIGNAL FLOWRecord Tuner/ Line Input (KU)
AudioA/D
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW Drive
VideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
INPUTOUTPUT
1394Phy.
1394 LinkDV-codec
SRC
Hard Disk Drive
TVTuner
Line-InSel
StereoDecoder
InputSelector
Audio
Video
Select (L,R) or (SAP,SAP)for Video Format Recording
And select (L,L), (R,R) or (L,R)to Output
Select (L,R) or (Mono+SAP)for VR Format Recording
DVR-510H-S
8.
SIGNAL FLOWPlayback
AudioA/D
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW Drive
VideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
OUTPUT
1394Phy.
1394 LinkDV-codec
SRC
Hard Disk Drive
TVTuner
Line-InSel
StereoDecoder
InputSelector
Audio
Video
Convert Sampling Ratefrom 48kHz to 32kHz
DVD-VRDVD-Video
DVR-510H-S
9.
SIGNAL FLOWRecording Monitor (DV Input)
AudioA/D
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW Drive
VideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
INPUTOUTPUT
1394Phy.
1394 LinkDV-codec
SRC
Hard Disk Drive
TVTuner
Line-InSel
StereoDecoder
InputSelector
Audio
Video
Convert Sampling Ratefrom 32kHz to 48kHz
DVR-510H-S
10.
SIGNAL FLOWRecording Monitor (Tuner/ Line/ DV Input)
AudioA/D
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW Drive
VideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
INPUTOUTPUT
1394Phy.
1394 LinkDV-codec
SRC
Hard Disk Drive
TVTuner
Line-InSel
StereoDecoder
InputSelector
Audio
Video
DVR-510H-S
11.
SIGNAL FLOWCD playback
AudioA/D
AudioD/A
Y/C/CVBS Video Out
Audio Analog Out
Tuner/FL Control CPU
ATA
SD
RA
M25
6Mb
AV-codecLSI
M65672WG
DIF Out (Opt.)
Y/Cb/Cr Video Out
DVD-R/RW Drive
VideoADC3D Y/C
DNR(REC)AV-Enc.
AV-Dec.
ProgressiveConverter
ATA I/F 32bit RISCCPU
3D DNR(PB)
GraphicsEngine
FrameTBC
VideoDAC
PAL/NTSCEncoder
PAL/NTSCDecoder
BackupSRAM4Mb
FLASH64Mb
CPUSDRAM128Mb
EN
CS
DR
AM
128M
b
DE
CS
DR
AM
64M
b
OUTPUT
1394Phy.
1394 LinkDV-codec
SRC
Hard Disk Drive
TVTuner
Line-InSel
StereoDecoder
InputSelector
Audio
Video
CD DigitalPCMOUT
DVR-510H-S
12.
DVR-310-S BLOCK DIAGRAM
CPU Construction
13.
CPU ConstructionDVR-310-S CPU Control Assignment
1 Chip System CODECIC1001
TUFLu-CON
WriterCPU
Tuner, FL, Key controlsTime management and
Timer REC management.
ATA
PI B
US
R6 Writer UINTWriter System control
Control system wide such as Recording & Playback operation
including each CPU control, ATA I/F, User I/F, etc.
communicationWith ATAPI command
Serial communication
14.
DVR-310-S BLOCK DIAGRAM
Circuit Board Layout
15.
Circuit Board Layout
FAN
DRIVE ASSY R6 (VXX2898)
Power Supply Unit
(VWR1373)
FRJB ASSY(VWV1964)
REAR
FRONT
(Only for PAL model)
TUMJ ASSY(VWV1960)
HDD(For DVR-510H-S)
MAIN ASSY(VWV1952)
FLKY ASSY(VWG2443)6
9
16.
Device Layout MAIN ASSY (Side A)
IC5202LINK/DVCODEC IC5101
Phy
X5101
IC5204DV SDRAM
CN
1901
CN
4501
CN
4401
CN4001
X420
1
VC4201
IC3301
IC31
01
CN5102
Writer Unit
27M Master Clock
Sampling Rate Converter
Audio ADC
Master ClockADJ
CN3001 CN2001
Power Supply
CN
4601
TUMJ TUMJ
For Serial DL
HDD
DVJB ASSY
17.
Device Layout MAIN ASSY (Side B)
IC10011-chip System Codec
[BGA]
IC1301ENC SDRAM
IC1103Backup SRAM
IC1201DEC SDRAM
IC11
01C
PU S
DR
AM
IC14
01A
TA S
DR
AM
IC14
21A
TA S
DR
AM
IC11
02FL
ASH
IC32
01
IC1Audio DAC
18.
DVR-310-S BLOCK DIAGRAM
FL Circuit
19.
FL CIRCUITPower Supply Distribution
There isNO FL DimmerNO LED (DVR-310-S)NO JOG.
FLDC-
V+5E, V+5FL
V-28V
FLDC+
FLDV –22V
FL Driver, Remote Sensor, SWsContinuous power
DC 5V
FL DriverDC –28V
FL DC 5.0V
CircuitVoltageSignal name
20.
DVR-310-S BLOCK DIAGRAM
TUMJ ASSY
21.
AV Signal FlowTUMJ Assy
VIDEO
SYNC《 TUFL u com》
IC3301VIDEO
SELECTOR
LA73030
CVBS/Y/C
CVBS/Y/C
CVBS/Y/C
L/R
JA2832IN 1
JA1301:SJA1302:V
IN 2(Front)
JA2832IN 3
L/R
L/R
JA2832IN 1
JA1302IN 2
(Front)
JA2832IN 3
UV TUNERVXF1022
MPX DECODERCXA2064M
IC2801AUDIO
SELECTORwith
ELECTRICA.T.T.
LC75342M
MAINUNIT
Y
C
L/R
CVBS
L/R
IC2001TUFL μ-CON
PD5966
IC2251EEP ROM
DIGITAL OUTCoax &Opto
JA3551OUT 1&2
JA3551OUT 1&2
JA3551OUT 1&2
CN3581D OUT
Y/Cb/Cr
Y
Y
Cb
Cr
V
C
CVBS
Y/CIC3501VIDEO
DRIVER
LA73054
ANALOG L/R
SPDIF
IC2271RTC
SYNCMAIN
《 TUFL u com》SYNCAFT
《 TUFLu com》SELV1, SELV2,
SELV3, SWSTBYAUDIOCONT
S1《 TUFL u com》
《 TUFL u com》EVOLCLK,
EVOLDATA,EVOLCE
22.
TUMJ ASSYTUNER u-CON etc.
* TUFL u-con There are 2 type of TUFL u-con IC for DVR-310-S. (1) Flash type (It is possible to update the firmware.) [Service mode: F] (2) Mask type (Part number label on the IC) [Service mode: M]
TUFL u-con IC may easy to be damaged by electrostatic.
* EEPROM (IC2251)
For backup Tuner data.(Pre-set CH, AFT ON/OFF, Skip CH etc.)
Information about timed recording
Other information(state of Volume, remote control mode and last Input positions (Line/ Tuner etc)
* Lithium battery Life time of battery is approx. 5 years.Power of RTC and Backup SRAM are supplied by Lithium battery when AC cord is disconnected.
23.
TUMJ ASSYCheck point
[Symptom] No picture of Terrestrial broadcasting
[Point] Check V+5TU. Check TUON signal, Q3006.
[Symptom]Black squelch at a specific channel# It becomes black squelch on picture when field electric intensity is low.
[Point] Check Field electric intensity.IC3301(YOUT)! Q3362(SYNCAFT)! TUFLμ-CONCount number of H_SYNC700/Frame ! Detect low field intensity ! squelch ON600/Frame ! Detect as normal !Squelch OFF
24.
DVR-310-S BLOCK DIAGRAM
MAIN ASSY
25.
MAIN BOARDBlock Diagram
IC2301AGC/ ACC
BA7655AF
IC1001PRISM
M65672WG
VIDEO DECODER
VIDEO ENCODER
AUDIOI/F
STREAM I/F
MPEG CODEC
SYSTEM CONTROLμ-CON
ATAPII/F
CVBSIN
YCYCbCr
BCKILRCKI
BCKOLRCKOADATAO
AT1DATA0-15
VMCLK AMCLK136M
AMCLK233M
AUDIO DECODER
AUDIO ENCODER
IC4205MASTERCLOCK
CLK: 27M
VIDEOIC3402PLL
CLK: 33/36MAUDIO27MCLKCONT
CVBS/YC
IC2501ALTERAPDY081A
CSYNCIN
IC310196kHz/24bit
A/D ConverterAK5381VT
ADATAI
IC3201192kHz/24bitD/A ConverterPCM1742KE
IC2331VIDEO AMP
MM1508XN
CVBS/Y
R6WRITER
CIN
Q2101-2105VIDEO
BUFFER
YCYCbCr
IC3251AUDIO BUFFER
LR
CN2001IC1201
DEC SDRAM64Mb
CLK: 108M
20
2426
468
1012
2830
1614
IC1301ENC SDRAM
128MbCLK: 121.5M
IC1401ATA SDRAM
256MbCLK: 81M
HOSTBUS
CLK: 54M
IC1101CPU SDRAM
128MbL LR R
IC1102FLASH64Mb
IC1103SRAM4Mb
26.
Main AssyCheck Point
[Symptom] No Picture, No Audio[Point] Check In & Out with Analogue signal of Video and Audio
@CN2001Video Signal 24pin ! V/YIN 26pin ! CIN 04pin ! Y 06pin ! COUT 08pin ! Y 10pin ! Cb 12pin ! CrAudio Signal 14pin ! ARMtoT 16pin ! ALMtoT 28pin ! LCHIN 30pin ! RCHIN
[Symptom] Beat noise on a monitor[Note] CN4702 of MAIN ASSY is not connected to MHLP Assy properly.
S/Composite output
Component Output
27.
Main AssyCheck Point
[Symptom] Recording NG[Check point] ENC SDRAM
[Symptom] Playback picture NG[Check point] DEC SDRAM
[Symptom] It does not work when power is turned on.[Check point] HOST BUS lines, TUFLμ-CON, PRISM IC
[Symptom] “LSI NG” is appeared on FL display.[Check point] Check DATA & Address BUS lines for the flowing IC.
* CPU SDRAM(IC1101), SRAM(IC1103), ATA SDRAM(IC1401)
[Symptom] “MONITOR” is appeared on FL display.[Check point] DATA in FLASH ROM may be faulty.
Down load the firmware by PC with interface JIG, or replace Flash ROM IC.* If this error is appeared, it is not able to use DISC downloading method.
[Symptom] No color on picture[Check point] Check adjustment of 27MHz Master Clock.
28.
MAIN BOARDMEMORIZED DATA
CPU SDRAM (IC1101)The execution area and working area of a program
FLASH ROM (IC1102)The storing area of a program code and setting information
SRAM (IC1103)The working area for record,and the storing area of setting information (backup RAM)
DEC SDRAM (IC1201)The working area of MPEG playback and OSD/ Thumbnail(OSD is mainly for Disc Menu creation in Video mode)
ENC SDRAM (IC1301)The working area of MPEG recording and analog input and output (AVIO) .
ATA SDRAM (IC1401)The working area of ATA/ OSD2/ Audio TBC(OSD2 is for all GUI)
ATA SDRAM (IC1421)This is only for an HDD modelThe working area about HDD operation
29.
MAIN BOARDPRISM LSI Function
[Functions]
* 10bit*27MHz(1ch),8bit*27MHz(3ch) Video ADC* PAL/NTSC Decoder* 3D Y/C Separator* Frame TBC* 3D DNR* MPEG Video Encoder* Dolby Digital Consumer Encoder* Graphics Engine (OSD, Scaling, Mixing)* MPEG Video Decoder* Audio Decoder (AC-3, MPEG)* PAL/NTSC Encoder* 10bit*54MHz(5ch) Video DAC* Progressive converter* Audio I/F* Drive I/F(ATA/ATAPI, 2ch)* Main CPU (32bit RISC, 54MHz)
1Chip Codec LSI (M65672WG) (IC1001)
Previous model used 11 LSI’s.
Process : 0.13μm、CMOS6 layer(6Cu)
Gate size : approx. 400Mil. Gate(exc. memory)
Power supply: 1.2V for internal,
3.3V for external(5V max)
Package : 564pin PBGA
30.
MAIN BOARDInternal Block Diagram for PRIZM LSI
HDD
DV-codec
OSD
VideoSelect
&ScalingMixing
AV Dec.
DriveI/F
AV Enc.
DAC
Audio I/FAudio ADC
M65672WG
Audio DAC
ADCDNR
SRC
DVD-R/RW
Drive
TBC
N/PEnc.
DAC525P
N/PDec. 3D Y/C
3DDNR
CPU
1394Phy
31.
MAIN BOARDLSI Specification for DV
3. Audio Sampling Rate Converter (IC3301)Voltage Only 3.3VFunction the following sampling rates are converted
in order to absorb frequency deflection. 48kHz (DV Clock) ! 48kHz (Recorder Clock)32kHz (DV Clock) ! 48kHz (Recorder Clock)
1. DV CODEC / IEEE1394 Link LSI (IC5202)Voltage I/O: 3.3V
Internal: 2.5VFunction DV Decode
DV EncodeIEEE1394 Link Layer ControlIEC61883 AV/C Command Control(The control command sending
function to a DV camcorder etc.)CPU (For IEEE1394 processing)
2. IEEE1394 PHY LSI (IC5101)Voltage Only 3.3VFunction IEEE1394 conformity physical layer control LSI
24.576MHz (PLL for IEEE1394) built-in Crystal oscillation circuit(Crystal oscillator is external)
32.
MAIN BOARDDV Block Diagram
To Writer
HOST BUS
To H.D.D
DV
IC14
01A
TA S
DR
AM
IC14
21A
TA S
DR
AM
CN
4401
CN
4501
IC1001PRISM
ATA
BUS
IC1102FLASH
IC1103SRAM
IC1101CPU
SDRAM
IC2501ALTERA
IC5202LINK
IC5101Phy
CN
5102IC5204
DV SDRAM
IC1301ENC
SDRAM
IC1201DEC
SDRAM
MCL
VCLKI
SCL
HCLK
ARCLK
DCLK0
ECLK0
IC33
01S
RC
SRC**O
SRC**I
IC4205Play Mster clock
IC4206
AMCLK2
IC3402PLL IC
27M
24M
VMCLKI
AMCLK133M
36M
IC3201DAC
IC3101A/D
33/36M
AD
CC
LKO
IC34
03
X4102Input Mster
clock
AD
MC
LKI 27M
IC4101
DV
PLL
CK
(AD
MC
LKI)
DV
VP
WM
IC4009
DVVCLKO
AUDIO LR OUT
AUDIO LR IN
VIDEO Y,C,Yp,Cb,Cr OUT
IC3251
VIDEO Y,C IN
CN
2001
CN3
001
TO TUNER u-COM
CN1901
SE
RIA
L
54M
54M
81M
36M
121.5M
108M
Q2101~5
Q2402~3
IC2301,IC2331,Q2203
IC3001
Q222
24.576M
33.
MAIN BOARDSignal Flow (DV INPUT)
DVPLLCK
IC10011-chip
CODEC LSI
(PRISM)
LPF
IC3301SRC
VCO
DVADATA , DVLRCK , DVBCK
DVAMCLKI
DVAMCLKO
DVVIDEO[7:0]
DVVCLKO
DVVCLKI
XRSTDV
RX3
APWM
LPF VCXOVPWM
VCLKI
HS_CLK
AMCLK48
AMCLK44
IC5202LINK/DvcodecμPD72893A
APLL_CK SRCDATAOSRCLRCKOSRCBCKO
SRCDATAISRCLRCKISRCBCKI
IC5341
IC5341
AudioD/A
Video OUT
Audio OUT
12.288MHz
27MHz
DV IN/OUT Switching SignalIt is “HI” in DV input
SRC communicateswith the 1-chip CODEC LSI
Video Encoder
IC5202 worksin DV DECODE mode
27M clocksynchronized withDV video source
Host Bus
X’tal24.576MHz HDATA[15:0]
HCS3 , DQMWS0 , HOE , HADRS[10:1]IC5101
PHYμPD72852
PHY_D [7:0]
CTL [1:0] HWAIT , INT4 , INT5
SCLK
LREQ
LPS
LINKON
DV
IC5204SDRAM16Mbit
16bit/54MHz
34.
MAIN BOARDSignal Flow (DV OUTPUT)
IC10011-chip
CODEC LSI
(PRISM)
LPF
IC3301SRC
VCO
DVADATA , DVLRCK , DVBCK
DVAMCLKI
DVVIDEO[7:0]
DVVCLKI
XRSTDV
RX3
APWM
LPF VCXOVPWM
VCLKI
HS_CLK
AMCLK48
AMCLK44
IC5202LINK/DvcodecμPD72893A
IC5341
IC5341
12.288MHz
27MHz
DV IN/OUT Switching SignalIt is “LOW” in DV output
DVVCLKO
DVPLLCK
DVAMCLKO
APLL_CK
IC5202 worksin DV ENCODE mode
X’tal24.576MHz HDATA[15:0]
HCS3 , DQMWS0 , HOE , HADRS[10:1]PHY_D [7:0]IC5101
PHYμPD72852
CTL [1:0] HWAIT , INT4 , INT5
SCLK
LREQ
LPS
LINKON
DV
IC5204SDRAM16Mbit
16bit/54MHz
35.
DVR-310-S BLOCK DIAGRAM
Audio Circuits
36.
Audio CircuitBasic Block
SRC
AudioA/D
TVTuner
Audio Analog Out
MainCPU
Tuner/FL Control CPU
SR
AM
FLA
SH
SD
RA
M
1394(DV)
DIF Out
InputSelector
AndVR
AudioMultiplexDecoder
DVcodec
DDCDpart
ATA I/F
DDCEPart
AudioI/F
AudioD/A
HDD
Writer
AK5381VT
Output(Main,Sub)
or (L,R)
Dolby Digital Consumer Encoder and Decoder M65672WG
0dB,±3dB,±6dB(Exp. Tuner)
CXA2020M
LC75342M
PCM1742KE
37.
Audio CircuitSignal flow
SRC
AudioA/D
TVTuner
Audio Analog Out
MainCPU
Tuner/FL Control CPU
SR
AM
FLA
SH
SD
RA
M
1394(DV)
DIF Out
InputSelector
AndVR
AudioMultiplexDecoder
DVcodec
DDCDpart
ATA I/F
DDCEPart
AudioI/F
AudioD/A
HDD
Writer
Through Pass
38.
Audio CircuitSignal flow
SRC
AudioA/D
TVTuner
Audio Analog Out
MainCPU
Tuner/FL Control CPU
SR
AM
FLA
SH
SD
RA
M
1394(DV)
DIF Out
InputSelector
AndVR
AudioMultiplexDecoder
DVcodec
DDCDpart
ATA I/F
DDCEPart
AudioI/F
AudioD/A
HDD
Writer
Recording Pass
39.
Audio CircuitSignal flow
SRC
AudioA/D
TVTuner
Audio Analog Out
MainCPU
Tuner/FL Control CPU
SR
AM
FLA
SH
SD
RA
M
1394(DV)
DIF Out
InputSelector
AndVR
AudioMultiplexDecoder
DVcodec
DDCDpart
ATA I/F
DDCEPart
AudioI/F
AudioD/A
HDD
Writer
Playback Pass
40.
Audio Circuit
Audio SpecificationNorth America , PX [BTSC+SAP]
Input Source
Carrier Signal Video Recording DVD-Video
Disc Record HDDUser Select
BTSCMono
Stereo
BTSC+SAP
Mono+SAP
Don’t Care
Stereo+SAP
Monoor
Stereo
Mono+SAP
Stereo+SAPSAP
2/0 2/0
2/0 2/0
1+1 2/0 [#1]
Principal Country : U.S.A, CANADA, PX
#1 : Only SAP will record as 2/0mode by User’s setting in advance.
41.
DVR-310-S BLOCK DIAGRAM
Power Supply Unit
42.
POWER SUPPLY UNITPower supply Assy
[Major Power Supply] (Refer to SM page 20)* TUMJ EV+6V ! V+3_3E(3.3V)! Backup for RTC(RTC) EV+6V ! V+5E(5V) ! INPUT & Display(FL Driver, F-Key, Remote Sensor) V+37E(37V) ! Tuner Module EV+6V ! V+5M(5V) ! Tuner u com EV+6V ! V+5VI(5V) ! Video IN(Video Selector) SW+6V! V+5VO(5V) ! Video Out(Video Driver) SW+13! V+9(9V) ! Audio(Audio Selector, MPX decoder) SW+13! V+13SW(13V) ! DC FAN motor
* MAIN SW+2.4V! V+PRA(1.2V) ! For PRISM IC SW+4V! V+3D(3.3V) ! Digital I/O(SDRAM, SRAM, Flash) SW+4V! V+3V(3.3V) ! Digital I/O(PRISM) SW+6V! V+5A(5V) ! Audio process line(DAC, ADC) SW+6V! V+5D(5V) ! ATAPI BUS line(R6 Writer) SW+13! V+12A(12V) ! Audio Output
43.
POWER SUPPLY UNITCheck point
[Service] (Refer to SM p46) Only Fuse on secondary circuit can be replaced for repair.
If other components parts are faulty, replace whole POWER SUPPLY UNIT for safety regulation. P101 ! AEK7050 (3A) P201, P401, P403, P404 ! AEK7067 (2A)
[ Note ] CN204(Yellow) is vacant for DVR-310H.
This connector is used for HDD unit of DVR-510H.
P101! SW+4V P201! SW+2.4V P401! EV+6V P403! SW+5V ! R6 WRITER +5V P404! SW+5V ! non
44.
DVR-310-S BLOCK DIAGRAM
DVD-R/RW Writer Unit
45.
Block Diagram for DVD writerR6 Writer
Spindle Motor
DISC
Pick-Up
ActuatorFocus /Tracking
Stepping Motor
Power Supply+5V / +12V
ATAPI
Line Out
RFNECμPC3320GCRF,TE,FEAPC,OPCWobble
Device Configuration Jumper
4 in 1 Connector
New
DSPNECμPD63620GMDVD/CD DecoderDVD/CD Encoder ATAPIReadChnannelWobble DPLLSERVO
CPUMitsubishiM30700FJLGP
768k
6CH DriverMitsubisiM63028FP
Loading Motor
RegulatorX2
Main PCB Assembly
650n Laser
780n LaserLD DriverElantec
FM OEIC
Digital Out(Optional)
Head Phone AmpNJM2769AM
Head Phone
RFTE,FE
SL
FD,TD,MD
Serial LineBus Line
IDE Bus Line
Front PCB Assembly
DD converterX 2
DRAM16M
AMP
LC TILT
PU Controler
OEIC
AWOBBLE
TempSencer
New
LVDSDRIVER
LVDS RECIEVER
SHF
SHF
46.
R6 WRITER UNITBasic concept
[ Pickup ](1) LCD Tilt servo system(2) LD driver with Strategy control
[ Pickup ](1) LCD Tilt servo system(2) LD driver with Strategy control
[ Traverse Mechanism ](1) DRA(Dynamic Resonance Absorber)to reduce mechanism vibration.(2) Deletion of Tilt mechanism
[ Traverse Mechanism ](1) DRA(Dynamic Resonance Absorber)to reduce mechanism vibration.(2) Deletion of Tilt mechanism
[ Circuits] (1) 2 chip S-Combo LSI(2) OPC(Optimum Power Control) circuit for X2 RW Disc(3) MAIN & FRONT Assy
[ Circuits] (1) 2 chip S-Combo LSI(2) OPC(Optimum Power Control) circuit for X2 RW Disc(3) MAIN & FRONT Assy
47.
R6 WRITER UNITCheck point
[Symptom] Not working for DVD[Note] Check whether DVD writer is recognized with Test mode. (S/M 60 page)
[Symptom] Reading and writing problem for Discs.[Check point] Check error rate by service mode.
Check LD(Laser Diode) current by test mode.(RF level is only for your reference, use to compare with other model.)
Notes
1. Protection by temperature detection (75 degrees C)Operation: Power OFF
"stopped operation by the temperature rise“ on screen