dynamic voltage and frequency scaling...
TRANSCRIPT
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
1
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Dynamic Voltage and FrequencyScaling Architecture for UnitsIntegration within a GALS NoC
Edith Beigné
F. Clermidy, S. Miermont, P. Vivet
2008
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
2
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
3
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
4
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Dynamic and Static power consumption issues
Dynamic Power Consumption
Static Power Consumption
Dynamic power consumption reduction :Reduce : switching activity, capacitances, supply voltage, frequency
Static power consumption reduction :Reduce : supply voltage, dominant leakage currents : ISTH, IGIDL, IGATEMulti VTH design
Low power techniques must exists at all design levels fromarchitecture to physical implementation
We propose a fully integrated solution to control locallydynamic and static power at Unit level within a GALS NoC
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
5
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
6
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC architecture for DVFS support (1)NoC architectureA fully asynchronous Network-on-Chip
IP units are synchronous islands usingprogrammable Local Clock Generator
Within the IP unit :Synchronization is done thanks to Pausable Clock
A Power Unit manages internal Vcore generatedusing external Vhigh and Vlow
A Network Interface is in charge of NoC communicationsLocal Power Management
Main CPU in charge of global power management
SAS
NI
Unit E
LCG
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Unit E
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Unit E
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Unit E
LCG
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CPU
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CPU
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CPU
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CPU
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Unit D
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Unit D
LCG
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Unit A
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Unit A
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Unit A
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Unit B
LCG
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Unit B
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LCG
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Unit C
LCG
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Unit C
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Unit C
LCG
POWER UNIT
Units_offUnits_rst
POWER UNITPOWER UNIT
POWER UNIT POWER UNIT POWER UNIT
VHIGHVLOW
NoC Architecture
Local fine grain power management can beexecuted during IP computation and communication
independently from the others
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
7
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC architecture for DVFS (2)Main Principles
SAS
NI
Unit E
LCG
SAS
NI
Unit E
LCG
NI
Unit E
LCG
NI
Unit E
LCG
SAS
NI
CPU
LCG
SAS
NI
CPU
LCG
NI
CPU
LCG
NI
CPU
LCG
SAS
NI
Unit D
LCG
SAS
NI
Unit D
LCG
NI
Unit D
LCG
NI
Unit D
LCG
SAS
NI
Unit A
LCG
SAS
NI
Unit A
LCG
NI
Unit A
LCG
NI
Unit A
LCG
SAS
NI
Unit B
LCG
SAS
NI
Unit B
LCG
NI
Unit B
LCG
NI
Unit B
LCG
SAS
NI
Unit C
LCG
SAS
NI
Unit C
LCG
NI
Unit C
LCG
NI
Unit C
LCG
POWER UNIT
Units_offUnits_rst
POWER UNITPOWER UNIT
POWER UNIT POWER UNIT POWER UNIT
VHIGHVLOW
Each synchronous IP is an independant power and frequencydomain
A local fine grain Dynamic Voltage Scaling :Implementation of a local hardware controller to control transitions between
Vhigh and VlowEnsures smooth DVS transitions for IP safe computation
A local fine grain Dynamic Frequency Scaling :Automatic frequency scalingUse of clock generation re-programming to find the optimal V/F point of
operation
Thanks to pausable clock technique, IP unit continues itsoperation during DVFS phases
GALS architecture and local clock generation is a natural enabler for easy local DVFS
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
8
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
9
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit architecture
Each IP core encapsulated withNetwork Interface,Test Wrapper,Pausable Clock,Power Supply Unit
IP units have 5 supply modes Init : reset at Vhigh (1.2V)High : Vhigh supplyLow : Vlow supply (0.8V)Hopping : switch Vhigh / Vlow for DVFSIdle : retention state at Vlow (no clock) Off : stand-by mode
xxx_test
V-HIGH V-LOWcut_off
test_scan
xxx_top
SynchronousNOC
protocol
POWERSUPPLY
UNIT
pwc_
cfg
xxx_unit
SYNCHRONOUSIP CORENETWORK
INTERFACE
LOWPOWER
MANAGER
GATED CLOCKidle
clk_coreclk_n
idl_c
fg
NO
C T
EST
WR
APP
ERpw
c_hl
PAUSABLE CLOCKGENERATOR
DELAY LINE PROG
SAS
IN
TER
FAC
E
delay_ctrl
clk_gene
xxx_sas
ISO
LATI
ON
C
ELLS
clock pause req/acksignals
reset_n
ANOC
4-phase /
4-rail
link
V-CORE POWER DOMAIN
PausableClock
Interface
ULTRA-CUT-OFF
VDD SELECTION
xxx_core
SAS
NI
Unit E
LCG
SAS
NI
Unit E
LCG
NI
Unit E
LCG
NI
Unit E
LCG
SAS
NI
CPU
LCG
SAS
NI
CPU
LCG
NI
CPU
LCG
NI
CPU
LCG
SAS
NI
Unit D
LCG
SAS
NI
Unit D
LCG
NI
Unit D
LCG
NI
Unit D
LCG
SAS
NI
Unit A
LCG
SAS
NI
Unit A
LCG
NI
Unit A
LCG
NI
Unit A
LCG
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NI
Unit B
LCG
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NI
Unit B
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Unit B
LCG
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NIUnit C
LCG
SAS
NIUnit C
LCG
NIUnit C
LCG
NIUnit C
LCG
POWER UNIT
Units_offUnits_rst
POWER UNITPOWER UNIT
POWER UNIT POWER UNIT POWER UNIT
VHIGHVLOW
NoC Unit Architecture
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
10
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
11
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit design (1)
Local Power Manager handles unit power modesA set of programmable registers, through the NoCConfiguration of :
Programmable delay linePower Supply Unit
Pulse Width modulator used to control the Hopping mode
Local Power Manager
PWM
Frequency
Voltage0
Vhigh
Vlow
0
FhighFlow
0
1
0
1Clk
xxx_top
xxx_test
V-HIGH V-LOWcut_off
test_scan
SynchronousNOC
protocol
POWERSUPPLY
UNIT
pwc_
cfg
xxx_unit
SYNCHRONOUSIP CORENETWORK
INTERFACE
LOWPOWER
MANAGER
GATED CLOCKidle
clk_coreclk_n
idl_c
fg
NO
C T
EST
WR
APP
ERpw
c_hl
PAUSABLE CLOCKGENERATOR
DELAY LINE PROG
SAS
IN
TER
FAC
E
delay_ctrl
clk_gene
xxx_sas
ISO
LATI
ON
C
ELLS
clock pause req/acksignals
reset_n
V-CORE POWER DOMAIN
PausableClock
Interface
ULTRA-CUT-OFF
VDD SELECTION
xxx_core
Hopping Operation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
12
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit design (2)
Power Supply Unit manages VcoreTwo power switches Thigh and Tlow LVT transistorsA Hopping UnitAn Ultra Cut-Off Generator
Power Supply Unit
xxx_test
V-HIGH V-LOWcut_off
test_scan
xxx_top
SynchronousNOC
protocol
POWERSUPPLY
UNIT
pwc_
cfg
xxx_unit
SYNCHRONOUSIP CORENETWORK
INTERFACE
LOWPOWER
MANAGER
GATED CLOCKidle
clk_coreclk_n
idl_c
fg
NO
C T
EST
WR
APP
ERpw
c_hl
PAUSABLE CLOCKGENERATOR
DELAY LINE PROG
SAS
IN
TER
FAC
E
delay_ctrl
clk_gene
xxx_sas
ISO
LATI
ON
C
ELLS
clock pause req/acksignals
reset_n
V-CORE POWER DOMAIN
PausableClock
Interface
ULTRA-CUT-OFF
VDD SELECTION
xxx_core
Vhigh Vlow
Thigh (xN) Tlow
POWERSWITCHES
Vcore
+-
SOFT-SWITCH
D•AVref
CONTROL
HopClk
from LPM
ULTRACUT-OFF
Unit
Cut-Off
Vuco
UCO clock
UC
OH
OPP
ING
UN
ITPower Supply Unit
Local Power Supply Unit offers a safe control of internal power supply depending on pre-defined power modes
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
13
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit design (3)Hopping Unit
Computing power
Ele
ctric
al p
ower
Vlow, Flow
Vhigh, Fhigh
Vdd-HoppingEnergy per operation scales with V²
Decrease Voltage (and Frequency) to be energy efficient
« Triple state » power supplyProposed by Tokyo Univ. (2000)
But was not integrated on chipUse of two PMOS power switches
Vhigh (1.2 V), Vlow (0.7 V), or off (0 V)
Switch between Vhigh and Vlow :Transitions take less than 100 nsMean speed / mean power of the IP is programmed by a PWM
Compatible with synchronous and asynchronous IPsFor GALS system : coordination done with local clock generator
Can easily be integrated in any CMOS circuitNo inductor contrary to traditional DC/DC convertersNo capacitor contrary to charge pump implementation
Vavg,Favg
hopphopslp(8)
hoppsync
hopslpsync(8)
pwc_hl
enclkhopspd(8)
enssupnotdown
fullonfulloff
testscanhtestscanlforcehighforcelow
cmp
encmp
cmdl
enrefselec
vcore
ref
vlowvhigh
cmdlbuf
cmdhbuf(20)cmdss(20)
29
9
4
20 20
2
2
8
softswitch
hoppingctrl
resy
nc comparator
pwrdriver
pow
ersw
itch
clkgen
refer
from
lpM
anag
erto
LC
G
from outsideof the bloc
to core
Vhigh Vlow
Thigh (xN) Tlow
POWERSWITCHES
Vcore
+-
SOFT-SWITCH
D•AVref
CONTROL
HopClk
from LPM
ULTRACUT-OFF
Unit
Cut-Off
Vuco
UCO clock
UC
OH
OPP
ING
UN
IT
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
14
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit design (4)Ultra Cut-Off Generator
Vhigh Vlow
Thigh (xN) Tlow
POWERSWITCHES
Vcore
+-
SOFT-SWITCH
D•AVref
CONTROL
HopClk
from LPM
ULTRACUT-OFF
Unit
Cut-Off
Vuco
UCO clock
UC
OH
OPP
ING
UN
IT
When reverse polarizing the gate, the leakage current goes through a minimum:
The subthreshold current ISTH diminishes,The IGIDL current increases.
The optimal polarization point varies with the temperature, the supply voltage and the process corners
The proposed UCO generator automatically polarizes the gate of the Power switch to its point of minimum leakage
two reference transistors respectively representing leakage currentsa current sense amplifier to compare those currentsa charge pump to generate the polarization voltage VP
Compensates for temperature variation, alleviates corners variations.
The gate oxide reliability is considered by introducing a passive stress reduction mechanism
1,00E-12
1,00E-11
1,00E-10
1,00E-09
1,00E-08
1,00E-07
1,20 1,30 1,40 1,50 1,60 1,70 1,80
Gate voltage (V)
Cur
rent
(A)
25°C45°C65°C85°C105°C125°C
T
Variation of the total leakage current with temperature.
1,00E-11
1,00E-10
1,00E-09
1,00E-08
1,00E-07
-0,8 -0,6 -0,4 -0,2 0
VGS (V)
ID (A
)
FF
TT
SS
Variation of the total leakage current with corner.
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
15
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit design (5)
Pause temporary the clock when a transfer (NoC) or a supply switch is required (LPM)
Based on :Two GALS ports : Synchronous-to Asynchronous and Asynchronous-to-SynchonousA programmable delay lineA pausable clock generator
Pausable Clock Generator arbitrates pause requests
xxx_test
V-HIGH V-LOWcut_off
test_scan
xxx_top
SynchronousNOC
protocol
POWERSUPPLY
UNIT
pwc_
cfg
xxx_unit
SYNCHRONOUSIP CORENETWORK
INTERFACE
LOWPOWER
MANAGER
GATED CLOCKidle
clk_coreclk_n
idl_c
fg
NO
C T
EST
WR
APP
ERpw
c_hl
PAUSABLE CLOCKGENERATOR
DELAY LINE PROG
SAS
IN
TER
FAC
E
delay_ctrl
clk_gene
xxx_sas
ISO
LATI
ON
C
ELLS
clock pause req/acksignals
reset_n
V-CORE POWER DOMAIN
PausableClock
Interface
ULTRA-CUT-OFF
VDD SELECTION
xxx_core
Pausable Clock Interface (1)
Programmable Delay Line
MEr1
r2
a1
a2
ai_asri_as
MEr1
r2
a1
a2
ai_sari_sa
MEr1
r2
a1
a2
ai_dlpri_dlp
reset_n
Clk
rclkdclk_b
rclk_dclk
dclk_bclk_prebuf
delay_cell[7:0], test_mode, reset_n
dclk
ClockTree
Pausable Clock generator
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
16
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
NoC Unit design (3)
Programmable delay line :Precise, small and low powerUsing Standard cellsOn the same unit power domain
xxx_test
V-HIGH V-LOWcut_off
test_scan
xxx_top
SynchronousNOC
protocol
POWERSUPPLY
UNIT
pwc_
cfg
xxx_unit
SYNCHRONOUSIP CORENETWORK
INTERFACE
LOWPOWER
MANAGER
GATED CLOCKidle
clk_coreclk_n
idl_c
fg
NO
C T
EST
WR
APP
ERpw
c_hl
PAUSABLE CLOCKGENERATOR
DELAY LINE PROG
SAS
IN
TER
FAC
E
delay_ctrl
clk_gene
xxx_sas
ISO
LATI
ON
C
ELLS
clock pause req/acksignals
reset_n
V-CORE POWER DOMAIN
PausableClock
Interface
ULTRA-CUT-OFF
VDD SELECTION
xxx_core
Pausable Clock Interface (2)
Programmable Delay Line
∆(i) ∆(i+1)
rst_nd[i]
rst_n
Ctrl[i]
Ctrl[i]
rst_nd[i+1]
rst_n
Ctrl[i+1]
Ctrl[i+1]
rst_n
rst_n
Test_mode
D(test)
Test_mode
Delaycell_in Delaycell_out
Pausable Clock Interface allows an efficient synchronization and a safe dynamic voltage and frequency
scaling with minimal latency cost
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
17
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
18
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
DVFS strategy programmed through NoC, Network Interface and global CPU
DVFS execution at system level
DVFS Execution
Global power management strategy is aiming atreducing the global energy while respecting global latency
constraints
HOPPING
INIT CFG HIGH LOW IDLE
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
19
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Outline
Dynamic and Static power consumption issuesNoC architecture for DVFS supportNoC Unit architectureNoC Unit designDVFS execution at system levelPower gain & physical implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
20
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Power gain & physical implementation (1)
Programmable delay line matches with unit logic on the same power domain :
Compensates any mismatch thanks to re-programmation
Power reduction :Vhigh=1.2V and Vlow=0.8V35 % dynamic power reduction between High and Low modesHopping mode is used to save power without any latency costLeakage power thanks to UCO is reduced by 2 decade
Power Supply Unit efficiency :Hopping Unit :
Only resistive losses in the power transistorsAbout 1 mW dynamic power
– => more than 95 % power efficiency90 % total efficiency (external DC-DC taken into account)
Power gain
An adaptive and reliable Power Supply Unit giving highpower reduction factor and high power efficiency
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
21
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Power Switch :One single Power-Switch for the complete power domainSized to get a speed loss < 5%Area : about < 5% of the power domain
Hopping UnitArea : 140µm*35µmHopping Transition : < 100 ns
Ultra-Cut-Off
Comparator D2A VDD-Hoppinglogic
Power-Switch
550µm
35µm
140µm
Power gain & physical implementation (1)Physical Implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
22
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
Conclusion
A fully integrated DVFS architecture within a GALS NoC
We are able to handle leakage problems due to technologyscaling
insertion of power switches
Dynamic power reduction is possible through voltage scaling:HoppingManagement of multi power domains in a complex SoC
Our knowledge of GALS systems lead us to automaticfrequency scaling
Pausable clock interfacesAsynchronous implementation
© CEA 2008. Tous droits réservés. Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEAAll rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
23
2007
E. BEIGNE- NOCS2008‘DVFS Architecture for Units Integration within a GALS NoC’
ALPIN :an “Asynchronous Low Power Innovative NoC”