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https://ntrs.nasa.gov/search.jsp?R=19650012049 2020-03-14T11:12:00+00:00Z

PORTABLE PFM ffiMULATOR

Designers:

Harold Levy Paul Heffner

Joseph Tinsley

Data Instrumentation Branch Data Systems Division

September 1964

GODDARD SPACE Fl.JGHT CENTER

Greenbelt, Maryland

CONTENTS

Page

INTRODUCTION . • . . . . . • . . . . . . . . . . . • . . . . . . . . . . . . . . • . . 1

SPECIFICATIONS . . • • . . • . . . . • . . • . . . . • . . . . • • . . . . . . • . • . 3

OPERATING INSTRUCTIONS ••.•.••. . • . • • • . . . . . . . . • . . . . . 4

DESCRIPTION AND THEORY OF OPERATION. . . . • • . . . . . . • • • . 4

CIRClJITS ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

BISTABLE MULTIVIBRATOR (FLIP-FLOP) CIRCUIT . . . . . . . . . . . 7

RUNDOWN CIRCUIT .• . . . . • • . • • . . . • . • • . . . . . • . • . . . . . . • . 14

NAND CIRCllT ..................................... 15

SCHMITT TRIGGER AND AMPLIFIER ..................... 18

OSCILLA TOR CIRCUIT . . • . • . . . . . • . . . . . • • . . . . . • • . • . • . • . 21

AUTOMATIC VOLTAGE-CONTROLLED (AVC) CIRCUIT ...•...•. 22

OSCILLA TOR GATE •. . . • . • • • • . . • • . . . • • . . . • . • . • • • . . • • . 25

POWER SUPPLY .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PERFORMANCE CHECK . • . • • . • . . . . • • . • • • • . . . • • . • . . . • • . 25

iii

ILL USTRA TIONS

Figure Page

Frontispiece- Portable PFM Simulator . . . . . . . . . . . . . . . . . . . . . .. vi

1 Typical Module Board ........................... 2

2 Simulator Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 PFM Simulator Logic, Block Diagram ................ 6

4 PFM Simulator, Phase Synchronization Logic Waveforms. . . . 8

5 PFM Simulator, Schematic Diagram . . . . . . . . . . . . . . . . . . 9

6 PFM Simulator, Wiring Diagram . . . . . . . . . . . . . . . . . . .. 11

7 Flip-flop Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13

8 Rundown and Flip-flop, Operating as Multivibrator . . . . . . .. 15

9 Rundown Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16

10 NAND Circuits . . . • . . . . . . . . . . . . . . . . . • . . . . . • . . .. 17

11 Schmitt Trigger and Amplifier ......•...•.•••.•.••• 19

12 OSCillator, AVC, and Oscillator Gate Circuits ........... 20

13 AVe wop ................................... 23

14 Complete L Pad ............................... 23

15 AC- Equivalent L Pad . • . . . . . . . . . . . . . . . . . . . . • . . • .. 23

16 Equivalent L Pad Seen by Input Signal. . . . . . . . . . . . . . . .. 24

17 Diode Characteristic Curve ...•.............•..... 24

18 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 26

19 Brown Test Point, Card 3 . . . . • • • • . • . • . • . • • • • • . • • •• 27

iv

Figure

20

21

22

23

24

25

26

Red Test Point, Card 3 ..................... .

Red and Brown Test Points, Card 3 ............ .

Yellow Test Point, Card 3

Orange Test Point, Card 3

. . . . . . . . . . . . . . . . . . . . .

Orange and Yellow Test Points, Card 3 ...•.......•...

Brown Test Point, Card 2

Brown Test Point, Card 1 ....

Page

28

28

29

29

30

30

31

27 Sinewave Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . 31

28 Square Wave Adjustment. . . . . . . . . . . . . . . . . . . . . . . . .. 32

29 Typical Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 33

30 Oscilloscope Pattern Showing Correct Adjustment ........ 34

31 SYNC BURST Variation • . . . . . . . . . . . . . . . . . . . . . . . .. 34

v

Frontispiece

• ,. , ~~

.~~~~~ t! ~

- Portable PFM S' Imulator

vi

PORTABLE PFM SIMULATOR

INTRODUCTION

The pulse-frequency modulation (PFM) simulator was designed in 1960 as a laboratory instrument to assist in the design and checkout of PFM equip­ment. Criteria for flexibility, data burst rates, data frequency ranges, etc., were based on previous PFM satellite ranges and expected future ranges.

The unit simulates the synchronous 16-channel frame pulse-frequency­modulated signal with frame-synchronization burst. Burst width, burst fre­quency, and burst amplitude are available by front panel control. The frame­synchronization burst can be positioned where desired at the beginning of the frame. The unit covers the data burst-rate range of 20 to 250 data bursts per second, and is continuously variable over these limits in just two ranges. The frequency within the data burst may be internally or externally applied; noise may be linearly summed with the signal by applying a noise generator signal to the unit.

The unit, which is fully tranSistorized, employs functional printed-circuit modules (Figure 1), including the power-supply regulator. All circuits were designed by the Data Instrumentation Development Branch. All outputs from the unit are protected against short circuits to ground.

1

Figure 1 - Typical Module Boord

SPECIFICATIONS

Signal:

Channels:

Number:

Burst frequency:

Burst duration:

Burst amplitude:

Burst de level:

Synchronization Burst:

Repetition Rate (simulated sampling rate):

Inputs and Input Impedances:

Noise input:

Ext. osc. input:

Outputs and Output Impedances:

Frequency burst output:

Burst envelope output:

Compo envelope output:

Burst #15 sync output:

Power:

Environment Temperature:

Structure:

Height

Width

Depth:

Controls:

Synchronous, pulse-frequency modulated, 16-channel frame with a synchronization burst

Sixteen

Internal or external (internal frequency continuously variable in two ranges cover­ing 4.5 to 45 kc)

Continuously variable, 0.5 to 50 msec in two ranges

Continuously variable, 0 to 4 vpp

± 0.5v continuously variable about Ovdc level of signal

Control to position the sync burst between channel 15 and channel 2

20 cycles/sec to 2 kilocycles/sec continu­ously variable, 2 ranges

6.1 kilohms

18 kilohms

100 ohms

1 kilohms

100 ohms

1 kilohm

105-120 volts rms 60 watts

Portable case

8-1/2 inches

5-3/4 inches

17 inches

Front panel

3

OPERATING INSTRUCTIONS

The PFM simulator unit operates on a standard 117-volt line. The BURST DC LEVEL control adjusts the dc level of the frequency burst with respect to the level of the blank for each burst and blank throughout the frame. In es­sence, this is a bias control to the oscillator AND gate. With large changes in temperature this control must be adjusted. The frequency within the burst must be measured by external means using, for example, an oscilloscope or a fre­quency counter. An appropriate sequence for operating the unit is:

1. Turn power switch to ON.

2. Throw INT. OSC.-EXT. OSC. switch to mode desired.

3. Synchronize oscilloscope to burst #15 sync output.

4. Turn BURST WIDTH and SYNC BURST WIDTH controls to minimum burst width.

5. Adjust BURST DC LEVEL.

6. Adjust BURST-BLANK controls.

7. Adjust BURST WIDTH controls.

8. Adjust SYNC. BURST WIDTH and SYNC. BURST POSITION controls.

9. Monitoring FREQ output, adjust frequency controls.

10. Throw SINEWAVE-SQ. WAVE switch to signal desired.

11. Adjust BURST AMPLITUDE.

DESCRIPTION AND THEORY OF OPERATION

The principal output of this unit is the 16-burst/blank frame including the synchronizing burst. All bursts consist of a sinewave (or square wave), controllable in two ranges of 5 to 15 kc and 15 to 45 kc. The burst amplitude can be varied from 0 to 4 volts peak-to-peak. The synchronizing burst width and occurrence in time relative to the preceding burst are individually controllable. The burst­blank period and the burst within the burst-blank period are adjustable over two ranges of 0.5 to 4 msec and 4 to 50 msec. The waveform within the burst may be switched to either a sinewave or a square wave. In either case, the waveform swings about the dc level of the blank period (Figure 2). The frequency of the square wave is that of the sinewave oscillator setting. The frequency within the burst may be provided by an external oscillator in order to obtain frequencies not attainable in the given ranges of the internal oscillator. The input for the external oscillator is at the rear of the unit.

4

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UNIJUNCTION : /'1 VL:

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FF7 OUT·] ~~n~---------------------------------~~~ ENVEL.

OUT , , , , "

I : ~ I

BURST OUT M •• ' •• " ......

CHANNEL -----; I #15 OUT L...J

(Sync,)

Figure 2 - Simulator Waveforms

,

The burst-blank period is set by a free-running unijunction rundown circuit which will be referred to as the clock. The clock output is shaped and used to drive both a binary counter and a monostable multivibrator which is a combina­tion of a flip-flop and a unijunction rundown circuit. Referring to Figures 2 and 3, the clock pulse after shaping is seen to trigger flip-flop #6 ON, initiating the rundown which puts out a delayed pulse to trigger the flip-flop OFF. This ON state will gate in the oscillator for the burst (the OFF state will be a blank). The clock also drives flip-flop #1, which is the front end of a binary scale-of-16 counter. After each lapse of 16 burst-blank periods, flip-flop #4 will trigger a

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Figure 3'- PFM Simulator Logic, Block Diagram

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E"'VEL-. OUT

NOISE IN

&U"S1' OUi

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FRE.Q.­OUT

CH.A~N£L- *IS OUT

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monostable consisting of flip-flop #8 and its rundown circuit. The delayed run­down pulse triggers flip-flop #8 OFF. The ON state of flip-flop #8 will be the delay setting of the sync burst, referred to as sync burst position. As flip-flop #8 resets after its delay, it will trigger another monostable conSisting of flip­flop #7 and its rundown circuit. The ON time of this flip-flop will be the sync burst width.

The burst gates for the sync burst and the following bursts are NOR­functioned so that the combined signal can be passed to the oscillator gate. The signal at this point is also passed through the envelope buffer to the ENV. OUT encoder.

So that the gate time of the burst will not begin at a random phase angle with respect to the incoming continuous sinewave (or square wave) appearing at the oscillator gate, logic is incorporated that will delay the gate until the sinewave (or square wave) passes through the dc level of the signal (Figure 4). This is done by triggering a Schmitt trigger at a dc level commensurate with the dc level of the incoming sinewave. The output of this Schmitt, after shap­ing, is AND-functioned with the output of the NOR to reset flip-flop #5. The set output (out-O) of this flip-flop at the -9 volt level will gate the OSC.-AND; but this output will not drop to the -9 volt level until the reset input (T-1) receives a positive-going pulse. Inspection of the wave forms in Figure 4 shows that this positive-going reset can occur only at the turn-on time of the Schmitt which was preset to trigger at the level mentioned above. In the square wave mode, a burst will always begin with a full square wave; Similarly, in the sinewave mode, a burst will always begin with a full sinewave (the output is shifted by 180 degrees).

The gated sinewave (or square wave) is amplified and ac-coupled to the BURST OUT encoder. A noise signal is applied and algebraically added to the PFM signal at the base of the output emitter-follower. The PFM-signal­amplitude control precedes this stage so that the signal may be reduced within the noise signal. Figures 5 and 6 are the complete schematic and wiring diagrams.

CIRCUITS

BISTABLE MULTIVIBRATOR (FLIP-FLOP) CIRCUIT

The flip-flop circuit (Figure 7) is a JK Eccles-Jordan binary circuit. The reset (j) and set (k) inputs are ac-coupled. By common connection of both the reset and set inputs, the circuit becomes a binary counter. A positive step

7

CLOCK OUT

FF6 OUT·]

NOR OUT

CW SINEWAVE

SCHMITT OUT

AND OUT

FFs OUT·O

Gate Input To Osc. Gate

OSC. AND OUT (Sq. Wave)

OSc. AND OUT (Sinewave)

SIMULATOR ) PHASE SYNC. LOGIC WAVEFORMS

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Figure 4 - PFM Simulator, Phase Synchronization Logic Waveforms

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Figure 5 - PFM Simulator, Schematic Diagram

9

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Figure 6 - PFM Simulator, Wiring Diagram

11

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FigLl'e 7 - Flip-flop Circuit

PIN CONNECTlON~

MONT MCK (,HD I A 6AID fa z a ioe -'!) • C -5 T1-~ ... D 11-4 11-2 5 • QUf.'-4 11-' ~ F" our_A CIUJ4It&.& 7 H aur"'I-. 0Uf4tt-. • .. MST-+ ~-.

, It ... .. ftESEf-2 III L ... " ~-. 11 M RDET3 SE1'-3 12 N ..... srr-a " p ..... ~o-, ... R SIE1' • OUTO-Z 15 5 OUTO-.s 16 T"

TP-f n u OUT AtIO. TO-2 Ie V QUT-o-+ TO-.J .. w 10-4--~ ., )C -~ ~8 II Y io. fONO • • GHII

voltage on the {nputs constitute true inputs. The logical function performed by this circuit is shown below:

k

... ,.

... ,.

A(T) = kA + jA

A(T) = kA + lA

A

0 "-,. A

1 ~ ,.

A set input and a reset input are included in the circuit. To employ these inputs a differentiated step voltage is applied.

Four flip-flop circuits and two passive AND gates are on each flip-flop board. The AND gates may be used to implement the four flip-flops as a decimal counter.

RUNDOWN CIRCUIT

The rundown circuit is a circuit which, when used with a flip-flop as shown below, constitutes a wide-range, continuously variable, high-duty cycle mono­stable multivibrator.

--t

kr-t FLIP FLOP

AU. f--

r RUN-

DOW~J,

1'- A(T) .J

Figure 8 shows the timing relationship of the rundown and flip-flop.

14

Flip-Flop Input

I I

Flip-Flop Output 11-------4 RC Charge

Within Rundown

Output of Rundown

I I I

I ~

Figure 8 - Rundown and Flip-flop, Operating as Multivibrator

When the input to the rundown circuit steps negatively from ground to -9v, Q 1 saturates and C begins to charge toward ground through the 2.4k resistor and the external front panel potentiometer. When the potential on C reaches the threshold* of the unijunction, it will break into conduction and discharge C to nearly -9v where the unijunction then presents an open circuit to C. The result of the fast discharge of C through the unijunction Q3 is a negative pulse at B2 of Q3' which is coupled to Q4' This input to Q 4 provides at its output a positive pulse which, as shown in Figure 10, is coupled back to the flip-flop, returning the flip-flop to its original state. This returns the input to the rundown to ground, and turns on Q2' a clamping transistor, which clamps C to -9v until a new input arrives at Q l' The delay time (T) of the circuit is a function of the setting of the front panel potentiometer and the choice of C. There are five rundown circuits on each board. (See Figure 9).

NAND CIRCUIT

The NAN!) circuit (Figure 10) is a DCTL circuit which (to function as a NAND) requires that all inputs be negative, and (to function as a NOR) requires

*The thres~old voltage of a unijunction is defined as Y)VB B where Y) is the intrinsic stand-off ratio (I) = 0.6) and VB B is the voltage impressed across\h

2e unijunction.

1 2

15

[-- .

,.... O'l

QI i!N1301

-9V

S.IK

INPtIT~ 101C.

NOTES:

1J2K =

+tlV

E¥TERNAL PANEL ---

I! .... K

TEST POINT

INllT

QZ 2.N490

.D47p7

.0»1'

"-70:.11

251:)IC.~ •

ItSIC.

~SE£ Mf1;r~- 1 NOTE 2 1eANf;£ I

i 1. FIVE CJJi!CIJITS PEJi! alARD. Z. D£T£J2MINES . .RANI;£

1rIIJLT1-RAN(#E

.S-'fMS "'-50 MS

POT. I CAR

5OK. I O.lpf' 50K 2.0p.'"

Figure 9 - Rundown Circuit

/OOIC.

S_IK

OUT

Q.3 2N496

PIN CONNECTIONS

Fli?0NT BACK.

GND I A GNO +8V 2 B +8V -9V 3 C -9V IN-I '" D OUT-I 8-1 (POT) .5 £ A-I (POT) l. F IN-2. 7 H our-Ii! S-2(POT) 8 ,J A-Z(POT) 9 K. IN-.3 10 L OUT-3 /J-.3(POT) /I All A • .3 (POT) IZ N

13 P IN-4 14- Ii! OUT-" S-4(POT) 15 s A'4(POT) II. T IN-S 17 U OUT-S B-.5(POT) 18 V A-5(POT) 19 w -9V 20 K -9V +lJV 21 Y +BV GND 22 Z C;NO

I-' -::J

"""'iiiI:

r-----------------~----------------------------------------------------~~

NAND -sv

4.3K

11'1127 11'10 ~ , '\

1"1127 IJo.IO ~ •

NOOEO-----..l

CLUSTER 11'112'7

CL. IN ou-----:-""*~ ...... ---eL.IN: IN~' J OCLOUT

NOTES:

'" CIRCUIT BOARD HAS A YELLOW LIFTER,

OUT

+8V

PIN CONNECTIONS

fRONT ~ Gt-ID I '" Gt-ID +8 2 e +8 -~ " C -~ INI ... D OUT \ INI 5 E oUTe I~Z " f OUT3 INZ 7 H OUT 4-IN3 8 J CI-"r'-OUT 11'13 9 \C. CI.41e-OOT 11'14 10 L CI,. .. '-IN 1"-11- II 1/1 CL"I-\Jo.\ IN5 It N CI,. .. Z-II-I IN 5 IS P a.-Z-IN INGo 14 ROUTS INc:. 15 5 OUT Go IN7 ~ TOUT 7 IN7 11 U NODE7 1"1' 18 V OUT 8 IN8 19 W /oIODES -s 20 )( -9 -tl 21 "( +8 GND 2t iI SIIID

Figure 10 - NAND Circuits

;: = ~ :::: ~ :~~:: ~

::::: ~ :J:";; ~ :::: ~ ~: :: IQ

I J 0

N: :: ICL

_ K 0

that anyone of the inputs be at ground. Logical functions implemented by this circuit are shown below:

(1) As a NAND (for negative logic):

Here the circuit implements the Sheffer stroke function.

(2) As a NOR (for positive logic):

Here, the circuit implements the Peirce function.

Better than 1-volt noise immunity is provided when the input is at ground level. Eight NAND circuits are on each card: Six of the circuits are restricted to a maximum of two inputs, and two circuits are expandable for greater fan-in ability by having a node to which extra input diodes may be connected. Two diode clusters are available with which fan-in may be extended.

SCHMITT TRIGGER AND AMPLIFIER

Figure 11 is a diagram of two separate circuits, a Schmitt trigger and an amplifier.

The Schmitt trigger is a conventional type with a trimpot to adjust the threshold. An input emitter-follower Q1 serves to increase the input impedance and isolate the effect of the threshold adjustment. The common emitter­resistor prevents the Schmitt's Q2 and Q3 output from going to ground. The shaper Q4 is a saturating stage ensuring a complete swing from ground to -9v

18

~ ~

~HMliT IN (AVe. OUT)

9

AMPL.lfIER IN 14

-~

-= 'BV

5CH~liT TRIGGER 5l0J'-'

-:3Y

+----+--.. 1:2~~301

TEST POINT (aROW~)

tiN

IK

~q,

-'!N

i'TEST ,.,.. (RED) TO Ff

~ , t H "AI-IP'

• tL 'g,q~~C. 51<. (aV 5WIlt:H) TRI"" pOT

~ -= SGHMITT SHAPER

TJ::sr POINT (YELLOW)

,~v

eURST OUT

Figure 11 - Schmitt Trigger and Amplifier

PIN CONNECTIONS FROOJI ~ G~D '1 A G"ID ~8 2 B t8 -~ 3 C -9

4 D 5 E ~ F 7 ® r.fc\'~~T;J;SH 8 J

5CHIAITTIN @ K 10 ~ ~.f~~~1: 6~~l) II 12 N 13 P

AMPI..IF'.""N ® R

.\lOISEI" I <S> II( POT (Qr EMITTER> C.T. IK POT T

U @ BVR~TOU~

'" w OIH &'.ovT

-9 20 r -~

+8 2.1 V +8 GoND z.. f G/o.IO

l\j

o

I asci LL~ TO R

I I

I

-'V

TEST PT. 11110"''')

@

r-----~ENOTE"

I I I

t!~.!':... _ __ J

l~~

/US!

20/1

o.l"r 15K

.02lrl

I ~tl( I

L-~================~_=-= __ +_'V __ ~I __ +-__________ ,-____ __

loloTU:

~)(nRIIAL OSC.11ol

I - IUC"TEI'HA&.. OUTL£TS ARe IIOI(U) WITH DOTTED L.INES.

z.- PIN CONNECTIONS ARE. CIRC.LI!D.

3- WHEN TAIllf.POT IS IIOUIITED 01l80AIID AK AWUTUDE CONTROLLED OIlTPUT " PIN If. WilEN EXTEIINAL POT IS EMPLOYED Ave AMPLITUDe CONTROLL£D OUTPUT

IS ,eNTeR TAP 0' ElCl"EltIlAL /O/( POT. 4- A lie POT WAY If ADDID IN 'fRllS WITH

THE ZSJ( I'OT TO PROVID. ',NI FrufulNCY ADJUST,.,UT.

s- IIJti: 10' 11",'0 it - I2ESI5TOR ADDED IN PARALLI:L TO

ATTENUATE OIITPUT SIGNAL SUCH THAT AU. OSCILLATOR <;.4T£S HAVE ~. SOIM£ AMPLITUDIt OUT.

OSC GATE

SEE NOTED

Mft Il_, INI'UT~ +-Sf(

Ave

II< -!N

.o~,< " 1+ lOv

--l

--n-"'" ~ ~ I II. <\' ..,'" !m.1If' I

151< -=

Figure 12 - Oscillator, AVC, and Oscillator Gate Circuits

(S~E NOTES I <tz.) PIN C.OONECTIONS

FRONT ~ GltD I A~D +8 2 !I +8 -9 S c-~

4 D 5 E .. ~ 7 II • J , /(

10 L-II M £In"EJtM.(D$c,INIj

ar MarE3 12 ... 15 P I't It IS 5

" T 17 U ~ 1l1l'\.I" La 'i

eN '" I' W -. 2iI) )( -, •• ZI Y1'1 GND12 1!~

of the output. The reduced output is used to drive the oscillator gate (Figure 12) whenever square waves are desired.

The input to the amplifier is an emitter-follower Q5 for high-input im­pedance, which drives an ac amplifier Q6 whose output is approximately 4.4vpp. The output amplitude is adjusted by an external front-panel potentiometer in the emitter of Q7; the output may be resistive mixed with noise and the com­bination of signal and noise is used to drive the emitter-follower at Q8. The series 51-ohm resistor protects the circuit against shorting of the output.

OSCILLA TOR CIRCUIT

The first circuit is a continuously variable sinusoidal oscillator of the Colpitts type which, through external switch control, has the two frequency ranges of 4.5 to 15 kc and 15 to 45 kc. Each range is obtained by switching a separate LC network into the oscillator. The approximate center frequency of the oscillator for each tank is given by:

1 f = 21T ~ where CT

=

By adding a variable resistance (R) between the emitter and ac ground, the equivalent ac tank circuit appears as shown below:

R

By varying R, the equivalent reactance provided by C 2 is altered and the center frequency of the network is changed. In the Mode II simulator, R is

21

the sum of a 25-kilohm potentiometer and a fixed resistor of 2 kilohms. The oscillator frequency variation with R is shown below:

R

27K -

~~~~==~-------f

Because the frequency varies nearly hyperbolically with R, a type-B logarithmic potentiometer having a curve as shown below is employed to provide an approximately linear variation of frequency with the turning of the frequency control.

R

~---+--~~~--------TURN

<J>/o 50% 100%

AUTOMATIC VOLTAGE-CONTROLLED (AVC) CIRCUIT

The function of the second circuit is to automatically voltage-control either the internally generated frequency signal or an externally applied frequency signal so that the input to the oscillator gate will always be a constant-level signal.

22

The principle employed is in essence that of controlling the gain of a Class A amplifier through interrogation of the output signal level as shown in Figure 13.

ATTENUATION CONTROL

Figure 13 - AVC Loop

This is done by equivalently varying the shunt resistance of an L pad pre­ceding the input to the Class A amplifier with a dc current that is a function of the output signal level of the amplifier. The L pad consists of a series re-sistor and an equivalent ac shunt resistance of two diodes which are dc biased in a region where, for changes in the dc current through the diode, the small signal diode resistance can be varied. Figures 14, 15, and 16 show the complete L pad, the ac equivalent, and the equivalent configuration seen by the input signal.

de bias r---1It--~

source

~ ac by-pass

Figure 14 - Complete L Pad

23

Figure 15 - AC· Equivalent L Pad

Figure 16 - Equivalent L Pad Seen by Input Signal

The variation of the small signal resistance with the dc bias current can be seen by reviewing the characteristic curve of the diode as shown in Figure 17, where V is chosen to be the ordinate and I the abscissa.

v de load line

/ _----Small signal operating point

. dv r =-

di

Figure 17 - Diode Characteristic Curve

The resistance exhibited by the diode is the tangent to the curve at the intersection of the dc bias current and the characteristic curve. For very small time-varying signals, the ac resistance is appreciably linear for a fixed dc operating point. By changing the quiescent operating point, the ac resistance is changed as shown.

The small variation from linearity is improved by using two diodes in parallel, one in an ac forward biased direction and one in a negatively biased direction; the ac resistance is then the parallel resistance of the two small signal resistances given by the two operating points of both diodes.

24

The dc bias current to the L pad is supplied by detecting and low pass­filtering the output of the Class A amplifier (Q2) amplifying this voltage, and then providing a current as a function of this voltage.

OSCILLA TOR GATE

The oscillator gate (Figure 12) digitally controls passage or infinite attenu­ation of a time-varying signal so that the signal dc level during the time of infinite attention is the dc center of the peak-to-peak levels of the signal during passage. This is done by biasing a Class A amplifier (Q6) so that the output quiescent operating level is ground. Application of a symmetrical input signal will then vary about ground at the output of the amplifier. A saturating transistor (Q7) is digitally controlled (at pin U) to turn this transistor full-on or full-off which infinitely attentuates the output of the Q6 or fully passes the output of Q6' respectively. The 2N508 was chosen for Q7 because it has an extremely low saturating voltage.

The dc level of the output of Q6 is externally controlled by varying a 50-k potentiometer in the bias network as shown in Figure 12.

POWER SUPPLY

The power supply (Figure 18) consists of two voltage regulators, one for +8vdc and one for -9vdc. The +8vdc power supply will deliver 300 ma and the -9vdc supply will deliver 400 mao Both regulators are of the series type in which regulation is made through control of a series power transistor by referencing the output of each supply through a divider network to a constant voltage source provided by a zener diode. Correction is made by varying the gain of the series power transistor through an amplifying stage with the infinite tesimal voltage differences seen between the zener diode and the divider net­work. Both regulators share the same transformer input through a full wave rectifier; each supply is filtered separately.

Each supply is protected against short circuits or excessive loads through current limiting. The supply voltages may be finely varied by adjusting the trimpots incorporated in the divider network of each regulator.

PERFORMANCE CHECK

This section describes the procedure for checking the simulator and setting all internal controls for proper operation.

25

~ 0')

r--------, THORo""50N • ZIFZ7

I I I~"" ---117V

I RillS

400 Mil

DIODES

1.lLIW

---, r- I

1.f:I 15 V DC I I -=- .l'OOO)JF--l L ±T __ _

2N12'4 oR 211J26 1.5.Q. IW I'" s voc '2:]11 : ( • ''1

I N-'2 I ---'

LJ\IV\. •• , ~B.=.2 L __

0-4

r - - -,- - , I +

13101°"'~-I Z5VDC

I I

I I -=-I + 31000",_ I 25VOC L ___ 1 __ --l

I'·W

'.fl.IW

NOTES: /- EXTERNAL COMPONENTS ARE ENCLOSED

WITH OOTTEO LINES z- LIMITIN~ CURRENT WHE.N OUTpUT IS SHORTEO TO "NO:

-9SUPPI.Y - 500!+OM()' (REGUlATIONT0400~50Mo.J ... 8 SUPPLY - 300~50MQ (RE&ULATIONT0250:!"50MIl)

3· CIRCUIT BOARD HAS A BLACK LlFlER.

11'1&8'

V-2'

• )TP (GREEt-I)

SDDA. J -<TRllliPOT

+

+

IOO,JJF 20Y Pc.

IOO)lF ZOV DC.

1000.11.

500 A

1 SOOA 11'1689 ~ TRIM POT

IAIW

~---<(!)TP (RED)

- 9 If DC

2N38~~~:0 ---, r - ~OOO)JF I

Figure 18 - Power Supply

I +I'5VOC; 1:::- I L ____ -'

PIN CONNE.CT/OHS FRONT SAC"

6No A 6NO

oIH~"" 2- 8 +8~HIO 'OOO)jF·/6VDC -, 3 C -,

olH t!- c .. D C -±t HI' II 5 E 8

E. II F E

1 H

• J

KE.Y ,

" KEY

10 L

CTzt.SV5.: 1/ iii ~ Z6.5V C1 IIMS ~ 12 II "illS

13 P

14 " KE.Y 15 s I<.E.'(

/6 T

E 11 U E.

8 /8 V It

"f-!l ~ c 19 W C ~t-!.ilo

"f-±t ~ -9 20 X -, ~~" IOOO)JF 15 roc +8

21 .y ... ., 6ND 22 Z GHD

All wave shapes and voltage levels should be made with front-panel switches in following positions (unless otherwise specified):

• All NAR/WIDE switches - wide position

• FREQ RANGE - high position

• SINEWAVE/SQ WAVE - SINEWAVE position

• INT OSC/EXT OSC switch - internal position

• BURST AMPLITUDE - maximum clockwise

• BURST DC LEVEL - maximum clockwise

All other controls will be used to obtain correct wave shapes. The printed circuit boards are numbered 1 to 6 from front to back.

Test equipment to be used includes: Tektronix 535 -A oscilloscope with dual trace amplifier, Simpson meter, and Hewlett-Packard oscillator.

1. Applyac with power ON switch. Measure the dc voltages, -9 and +8, at test points on power-supply card (card 6). Green test point is +8; left trimpot adjusts this voltage. Red test point is -9; right trimpot adjusts this voltage.

2. Observing sawtooth wave at brown test point on card 3 (rundown), adjust this sawtooth with front­panel 50K pot, BURST­BLANK PERIOD, for a 20-millisecond sawtooth (Figure 19). Scope settings: Sweep time, 5 milliseconds/ cm; vertical deflection, 2 volts/ cm; sync, internal negative.

Figure 19 - Brown Test Point, Card 3

27

3. Observing sawtooth wave at red test point on card 3 (rundown), adjust this sawtooth with front­panel control BURST WIDTH for a 10-millisecond blank (Figure 20). Scope settings: Sweep time, 5 milliseconds/em; vertical deflection, 2 volts/em; sync, internal negative.

4. Observing sawtooth waves at red and brown test points on card 3 (run­down), the time relation­ship should be: During the time of the 20-millisecond sawtooth there should ap­pear a 10-millisecond sawtooth and a 10-milli­second blank (Figure 21). Scope settings: Sweep time, 5 milliseconds/cm; vertical deflection, 2 volts/ cm; sync, internal negative

Fi gure 20 - Red Test Po int, Card 3

Figure 21 - Red and Brown Test Points, Card 3

28

5. Observing sawtooth wave at yellow test point, card 3 (rundown), adjust this sawtooth for a mini­mum of 5 milliseconds with SYNC' BURST POSITION control on front panel. This wave shape is ob­tained by using external sync from burst 15 con­nector. Scope settings remain the same as for last check.

6. Observing wave shape at orange test point, card 3 (rundown), adjust saw­tooth wave for 10 milli­seconds with front-panel control SYNC BURST WIDTH. Obtain external sync from burst 15 con­nector on front panel.

Figure 22 - Yellow Test Point, Card 3

Figure 23 - Orange Test Point, Card 3

29

7. Observe wave shapes at orange and yellow test points on card 3 (run­down) and check to de­termine if the negative­going edge of the SYNC BURST POSITION saw­tooth (which is 5 milli­seconds in duration) occurs at the beginning of the 10-millisecond sawtooth (Fig­ure 24). Scope settings: Sweep time, 5 milliseconds/ cm; vertical deflection, 2 volts/ cm; sync, external from burst 15 connector.

8. Obtain a symmetrical waveform at brown test point, card 2 (oscillator gate). Set OSC FINE con­trol to midrange by adjust­ing OSC COARSE control on front panel, simultane­ously adjusting left trim­pot on card 2 until no noticeable change occurs in the bias set and the peak­ing of the oscillator. This condition gives equal swing above and below ground (Figure 25). Scope settings: Sweep time, 20 milliseconds/cm; vertical deflection, 2 volts/ cm; sync, internal positive.

Figure 24 - Orange and Yellow Test Points, Card 3

Figure 25 - Brown Test Point, Card 2

30

9. Observe square wave at brown test point, card 1 (Schmitt and amplifier). Obtain a symmetrical wave­form by adjusting left trim­pot on card 1 (Figure 26). Scope settings: Sweep time, 20 milliseconds/cm; vertical deflection, 2 volts/ cm; sync, internal negative.

10. Adjust sinewave at burst OUT connector on front panel for maximum amplitude with right trimpot on card 2 (oscillator gate) before saturation occurs at about 4 volts. (Note: This will not give best sinewave operation; see Figure 27.) Scope settings: Sweep time, 0.1 millisec/ cm; vertical deflection, 2 volts/ cm; sync, internal negative.

Figure 26 - Brown Test Point, Card 1

Figure 27 - Sinewave Adjustment

31

11. While monitoring BURST OUT, move SINE­WAVE/SQ. WAVE switch to SQ. WAVE position. Ad­just SQ WA VE for best sym­metrical wave above and below ground with trimpot on right of card 1 (Schmitt and amplifier); approxi­mate 6-1/2 volts peak-to­peak. When this is com­plete, throw switch back to SINEWAVE position. Scope settings: Sweep time, 0.1 milliseconds/em; vertical deflection, 2 volts/ cm.

rigure 28 - Square Wave Adjustment

12. At this point check wave shapes and voltage levels as shown in Figure 29.

13. Now observe BURST OUT as compared to SYNC BURST POSITION, yellow test pOint. Obtain scope sync from burst 15 connector on front panel. If all adjustments are correct, the result will look like Figure 30. Note that, by increasing the SYNC BURST POSITION by 15 milliseconds, sync burst has moved to burst 1 as seen in Figure 31.

32

•

BROWN TEST POINT

RED TEST POINT

ORANGE TEST POINT

YELLOW TEST POINT

FLIP-fLOP'1

\.0-40 ,.. sec-...j

ILJO

V

-8'1 ~80 ",sec-ll nJ: 14-160 ,..Me-tl nJ: jt-320 ,..Me-tj nJ:

CORRECT BURST OUTPUT

~ j..15/.J.hC N J+ ~~ etc .

..;. sa

OV

FLIP-FLOP '2

10 10 It.-",sec.j....;.tse:-oo!

ruO

V

10 -7V

r~'l-JOV

tlf ~ ov 315 ~-7\I

ruov -7\1

THIS ENVELOPE CARRIES A SINE OR SQUARE WAVE

NOTES:

A - COMBINATION Of BURST-BLANK AND SYNC BURST PULSES

B - AS SYNC BURST IS MOVED FROM THE 16TH TO THE 5TH CHANNEL, THE RISING EDGE OF SYNC POSITION WILL MOVE ACCORDI NGL Y

C - THE SYNC WIDTH PULSE WILL FOLLOW THE RISING EDGE OF SYNC POSITION.

I,..S PER SMALLEST DIVISION

< 3 TO 15 > CHAN

NAND FRONT

n~IOV GREEN TEST POINT

-9V

DO

V

19 ",sec ~ BLUE TEST POiNT

-9V

mov VIOLET TEST POINT

-9V ov GRAY TEST POINT

-9V

15

Figure 29 - Typical Waveforms

33

NAND FRONT

101 T'l OV

-9V

OV

-9V

OV

-9V

~OV 300 ,/liMe ~

-9V

NOTE C

TEST POINTS:

TP BROWN, BOARD 3 BURST -BlANK PERIOD

TP RED, BOARD 4 SHAPED BURST -BlANK PERIOD TRIGGER

TP RED, BOARD 3 BURST -BlANK WIDTH

TP ORANGE, BOARD 4

TP BROWN, BOARD 6 GATE PULSE IN

BURST OUT

TP YELLOW, BOARD 5 FLIP-flOP 5

TP YELLOW, BOARD 3 SYNC POSITION

TP ORANGE, BOARD 3 SYNC WIDTH

Figure30 - Oscilloscope Pattern Showing Correct Adjustment

•

Figure 31 - SYNC BURST Variation

:34