e200z759n3crm: e200z759n3 core reference manual · 1.1.2 microarchitecture summary ... 8.3.9...

e200z759n3 Core Reference Manual, Rev. 2

Freescale Semiconductor 1

e200z759n3 Core Reference ManualSupports:

e200z759n3

e200z759n3CRMRev. 2

January 2015



Chapter 1e200z759n3 Overview

1.1 Overview of the e200z759n3 ..........................................................................................................231.1.1 Features .............................................................................................................................231.1.2 Microarchitecture summary ..............................................................................................24

1.1.2.1 Instruction unit features ..................................................................................261.1.2.2 Integer unit features ........................................................................................271.1.2.3 Load/store unit features ..................................................................................271.1.2.4 Cache features .................................................................................................271.1.2.5 MMU Features ................................................................................................281.1.2.6 e200z759n3 system bus features .....................................................................28

Chapter 2Register Model

2.1 PowerPC Book E registers ..............................................................................................................332.2 Zen-specific special purpose registers .............................................................................................352.3 Zen-specific device control registers ...............................................................................................372.4 Special-purpose register descriptions ..............................................................................................37

2.4.1 Machine State Register (MSR) .........................................................................................372.4.2 Processor ID Register (PIR) .............................................................................................392.4.3 Processor Version Register (PVR) ....................................................................................402.4.4 System Version Register (SVR) ........................................................................................412.4.5 Integer Exception Register (XER) ....................................................................................412.4.6 Exception Syndrome Register ..........................................................................................42

2.4.6.1 PowerPC VLE mode instruction syndrome ....................................................442.4.6.2 Misaligned instruction fetch syndrome ...........................................................44

2.4.7 Machine Check Syndrome Register (MCSR) ...................................................................452.4.8 Timer Control Register (TCR) ..........................................................................................472.4.9 Timer Status Register (TSR) .............................................................................................482.4.10 Debug registers .................................................................................................................492.4.11 Hardware Implementation Dependent Register 0 (HID0) ................................................502.4.12 Hardware Implementation Dependent Register 1 (HID1) ................................................522.4.13 Branch Unit Control and Status Register (BUCSR) .........................................................532.4.14 L1 Cache Control and Status Registers (L1CSR0, L1CSR1) ...........................................542.4.15 L1 Cache Configuration registers (L1CFG0, L1CFG1) ...................................................542.4.16 L1 Cache Flush and Invalidate registers (L1FINV0, L1FINV1) ......................................552.4.17 MMU Control and Status Register (MMUCSR0) ............................................................552.4.18 MMU Configuration register (MMUCFG) .......................................................................552.4.19 TLB Configuration registers (TLB0CFG, TLB1CFG) .....................................................55

2.5 SPR register access ..........................................................................................................................552.5.1 Invalid SPR references ......................................................................................................552.5.2 Synchronization requirements for SPRs ...........................................................................562.5.3 Special purpose register summary ....................................................................................57

2.6 Reset settings ...................................................................................................................................60


4 Freescale Semiconductor

Chapter 3Instruction Model

3.1 Unsupported instructions and instruction forms .............................................................................653.2 Implementation-specific instructions ..............................................................................................653.3 Book E instruction extensions .........................................................................................................663.4 Memory access alignment support ..................................................................................................663.5 Memory synchronization and reservation instructions ...................................................................663.6 Branch prediction ............................................................................................................................683.7 Interruption of instructions by interrupt requests ............................................................................683.8 New Zen instructions and APUs .....................................................................................................683.9 ISEL APU .......................................................................................................................................693.10 Debug APU .....................................................................................................................................69

3.10.1 Debug notify halt instructions ...........................................................................................713.11 Machine Check APU .......................................................................................................................733.12 WAIT APU ......................................................................................................................................753.13 Enhanced reservations APU ............................................................................................................763.14 Volatile Context Save/Restore APU ................................................................................................793.15 Unimplemented SPRs and read-only SPRs .....................................................................................873.16 Invalid forms of instructions ...........................................................................................................87

3.16.1 Load and store with update instructions ...........................................................................873.16.2 Load multiple word (lmw, e_lmw) instruction .................................................................873.16.3 Branch conditional to count register instructions .............................................................873.16.4 Instructions with reserved fields non-zero ........................................................................88

3.17 Instruction summary ........................................................................................................................883.17.1 Instruction index sorted by mnemonic ..............................................................................893.17.2 Instruction index sorted by opcode .................................................................................102

Chapter 4Instruction Pipeline and Execution Timing

4.1 Overview of operation ...................................................................................................................1174.1.1 Control unit .....................................................................................................................1194.1.2 Instruction unit ................................................................................................................1194.1.3 Branch unit ......................................................................................................................1194.1.4 Instruction decode unit ....................................................................................................1194.1.5 Exception handling .........................................................................................................120

4.2 Execution units ..............................................................................................................................1204.2.1 Integer execution units ....................................................................................................1204.2.2 Load / store unit ..............................................................................................................1204.2.3 Embedded floating-point execution units .......................................................................120

4.3 Instruction pipeline ........................................................................................................................1204.3.1 Description of pipeline stages .........................................................................................1224.3.2 Instruction prefetch buffers and branch target buffer .....................................................1234.3.3 Single-cycle instruction pipeline operation ....................................................................1254.3.4 Basic load and store instruction pipeline operation ........................................................1254.3.5 Change-of-flow instruction pipeline operation ...............................................................126



4.3.6 Basic multi-cycle instruction pipeline operation ............................................................1284.3.7 Additional examples of instruction pipeline operation for load and store ......................1294.3.8 Move to/from SPR instruction pipeline operation ..........................................................131

4.4 Control hazards .............................................................................................................................1334.5 Instruction serialization .................................................................................................................133

4.5.1 Completion serialization .................................................................................................1334.5.2 Dispatch serialization ......................................................................................................1344.5.3 Refetch serialization .......................................................................................................134

4.6 Concurrent instruction execution ..................................................................................................1354.7 Instruction Timings .......................................................................................................................1364.8 Operand placement on performance .............................................................................................141

Chapter 5Embedded Floating-Point APU (EFPU2)

5.1 Nomenclature and conventions .....................................................................................................1435.2 EFPU programming model ...........................................................................................................143

5.2.1 Signal Processing Extension / Embedded Floating-point Status and Control Register (SPEFSCR) 1435.2.2 GPRs and PowerISA 2.06 instructions ...........................................................................1475.2.3 SPE/EFPU available bit in MSR ....................................................................................1475.2.4 Embedded floating-point exception bit in ESR ..............................................................1475.2.5 EFPU exceptions .............................................................................................................147

5.2.5.1 EFPU unavailable exception .........................................................................1485.2.5.2 Embedded floating-point data exception ......................................................1485.2.5.3 Embedded floating-point round exception ...................................................148

5.2.6 Exception Priorities .........................................................................................................1495.3 Embedded floating-point APU operations ....................................................................................149

5.3.1 Floating-point data formats .............................................................................................1495.3.1.1 Single-precision floating-point format ..........................................................1505.3.1.2 Half-precision floating-point format .............................................................151

5.3.2 IEEE 754 compliance .....................................................................................................1525.3.3 Floating-point exceptions ...............................................................................................1535.3.4 Embedded scalar single-precision floating-point instructions ........................................1535.3.5 EFPU Vector Single-precision Embedded Floating-Point Instructions ..........................186

5.4 Embedded floating-point results summary ...................................................................................2385.5 EFPU instruction timing ................................................................................................................253

5.5.1 EFPU single-precision vector floating-point instruction timing .....................................2545.5.2 EFPU single-precision scalar floating-point instruction timing .....................................255

5.6 Instruction forms and opcodes ......................................................................................................2565.6.1 Opcodes for EFPU vector floating-point instructions ....................................................2575.6.2 Opcodes for EFPU scalar single-precision floating-point instructions ..........................259

Chapter 6Signal Processing Extension APU (SPE APU)

6.1 Nomenclature and conventions .....................................................................................................261



6.2 SPE programming model ..............................................................................................................2616.2.1 SPE Status and Control Register (SPEFSCR) ................................................................2616.2.2 Accumulator ....................................................................................................................263

6.2.2.1 Context switch ..............................................................................................2646.2.3 GPRs and PowerPC Book E instructions .......................................................................2646.2.4 SPE available bit in MSR ...............................................................................................2646.2.5 SPE exception bit in ESR ...............................................................................................2646.2.6 SPE exceptions ...............................................................................................................264

6.2.6.1 SPE APU Unavailable exception ..................................................................2656.2.7 Exception priorities .........................................................................................................265

6.3 Integer SPE simple instructions ....................................................................................................2656.4 Integer SPE multiply, multiply-accumulate, and operation to accumulator instructions (complex integer instructions) 307

6.4.1 Multiply halfword instructions .......................................................................................3086.4.2 Multiply words instructions ............................................................................................3726.4.3 Add/subtract word to accumulator instructions ..............................................................4126.4.4 Initializing and reading the accumulator ........................................................................420

6.5 SPE vector load/store instructions .................................................................................................4226.6 SPE instruction timing ..................................................................................................................458

6.6.1 SPE integer simple instructions timing ...........................................................................4586.6.2 SPE load and store instruction timing .............................................................................4606.6.3 SPE complex integer instruction timing .........................................................................461

6.7 Instruction forms and opcodes ......................................................................................................4656.7.1 SPE vector integer simple instructions ...........................................................................4666.7.2 Opcodes for SPE load and store instructions ..................................................................4686.7.3 Opcodes for SPE complex integer instructions ..............................................................469

Chapter 7Interrupts and Exceptions

7.1 e200z759n3 interrupts ...................................................................................................................4797.2 Exception Syndrome Register (ESR) ............................................................................................4827.3 Machine State Register (MSR) ......................................................................................................484

7.3.1 Machine Check Syndrome Register (MCSR) .................................................................4867.4 Interrupt Vector Prefix Registers (IVPR) ......................................................................................4897.5 Interrupt Vector Offset Registers (IVORxx) .................................................................................4907.6 Hardware Interrupt Vector Offset Values (p_voffset[0:15]) ..........................................................4907.7 Interrupt definitions .......................................................................................................................491

7.7.1 Critical Input interrupt (IVOR0) .....................................................................................4917.7.2 Machine Check interrupt (IVOR1) .................................................................................492

7.7.2.1 Machine check causes ...................................................................................4927.7.2.1.1Error report machine check exceptions ........................................................4927.7.2.1.2Non-maskable interrupt machine check exceptions .....................................4977.7.2.1.3Asynchronous machine check exceptions ....................................................497

7.7.2.2 Machine check interrupt actions ...................................................................5047.7.2.3 Checkstop state .............................................................................................505



7.7.3 Data Storage interrupt (IVOR2) ......................................................................................5057.7.4 Instruction Storage interrupt (IVOR3) ............................................................................5067.7.5 External Input interrupt (IVOR4) ...................................................................................5077.7.6 Alignment interrupt (IVOR5) .........................................................................................5087.7.7 Program interrupt (IVOR6) ............................................................................................5087.7.8 Floating-Point Unavailable interrupt (IVOR7) ...............................................................5097.7.9 System Call interrupt (IVOR8) .......................................................................................5107.7.10 Auxiliary Processor Unavailable interrupt (IVOR9) ......................................................5107.7.11 Decrementer interrupt (IVOR10) ....................................................................................5107.7.12 Fixed-Interval Timer interrupt (IVOR11) .......................................................................5117.7.13 Watchdog Timer interrupt (IVOR12) ..............................................................................5127.7.14 Data TLB Error interrupt (IVOR13) ...............................................................................5127.7.15 Instruction TLB Error interrupt (IVOR14) .....................................................................5137.7.16 Debug interrupt (IVOR15) ..............................................................................................5147.7.17 System Reset interrupt ....................................................................................................5167.7.18 SPE/EFPU APU Unavailable interrupt (IVOR32) .........................................................5187.7.19 Embedded Floating-point Data interrupt (IVOR33) .......................................................5187.7.20 Embedded Floating-point Round interrupt (IVOR34) ....................................................5197.7.21 Performance monitor interrupt (IVOR35) ......................................................................519

7.8 Exception recognition and priorities .............................................................................................5207.8.1 Exception priorities .........................................................................................................522

7.9 Interrupt processing .......................................................................................................................5257.9.1 Enabling and disabling exceptions .................................................................................5267.9.2 Returning from an interrupt handler ...............................................................................527

7.10 Process switching ..........................................................................................................................527

Chapter 8Performance Monitor

8.1 Overview .......................................................................................................................................5298.2 Performance Monitor APU instructions ........................................................................................5308.3 Performance Monitor APU registers .............................................................................................531

8.3.1 Invalid PMR references ..................................................................................................5328.3.2 References to read-only PMRs .......................................................................................5328.3.3 Performance Monitor Global Control Register 0 (PMGC0) ..........................................5328.3.4 User Performance Monitor Global Control Register 0 (UPMGC0) ...............................5348.3.5 Performance Monitor Local Control A Registers (PMLCa0PMLCa3) ........................5348.3.6 User Performance Monitor Local Control A Registers (UPMLCa0UPMLCa3) .........5358.3.7 Performance Monitor Local Control B Registers (PMLCb0PMLCb3) ........................5358.3.8 User Performance Monitor Local Control B registers (UPMLCb0UPMLCb3) ...........5408.3.9 Performance Monitor Counter registers (PMC0PMC3) ...............................................5408.3.10 User Performance Monitor Counter registers (UPMC0UPMC3) .................................541

8.4 Performance monitor interrupt ......................................................................................................5418.5 Event counting ...............................................................................................................................542

8.5.1 MSR-based context filtering ...........................................................................................5428.6 Examples .......................................................................................................................................543



8.6.1 Chaining counters ...........................................................................................................5438.6.2 Thresholding ...................................................................................................................543

8.7 Event selection ..............................................................................................................................544

Chapter 9Power Management

9.1 Power management .......................................................................................................................5559.1.1 Active state .....................................................................................................................5559.1.2 Waiting state ....................................................................................................................5559.1.3 Halted state .....................................................................................................................5559.1.4 Stopped state ...................................................................................................................5569.1.5 Power management pins .................................................................................................5569.1.6 Power management control bits ......................................................................................5579.1.7 Software considerations for power management using wait instructions .......................5579.1.8 Software considerations for power management using Doze, Nap or Sleep ..................5589.1.9 Debug considerations for power management ................................................................558

Chapter 10Memory Management Unit

10.1 Overview .......................................................................................................................................55910.2 Effective to real address translation ..............................................................................................559

10.2.1 Effective addresses ..........................................................................................................55910.2.2 Address spaces ................................................................................................................55910.2.3 Process ID .......................................................................................................................56010.2.4 Translation flow ..............................................................................................................56010.2.5 Permissions .....................................................................................................................56210.2.6 Restrictions on 1 KB and 2 KB page size usage .............................................................563

10.3 Translation Lookaside Buffer (TLB) .............................................................................................56310.4 Configuration information .............................................................................................................564

10.4.1 MMU Configuration Register (MMUCFG) ...................................................................56410.4.2 TLB0 Configuration Register (TLB0CFG) ....................................................................56510.4.3 TLB1 Configuration Register (TLB1CFG) ....................................................................566

10.5 Software interface and TLB instructions ......................................................................................56710.5.1 TLB read entry instruction (tlbre) ...................................................................................56810.5.2 TLB write entry instruction (tlbwe) ................................................................................56810.5.3 TLB search instruction (tlbsx) ........................................................................................56810.5.4 TLB Invalidate (tlbivax) Instruction ...............................................................................56910.5.5 TLB synchronize instruction (tlbsync) ...........................................................................570

10.6 TLB operations ..............................................................................................................................57110.6.1 Translation reload ...........................................................................................................57110.6.2 Reading the TLB .............................................................................................................57110.6.3 Writing the TLB ..............................................................................................................57110.6.4 Searching the TLB ..........................................................................................................57110.6.5 TLB miss exception update ............................................................................................57210.6.6 IPROT invalidation protection ........................................................................................572



10.6.7 TLB load on reset ...........................................................................................................57210.6.8 The G bit .........................................................................................................................573

10.7 MMU control registers ..................................................................................................................57310.7.1 Data Exception Address Register (DEAR) .....................................................................57310.7.2 MMU Control and Status Register 0 (MMUCSR0) .......................................................57310.7.3 MMU assist registers (MAS) ..........................................................................................574

10.7.3.1 MMU Read/Write and Replacement Control register (MAS0) ....................57410.7.3.2 Descriptor Context and Configuration Control register (MAS1) .................57510.7.3.3 EPN and Page Attributes register (MAS2) ...................................................57610.7.3.4 RPN and Access Control register (MAS3) ...................................................57710.7.3.5 Hardware Replacement Assist Configuration register (MAS4) ...................57810.7.3.6 TLB Search Context Register 0 (MAS6) ......................................................579

10.7.4 MAS registers summary .................................................................................................58010.7.5 MAS register updates ......................................................................................................580

10.8 TLB coherency control ..................................................................................................................58110.9 Core interface operation for MMU control instructions ...............................................................581

10.9.1 Transfer type encodings for MMU control instructions .................................................58110.10 Effect of hardware debug on MMU operation ..............................................................................58210.11 External translation alterations for realtime systems ....................................................................583

Chapter 11L1 Cache

11.1 Overview .......................................................................................................................................58511.2 16 KB cache organization .............................................................................................................58611.3 Cache lookup .................................................................................................................................58711.4 Cache control .................................................................................................................................589

11.4.1 L1 Cache Control and Status Register 0 (L1CSR0) .......................................................58911.4.2 L1 Cache Control and Status Register 1 (L1CSR1) .......................................................59311.4.3 L1 Cache Configuration Register 0 (L1CFG0) ..............................................................59511.4.4 L1 Cache Configuration Register 1 (L1CFG1) ..............................................................596

11.5 Data cache software coherency .....................................................................................................59711.6 Address aliasing ............................................................................................................................59711.7 Cache Operation ............................................................................................................................598

11.7.1 Cache enable/disable .......................................................................................................59811.7.2 Cache fills .......................................................................................................................59811.7.3 Cache line replacement ...................................................................................................59911.7.4 Cache miss access ordering ............................................................................................59911.7.5 Cache-inhibited accesses ................................................................................................59911.7.6 Guarded accesses ............................................................................................................60011.7.7 Cache-inhibited guarded accesses ..................................................................................60011.7.8 Cache invalidation ..........................................................................................................60011.7.9 Cache flush/invalidate by set and way ............................................................................601

11.7.9.1 L1 Flush and Invalidate Control Register 0 (L1FINV0) ..............................60111.7.9.2 L1 Flush and Invalidate Control Register 1 (L1FINV1) ..............................602

11.8 Cache parity and EDC protection ..................................................................................................603



11.8.1 Cache error action control ...............................................................................................60411.8.1.1 L1CSR[0,1][I,D]CEA = 00, machine check generation on error .................60411.8.1.2 L1CSR[0,1][I,D]CEA = 01, correction/auto-invalidation on error ..............605

11.8.1.2.1Instruction cache errors ..............................................................................60511.8.1.2.2Data cache errors ........................................................................................60611.8.1.2.3Data cache line flush or invalidation due to reservation instructions

(l[b,h,w]arx, st[b,h,w]cx.) .......................................................................60711.8.2 Parity/EDC error handling for cache control operations and instructions ......................607

11.8.2.1 L1FINV[0,1] operations ...............................................................................60711.8.2.2 Cache touch instructions (dcbt, dcbtst, icbt) .................................................60811.8.2.3 icbi instructions .............................................................................................60811.8.2.4 dcbi instructions ............................................................................................60811.8.2.5 dcbst instructions ..........................................................................................60911.8.2.6 dcbf instructions ............................................................................................60911.8.2.7 dcbz instructions ...........................................................................................60911.8.2.8 Cache locking instructions (dcbtls, dcbtstls, dcblc, icbtls, icblc) .................610

11.8.3 Cache inhibited accesses and parity/EDC errors ............................................................61011.8.4 Snoop operations and parity/EDC errors ........................................................................61111.8.5 EDC checkbit/syndrome coding scheme generation ICache .....................................61111.8.6 EDC checkbit/syndrome coding scheme generation DCache ...................................61211.8.7 Cache error injection .......................................................................................................612

11.9 Push and store buffers ...................................................................................................................61311.10 Cache management instructions ....................................................................................................614

11.10.1Instruction cache block invalidate (icbi) instruction .......................................................61411.10.2Instruction cache block touch (icbt) instruction .............................................................61411.10.3Data cache block allocate (dcba) instruction ..................................................................61411.10.4Data cache block flush (dcbf) instruction .......................................................................61511.10.5Data cache block invalidate (dcbi) instruction ...............................................................61511.10.6Data cache block store (dcbst) instruction ......................................................................61511.10.7Data cache block touch (dcbt) instruction ......................................................................61511.10.8Data cache block touch for store (dcbtst) instruction .....................................................61511.10.9Data cache block set to zero (dcbz) instruction ..............................................................615

11.11 Touch instructions .........................................................................................................................61611.12 Cache line locking/unlocking APU ...............................................................................................616

11.12.1Overview .........................................................................................................................61611.12.2dcbtls data cache block touch and lock set ................................................................61811.12.3dcbtstls data cache block touch for store and lock set ...............................................61911.12.4dcblc data cache block lock clear ..............................................................................61911.12.5icbtls instruction cache block touch and lock set .......................................................62011.12.6icblc instruction cache block lock clear .....................................................................62111.12.7Effects of other cache instructions on locked lines .........................................................62211.12.8Flash clearing of lock bits ...............................................................................................622

11.13 Cache instructions and exceptions ................................................................................................62311.13.1Exception conditions for cache instructions ...................................................................62311.13.2Transfer type encodings for cache management instructions .........................................624



11.14 Sequential consistency ..................................................................................................................62511.15 Self-modifying code requirements ................................................................................................62511.16 Page table control bits ...................................................................................................................625

11.16.1Writethrough stores .........................................................................................................62611.16.2Cache-inhibited accesses ................................................................................................62611.16.3Memory coherence required ...........................................................................................62611.16.4Guarded storage ..............................................................................................................62611.16.5Misaligned accesses and the endian (E) bit ....................................................................626

11.17 Reservation instructions and cache interactions ............................................................................62611.18 Effect of hardware debug on cache operation ...............................................................................62711.19 Cache memory access for debug / error handling .........................................................................627

11.19.1Cache memory access via software ................................................................................62711.19.2Cache memory access through JTAG/OnCE port ..........................................................62811.19.3Cache Debug Access Control register (CDACNTL) ......................................................629

11.19.3.1 Cache Debug Access Data register (CDADATA) ........................................63011.20 Hardware Debug (Cache) Control Register 0 ...............................................................................63111.21 Hardware cache coherency ............................................................................................................632

11.21.1Coherency protocol .........................................................................................................63311.21.2Snoop command port ......................................................................................................63311.21.3Snoop request queue .......................................................................................................63511.21.4Snoop lookup operation ..................................................................................................63511.21.5Snoop errors ....................................................................................................................63611.21.6Snoop collisions ..............................................................................................................63611.21.7Snoop synchronization ....................................................................................................636

11.21.7.1 Synchronization port request ........................................................................63611.21.7.2 Snoop command port request .......................................................................637

11.21.8Starvation control ............................................................................................................63711.21.9Queue flow control .........................................................................................................63711.21.10Snooping in low power states .......................................................................................638

Chapter 12Debug Support

12.1 Overview .......................................................................................................................................63912.1.1 Software debug facilities ................................................................................................639

12.1.1.1 PowerISA 2.06 compatibility ........................................................................64012.1.2 Additional debug facilities ..............................................................................................64012.1.3 Hardware debug facilities ...............................................................................................64012.1.4 Sharing debug resources by software/hardware .............................................................641

12.1.4.1 Simultaneous hardware and software debug event handing .........................64112.2 Software debug events and exceptions ..........................................................................................642

12.2.1 Instruction Address Compare event ................................................................................64312.2.2 Data Address Compare event .........................................................................................644

12.2.2.1 Data Address Compare event status updates ................................................64512.2.3 Linked Instruction Address and Data Address Compare event ......................................65512.2.4 Trap debug event .............................................................................................................656



12.2.5 Branch Taken debug event ..............................................................................................65612.2.6 Instruction Complete debug event ..................................................................................65612.2.7 Interrupt Taken debug event ...........................................................................................65712.2.8 Critical Interrupt Taken debug event ..............................................................................65712.2.9 Return debug event .........................................................................................................65712.2.10Critical Return debug event ............................................................................................65812.2.11Debug Counter debug event ...........................................................................................65812.2.12External debug event ......................................................................................................65812.2.13Unconditional debug event .............................................................................................658

12.3 Debug registers ..............................................................................................................................65912.3.1 Debug address and value registers ..................................................................................65912.3.2 Debug Counter register (DBCNT) ..................................................................................66012.3.3 Debug Control and Status registers .................................................................................660

12.3.3.1 Debug Control Register 0 (DBCR0) .............................................................66112.3.3.2 Debug Control Register 1 (DBCR1) .............................................................66312.3.3.3 Debug Control Register 2 (DBCR2) .............................................................66512.3.3.4 Debug Control Register 3 (DBCR3) .............................................................66912.3.3.5 Debug Control Register 4 (DBCR4) .............................................................67412.3.3.6 Debug Control Register 5 (DBCR5) .............................................................67512.3.3.7 Debug Control Register 6 (DBCR6) .............................................................67712.3.3.8 Debug Status register (DBSR) ......................................................................679

12.3.4 Debug External Resource Control register (DBERC0) ..................................................68112.3.5 Debug Event Select register (DEVENT) ........................................................................68812.3.6 Debug Data Acquisition Message register (DDAM) ......................................................689

12.4 External debug support ..................................................................................................................68912.4.1 External debug registers ..................................................................................................690

12.4.1.1 External Debug Control Register 0 (EDBCR0) ............................................69112.4.1.2 External Debug Status Register 0 (EDBSR0) ...............................................69212.4.1.3 External Debug Status Register Mask 0 (EDBSRMSK0) ............................694

12.4.2 OnCE introduction ..........................................................................................................69612.4.3 JTAG/OnCE pins ............................................................................................................69812.4.4 OnCE internal interface signals ......................................................................................698

12.4.4.1 CPU debug request (dbg_dbgrq) ..................................................................69912.4.4.2 CPU debug acknowledge (cpu_dbgack) .......................................................69912.4.4.3 CPU address, attributes .................................................................................69912.4.4.4 CPU data .......................................................................................................699

12.4.5 OnCE interface signals ...................................................................................................69912.4.5.1 OnCE enable (jd_en_once) ...........................................................................69912.4.5.2 OnCE debug request/event (jd_de_b, jd_de_en) ..........................................70012.4.5.3 e200z759n3 OnCE debug output (jd_debug_b) ...........................................70012.4.5.4 e200z759n3 CPU clock on input (jd_mclk_on) ...........................................70012.4.5.5 Watchpoint events (jd_watchpt[0:29]) ..........................................................700

12.4.6 e200z759n3 OnCE controller and serial interface ..........................................................70112.4.6.1 e200z759n3 OnCE Status Register (OSR) ...................................................70112.4.6.2 e200z759n3 OnCE Command register (OCMD) ..........................................702



12.4.6.3 e200z759n3 OnCE Control Register (OCR) ................................................70612.4.7 Access to debug resources ..............................................................................................70812.4.8 Methods of entering debug mode ...................................................................................710

12.4.8.1 External debug request during RESET .........................................................71012.4.8.2 Debug request during RESET .......................................................................71012.4.8.3 Debug request during normal activity ..........................................................71112.4.8.4 Debug request during Waiting, Halted, or Stopped state ..............................71112.4.8.5 Software request during normal activity .......................................................71112.4.8.6 Debug notify halt instructions .......................................................................711

12.4.9 CPU Status and Control Scan Chain Register (CPUSCR) .............................................71212.4.9.1 Instruction Register (IR) ...............................................................................71212.4.9.2 Control State register (CTL) .........................................................................71312.4.9.3 Program Counter register (PC) .....................................................................71612.4.9.4 Write-Back Bus Register (WBBRlow, WBBRhigh) ....................................71612.4.9.5 Machine State Register (MSR) .....................................................................71712.4.9.6 Exiting debug mode and interrupt blocking .................................................717

12.4.10Instruction Address FIFO buffer (PC FIFO) ..................................................................71712.4.10.1 PC FIFO ........................................................................................................717

12.4.11Reserved registers (reserved) ..........................................................................................71912.5 Watchpoint support ........................................................................................................................71912.6 MMU and cache operation during debug ......................................................................................72112.7 Cache array access during debug ..................................................................................................72212.8 Basic steps for enabling, using, and exiting external debug mode ...............................................72212.9 Parallel Signature unit ...................................................................................................................723

12.9.1 Parallel Signature Control Register (PSCR) ...................................................................72512.9.2 Parallel Signature Status Register (PSSR) ......................................................................72512.9.3 Parallel Signature High Register (PSHR) .......................................................................72612.9.4 Parallel Signature Low Register (PSLR) ........................................................................72612.9.5 Parallel Signature Counter Register (PSCTR) ................................................................72712.9.6 Parallel Signature Update High Register (PSUHR) .......................................................72712.9.7 Parallel Signature Update Low Register (PSULR) .........................................................727

Chapter 13Nexus 3 Module

13.1 Introduction ...................................................................................................................................72913.1.1 General description .........................................................................................................72913.1.2 Terms and definitions ......................................................................................................72913.1.3 Feature list .......................................................................................................................73013.1.4 Functional block diagram ...............................................................................................732

13.2 Enabling Nexus 3 operation ..........................................................................................................73213.3 TCODEs supported .......................................................................................................................73313.4 Nexus 3 programmers model .......................................................................................................739

13.4.1 Client Select Control register (CSC) ..............................................................................74113.4.2 Port Configuration Register (PCR) reference only ....................................................74113.4.3 Nexus Development Control Register 1 (DC1) ..............................................................742



13.4.4 Nexus Development Control Registers 2 and 3 (DC2, DC3) .........................................74413.4.5 Nexus Development Control Register 4 (DC4) ..............................................................74813.4.6 Development Status register (DS) ..................................................................................74913.4.7 Watchpoint Trigger registers (WT, PTSTC, PTETC, DTSTC, DTETC) ........................74913.4.8 Nexus Watchpoint Mask register (WMSK) ....................................................................75413.4.9 Nexus Overrun Control Register (OVCR) ......................................................................75513.4.10Data Trace Control Register (DTC) ................................................................................75613.4.11Data Trace Start Address Registers (DTSA14) ............................................................75813.4.12Data Trace End Address registers (DTEA14) ...............................................................75813.4.13Read/Write Access Control/Status register (RWCS) ......................................................76013.4.14Read/Write Access Data (RWD) .....................................................................................76113.4.15Read/Write Access Address register (RWA) ..................................................................763

13.5 Nexus 3 register access via JTAG/OnCE ......................................................................................76313.6 Nexus message fields ....................................................................................................................764

13.6.1 TCODE field ...................................................................................................................76413.6.2 Source ID field (SRC) .....................................................................................................76413.6.3 Relative address field (U-ADDR) ...................................................................................76413.6.4 Full address field (F-ADDR) ..........................................................................................76513.6.5 Address space indication field (MAP) ............................................................................765

13.7 Nexus message queues ..................................................................................................................76613.7.1 Message queue overrun ..................................................................................................76613.7.2 CPU stall .........................................................................................................................76613.7.3 Message suppression .......................................................................................................76613.7.4 Nexus message priority ...................................................................................................76713.7.5 Data Acquisition Message (DQM) priority loss response ..............................................76813.7.6 Ownership Trace Message (OTM) priority loss response ..............................................76813.7.7 Program Trace Message (PTM) priority loss response ...................................................76813.7.8 Data Trace Message (DTM) priority loss response ........................................................768

13.8 Debug Status messages .................................................................................................................76813.9 Error messages ..............................................................................................................................76913.10 Ownership trace .............................................................................................................................769

13.10.1Overview .........................................................................................................................76913.10.2Ownership Trace Messaging (OTM) ..............................................................................769

13.11 Program trace ................................................................................................................................77013.11.1Branch Trace messaging types ........................................................................................770

13.11.1.1 Zen Indirect Branch message instructions ....................................................77113.11.1.2 Zen Direct Branch Message instructions ......................................................77113.11.1.3 BTM using Branch History Messages ..........................................................77213.11.1.4 BTM using Traditional Program Trace messages .........................................772

13.11.2BTM Message formats ....................................................................................................77213.11.2.1 Indirect Branch Messages (history) ..............................................................77213.11.2.2 Indirect Branch Messages (traditional) .........................................................77313.11.2.3 Direct Branch Messages (traditional) ...........................................................773

13.11.3Program Trace message fields ........................................................................................77313.11.3.1 Sequential Instruction Count field (ICNT) ...................................................773



13.11.3.2 Branch/Predicate Instruction History (HIST) ...............................................77413.11.3.3 Execution mode indication ...........................................................................774

13.11.4Resource Full Messages ..................................................................................................77513.11.5Program Correlation Messages (PCM) ...........................................................................775

13.11.5.1 Program Correlation Message generation for TLB update with new address translation .....................................................................................................................77713.11.5.2 Program Correlation Message generation for TLB invalidate (tlbivax) operations ......................................................................................................................77813.11.5.3 Program Correlation Message generation for PID updates or MSRIS updates .........................................................................................................................................778

13.11.6Program trace overflow error messages ..........................................................................77813.11.7Program trace synchronization messages .......................................................................77813.11.8Enabling Program Trace .................................................................................................78013.11.9Program Trace timing diagrams (2 MDO / 1 MSEO configuration) ..............................781

13.12 Data Trace ....................................................................................................................................78213.12.1Data Trace Messaging (DTM) ........................................................................................78213.12.2DTM Message formats ...................................................................................................782

13.12.2.1 Data Write Messages ....................................................................................78213.12.2.2 Data Read Messages .....................................................................................78213.12.2.3 Data Trace Synchronization Messages .........................................................783

13.12.3DTM operation ...............................................................................................................78413.12.3.1 Data trace windowing ...................................................................................78413.12.3.2 Data access / instruction access data tracing ................................................78513.12.3.3 Data trace filtering ........................................................................................78513.12.3.4 Zen bus cycle special cases ...........................................................................785

13.12.4Data Trace Timing Diagrams(8 MDO / 2 MSEO configuration) ...................................78613.13 Data Acquisition messaging ..........................................................................................................786

13.13.1Data Acquisition ID Tag field .........................................................................................78713.13.2Data Acquisition Data field ............................................................................................78713.13.3Data Acquisition Trace event ..........................................................................................787

13.14 Watchpoint Trace Messaging ........................................................................................................78713.14.1Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration) ...................................789

13.15 Nexus 3 read/write access to memory-mapped resources .............................................................79013.15.1Single write Access .........................................................................................................79013.15.2Block write access ..........................................................................................................79113.15.3Single read access ...........................................................................................................79113.15.4Block read access ............................................................................................................79213.15.5Error handling .................................................................................................................792

13.15.5.1 AHB read/write error ....................................................................................79313.15.5.2 Access termination ........................................................................................793

13.15.6Read/write access error message ....................................................................................79313.16 Nexus 3 pin interface .....................................................................................................................793

13.16.1Pins implemented ............................................................................................................79313.16.2Pin protocol .....................................................................................................................796

13.17 Rules for output messages .............................................................................................................798



13.18 Auxiliary port arbitration ..............................................................................................................79813.19 Examples .......................................................................................................................................79813.20 Electrical characteristics ................................................................................................................80113.21 IEEE 1149.1 (JTAG) RD/WR sequences ......................................................................................801

13.21.1JTAG sequence for accessing internal Nexus registers ..................................................80113.21.2JTAG sequence for read access of memory-mapped resources ......................................80213.21.3JTAG sequence for write access of memory-mapped resources ....................................802

Chapter 14External Core Complex Interfaces

14.1 Signal index ...................................................................................................................................80614.2 Signal descriptions ........................................................................................................................813

14.2.1 e200z759n3 processor clock (m_clk) .............................................................................81414.2.2 Reset-related signals .......................................................................................................814

14.2.2.1 Power-on reset (m_por) ................................................................................81414.2.2.2 Reset (p_reset_b) ..........................................................................................81414.2.2.3 Watchdog reset status (p_wrs[0:1]) ..............................................................81514.2.2.4 Debug reset control (p_dbrstc[0:1]) ..............................................................81514.2.2.5 Reset base (p_rstbase[0:29]) .........................................................................81514.2.2.6 Reset endian mode (p_rst_endmode) ............................................................81514.2.2.7 Reset VLE Mode (p_rst_vlemode) ...............................................................81514.2.2.8 JTAG/OnCE reset (j_trst_b) .........................................................................815

14.2.3 Address and data buses ...................................................................................................81614.2.3.1 Address bus (p_d_haddr[31:0], p_i_haddr[31:0]) ........................................81614.2.3.2 Read data bus (p_d_hrdata[63:0], p_i_hrdata[63:0]) ....................................81614.2.3.3 Write data bus (p_d_hwdata[63:0]) ..............................................................816

14.2.4 Transfer attribute signals .................................................................................................81714.2.4.1 Transfer type (p_d_htrans[1:0], p_i_htrans[1:0]) .........................................81714.2.4.2 Write (p_d_hwrite, p_i_hwrite) ....................................................................81714.2.4.3 Transfer size (p_d_hsize[1:0], p_i_hsize[1:0]) .............................................81714.2.4.4 Burst type (p_d_hburst[2:0], p_i_hburst[2:0]) ..............................................81814.2.4.5 Protection control (p_d_hprot[5:0], p_i_hprot[5:0]) ....................................81814.2.4.6 Transfer data error (p_d_htrans_derr) ...........................................................82014.2.4.7 Globally coherent access (p_d_gbl) .........................................................82014.2.4.8 Cache way replacement (p_d_wayrep[0:1], p_i_wayrep[0:1]) ....................820

14.2.5 Byte lane specification ....................................................................................................82014.2.5.1 Unaligned access (p_d_hunalign, p_i_hunalign) ..........................................82114.2.5.2 Byte strobes (p_d_hbstrb[7:0], p_i_hbstrb[7:0]) ..........................................821

14.2.6 Transfer control signals ...................................................................................................83114.2.6.1 Transfer ready (p_d_hready, p_i_hready) .....................................................83114.2.6.2 Transfer response (p_d_hresp[2:0], p_i_hresp[1:0]) ....................................83114.2.6.3 Bus stall global write request (p_stall_bus_gwrite) ......................................832

14.2.7 AHB clock enable signals ...............................................................................................83214.2.7.1 Instruction AHB clock enable (p_i_ahb_clken) ...........................................83214.2.7.2 Data AHB clock enable (p_d_ahb_clken) ....................................................833



14.2.8 Master ID configuration signals .....................................................................................83314.2.8.1 CPU master ID (p_masterid[3:0]) .................................................................83314.2.8.2 Nexus master ID (nex_masterid[3:0]) ..........................................................833

14.2.9 Coherency control signals ...............................................................................................83314.2.9.1 Snoop ready (p_snp_rdy) ..............................................................................83314.2.9.2 Snoop request (p_snp_req) ...........................................................................83414.2.9.3 Snoop command input (p_snp_cmd_in[0:1]) ...............................................83414.2.9.4 Snoop request ID input (p_snp_id_in[0:3]) ..................................................83414.2.9.5 Snoop address input (p_snp_addr_in[0:26]) .................................................83514.2.9.6 Snoop acknowledge (p_snp_ack) .................................................................83514.2.9.7 Snoop request ID output (p_snp_id_out[0:3]) ..............................................83514.2.9.8 Snoop response (p_snp_resp[0:4]) ................................................................83514.2.9.9 Cache stalled (p_cac_stalled) ........................................................................83614.2.9.10 Data cache enabled (p_d_cache_en) .............................................................836

14.2.10Memory synchronization control signals ........................................................................83614.2.10.1 Synchronization request in (p_sync_req_in) ................................................83614.2.10.2 Synchronization request acknowledge out (p_sync_ack_out) ......................83614.2.10.3 Synchronization request out (p_sync_req_out) ............................................83714.2.10.4 Synchronization request acknowledge in (p_sync_ack_in) ..........................837

14.2.11Interrupt signals ..............................................................................................................83714.2.11.1 External input interrupt request (p_extint_b) ................................................83714.2.11.2 Critical input interrupt request (p_critint_b) .................................................83814.2.11.3 Non-maskable input interrupt request (p_nmi_b) .........................................83814.2.11.4 Interrupt pending (p_ipend) ..........................................................................83814.2.11.5 Autovector (p_avec_b) .................................................................................83814.2.11.6 Interrupt vector offset (p_voffset[0:15]) .......................................................83814.2.11.7 Interrupt vector acknowledge (p_iack) .........................................................83914.2.11.8 Machine check (p_mcp_b) ............................................................................839

14.2.12External translation alteration signals .............................................................................83914.2.12.1 External PID enable (p_extpid_en) ...............................................................83914.2.12.2 External PID in (p_extpid[6:7]) ....................................................................839

14.2.13Timer facility signals ......................................................................................................84014.2.13.1 Timer disable (p_tbdisable) ..........................................................................84014.2.13.2 Timer external clock (p_tbclk) ......................................................................84014.2.13.3 Timer interrupt status (p_tbint) .....................................................................840

14.2.14Processor reservation signals ..........................................................................................84014.2.14.1 CPU reservation status (p_rsrv) ....................................................................84014.2.14.2 CPU reservation clear (p_rsrv_clr) ...............................................................840

14.2.15Miscellaneous processor signals .....................................................................................84114.2.15.1 CPU ID (p_cpuid[0:7]) .................................................................................84114.2.15.2 PID0 outputs (p_pid0[0:7]) ...........................................................................84114.2.15.3 PID0 update (p_pid0_updt) ..........................................................................84114.2.15.4 System version (p_sysvers[0:31]) .................................................................84114.2.15.5 Processor version (p_pvrin[16:31]) ..............................................................84114.2.15.6 HID1 system control (p_hid1_sysctl[0:7]) ...................................................842



14.2.15.7 Debug event outputs (p_devnt_out[0:7]) ......................................................84214.2.16Processor state signals ....................................................................................................842

14.2.16.1 Processor mode (p_mode[0:3]) .....................................................................84214.2.16.2 Processor execution pipeline status (p_pstat_pipe0[0:5], p_pstat_pipe1[0:5]) .........................................................................................................................................84214.2.16.3 Branch prediction status (p_brstat[0:1]) .......................................................84314.2.16.4 Processor exception enable MSR values (p_msr_EE, p_msr_CE, p_msr_DE, p_msr_ME) ...................................................................................................................84414.2.16.5 Processor return from interrupt (p_rfi, p_rfci, p_rfdi, p_rfmci) ...................84414.2.16.6 Processor machine check (p_mcp_out) ........................................................844

14.2.17Power management control signals ................................................................................84414.2.17.1 Processor waiting (p_waiting) ......................................................................84414.2.17.2 Processor halt request (p_halt) ......................................................................84514.2.17.3 Processor halted (p_halted) ...........................................................................84514.2.17.4 Processor stop request (p_stop) ....................................................................84514.2.17.5 Processor stopped (p_stopped) .....................................................................84514.2.17.6 Low-power mode signals (p_doze, p_nap, p_sleep) .....................................84514.2.17.7 Wakeup (p_wakeup) .....................................................................................845

14.2.18Performance monitor signals ..........................................................................................84614.2.18.1 Performance monitor event (p_pm_event) ...................................................84614.2.18.2 Performance monitor counter 0 overflow state (p_pmc0_ov) ......................84614.2.18.3 Performance monitor counter 1 overflow state (p_pmc1_ov) ......................84614.2.18.4 Performance monitor counter 2 overflow state (p_pmc2_ov) ......................84614.2.18.5 Performance monitor counter 3 overflow state (p_pmc3_ov) ......................84614.2.18.6 Performance monitor counter 3 qualifier inputs (p_pmc[0,1,2,3]_qual) ......846

14.2.19Debug event input signals ...............................................................................................84614.2.19.1 Unconditional debug event (p_ude) ..............................................................84714.2.19.2 External debug event 1 (p_devt1) .................................................................84714.2.19.3 External debug event 2 (p_devt2) .................................................................847

14.2.20Debug event output signals (p_devnt_out[0:7]) .............................................................84714.2.21Debug/emulation (Nexus 1/ OnCE) support signals .......................................................847

14.2.21.1 OnCE enable (jd_en_once) ...........................................................................84814.2.21.2 Debug session (jd_debug_b) .........................................................................84814.2.21.3 Debug request (jd_de_b) ...............................................................................84814.2.21.4 DE_b active high output enable (jd_de_en) .................................................84914.2.21.5 Processor clock on (jd_mclk_on) .................................................................84914.2.21.6 Watchpoint events (jd_watchpt[0:29]) ..........................................................849

14.2.22Development support (Nexus 3) signals .........................................................................84914.2.23JTAG support signals ......................................................................................................850

14.2.23.1 JTAG/OnCE serial input (j_tdi) ....................................................................85014.2.23.2 JTAG/OnCE serial clock (j_tclk) ..................................................................85014.2.23.3 JTAG/OnCE serial output (j_tdo) .................................................................85014.2.23.4 JTAG/OnCE test mode select (j_tms) ...........................................................85014.2.23.5 JTAG/OnCE test reset (j_trst_b) ...................................................................85114.2.23.6 Test-Logic-Reset (j_tst_log_rst) ...................................................................851



14.2.23.7 Run-Test/Idle (j_rti) ......................................................................................85114.2.23.8 Capture IR (j_capture_ir) ..............................................................................85114.2.23.9 Shift IR (j_shift_ir) .......................................................................................85114.2.23.10Update IR (j_update_ir) ...............................................................................85214.2.23.11Capture DR (j_capture_dr) ..........................................................................85214.2.23.12Shift DR (j_shift_dr) ....................................................................................85214.2.23.13Update DR w/write (j_update_gp_reg) .......................................................85214.2.23.14Register select (j_gp_regsel) .......................................................................85214.2.23.15Enable OnCE register select (j_en_once_regsel) ........................................85214.2.23.16External Nexus register select (j_nexus_regsel) ..........................................85314.2.23.17External LSRL register select (j_lsrl_regsel) ..............................................85314.2.23.18Serial data (j_serial_data) ............................................................................85314.2.23.19Key data in (j_key_in) .................................................................................854

14.2.24JTAG ID signals ..............................................................................................................85414.2.24.1 JTAG ID sequence (j_id_sequence[0:1]) ......................................................85514.2.24.2 JTAG ID sequence (j_id_sequence[2:9]) ......................................................85514.2.24.3 JTAG ID version (j_id_version[0:3]) ............................................................855

14.2.25Test signals ......................................................................................................................85614.3 Timing diagrams ............................................................................................................................856

14.3.1 AHB clock enable and the internal HCLK .....................................................................85614.3.2 Processor instruction/data transfers ................................................................................856

14.3.2.1 Basic read transfer cycles .............................................................................85814.3.2.2 Read transfer with wait state .........................................................................85914.3.2.3 Basic write transfer cycles ............................................................................86014.3.2.4 Write transfer with wait states ......................................................................86214.3.2.5 Read and write transfers ...............................................................................86314.3.2.6 Misaligned accesses ......................................................................................86714.3.2.7 Burst accesses ...............................................................................................87014.3.2.8 Error termination operation ..........................................................................874

14.3.3 Memory synchronization control operation ....................................................................87714.3.4 Cache coherency interface operation ..............................................................................880

14.3.4.1 Stop mode entry/exit and snoop ready signaling ..........................................88414.3.5 Power management .........................................................................................................88514.3.6 Interrupt Interface ...........................................................................................................88614.3.7 Time base interface ....................................

e200z759n3crm: e200z759n3 core reference manual · 1.1.2 microarchitecture summary ... 8.3.9...

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