EC – 316 Microprocessor Lab Project

Netaji Subhas Institute of Technology

Tambola Controller using 8085

Submitted to – Prof. Dhananjay V. Gadre

By – Ishaan Kubba Kartik Goel 66/EC/13 76/EC/13 ECE-2 ECE-2

Acknowledgements

We would like to acknowledge the guidance and mentorship provided by Prof. Dhananjay V. Garde during the course of this semester, inspiring and motivating us throughout. He helped us conceive our project and provided us with solutions of various potential problems. Also we are very grateful to all our friends and family members who supported us throughout this venture.

Index

1.Synopsis 2.Introduction and Justification 3.Timeline Comparison 4.Block Diagram and Schematics 5.Project Description i) Concepts Involved ii) Performance Criteria iii) Hardware Description iv) Software Description 6.Testing Procedure 7.Conclusion 8.Gallery 9.Bibliography

Synopsis

Tambola Controller is an Intel 8085 based project made for simplifying and easing the game process. It generates a random number from 1 to 90 and displays it on a LED Matrix having 90 LED’s, one for each number. The numbers, which are already called out will be represented by glowing LED’s except the last called number which will be blinking.

The controller physically consist of three parts:1) Main board containing 8085 chip and its control

logic2) A 9x10 LED Matrix3) A LED Matrix driver board

The LED Matrix driver board is attached permanently with LED Matrix and consists of one ULN2803A and one Darlington pair (BC547 and BD139) for low side switching and two UDN2981 for high side switching.

The LED Matrix is multiplexed i.e. only one row of LED Matrix will be glowing at a particular instant of time but the switching between different rows is so fast that due to persistence of vision, all rows will appear to be glowing at same time.

For multiplexing, an astable multivibrator is used on the main board which keep on interrupting the 8085 at a rate which is sufficiently high for multiplexing without any flickering.

The project aims at removing the manual labour of making ninety paper pieces. Also, it ensures the randomness of the number called, leading to smooth and fair conduct of game without any cheating.

Introduction and Justification

Tambola is game of luck. It involves a person calling out numbers from the set of 1-90. Players are required to cross out the numbers on the sheets provided to them if there is a match. In the traditional method, there is a bowl containing 90 folded paper pieces. A number from 1 to 90 is written on all the paper pieces without repeating. The person managing the game picks a piece of paper randomly and calls the number written on it. The player whose all numbers have been called out will win the game.

Problems with traditional method:1. Need to cut 90 paper pieces, every time you play

the game.2. Paper wear out by repetitive folding and

unfolding.3. As the paper wears out, the numbers become more

predictable.4. Extent of randomness is very low.5. It becomes very cumbersome and tiresome to handle

90 paper pieces.6. Need to make a record of numbers which have come

to check for the winner.7. Cheating by person managing the pieces are highly

likely.

Our project i.e. Tambola Controller removes all those problems. It contains a 8085 board, a led matrix driver board and a led matrix (9 x 10), each led representing a number from 1 to 90. There is a button on 8085 board which whenever pressed will randomly glow an led, thus generating a random number. Extent of randomness is very high due to the algorithm design. No need to make record of numbers which are called out as they will be

represented by glowing LED’s and the last number called will be represented by blinking a LED. The electronic can be fully automated in further versions and avoids the need of a person to manage the game. Also the matrix can be scaled up to any extent depending on the gathering. Announcement system can also be introduced.

Timeline Comparison

Proposed Gantt Chart in the IPR submitted.

True progress Gantt Chart

Inference

From two Gantt charts, it is concluded that the rate determining steps were Making schematics for 8085, Routing, Board fabrication and Soldering, Code testing on hardware.Due to mid-semester examination in beginning of March, making schematics for 8085 was delayed, after which the approximate time taken for completion of other activities was same as decided. Also, it is observed that no extra time allocation for code making was required. Mostly due to the time saved when board was sent for fabrication.

Block Diagram and Schematics for the project

Main 8085 board schematic

LED matrix and driver board schematic

Project Description

A microprocessor based project can be sub divided into the very classical divisions namely the Hardware of the Project and the code running on the system. Before designing any of the two mentioned above it is very important to have a vision regarding how to implement the project and what performance testing criteria the project must fulfill.

Concepts involved –

1. Random Number Generation – The aim of the project is to generate random numbers and display on a matrix. The

domain for the Tambola game is, numbers ranging 1-90 with no repetitions because each number is unique. Selection of the random number was to be initiated by the user from the pool of 1-90 on a button press. This was achieved by having a regular source of interrupt on the system counting from 1 to 90 at frequencies of the order of 1000 counts per second. The occasional user input is used to pause this counting process, and take in the current value pointed by the random counter. This number is flagged to indicate that it has already been used up. Counting numbers from 1-90 requires 7 bits of data and hence the 8 bit is used as a flag. Flag set indicates the value has already been used. To avoid this situation, the program is such that, it automatically picks up the next unused value in the sequence one the counter is paused.

2.Multiplexing - Multiplexing is to share a common resource in a system, when the number of requests for that resource is large without affecting system performance. Time division multiplexing is when, a certain resource is allocated to different data streams for a fixed percentage of time in the total time allocated for that resource. In this project the common resource being the microprocessor outputting the data for the display. In an un-multiplexed display system, as many number of pins are required as many pixels present in the display, thereby increasing the hardware requirements exponentially. In a multiplexed display, the display matrix is subdivided into rows and columns. At a time only one row contains a valid data and rest of the rows are turned off. The data is outputted on the column. The time allocated of each row to turn on with its valid data is fixed. In the next refresh period, a newer row is turned on along with its data while others remain off. Above a certain limit of the refresh rate, human eyes cannot distinguish between the subtle changes

happening on the display and perceive everything at once. This is called persistence of vision. The nominal value of the refresh rate is taken to be 100Hz. This allows the sharing of the microprocessor data bus for the display and keeping the number of ports to a minimum.

Performance criteria for the project

1. ISR Rate – The rate at which the display is being refreshed or multiplexed is called POV rate. For a 9x10 LED matrix that is being multiplexed row wise, 100Hz refresh rate per row is chosen. This in turn results in the entire display being refreshed at 900Hz. This is an optimum value for persistence of vision. The interrupt that is being used to refresh the display is also being used as the random counter. Also the length of the ISR is important, as a longer ISR will leave lesser time for the main programme, that checks for the user inputs. Thereby missing the user input. Length of the ISR and POV rate are interrelated. The time period of the POV frequency will decide the percentage of time available with the system to spend in polling the user switch. Hence, reduced ISR rate is preferable. In this project a variable ISR rate mechanism is available by using a potentiometer. Currently ISR rate is set to 700 Hz i.e. 78Hz per row which is sufficient for the display as well as user switch monitoring. Hence satisfying both the criteria.

2. Brightness of the LED Matrix – Under non-multiplexed situations, the brightness of the matrix is easier to control by choosing a appropriate transistor and resistor. Under multiplexed situations, the calculations become a little more complex. Since each row is not turned on for the entire duration, the peak current through the LED must increase so as to achieve the same average brightness as in a no multiplexed situation. The current through the LED increases by a factor equal to the number of multiplexed rows that is nine in this case. Also suitable transistors must be chosen on the high side to provide nine fold current from the power supply. On the low side the transistor not only needs to sink the increased current of a single led but from all the led ‘s connected to that row.

Hence further increasing the max current requirement of the transistor. In general increased IC max reduces the HFE of the transistor. This causes the system to draw more current from the ports. This problem can be solved using Darlington pair transistors.

Calculations for multiplexing

I average for LED = 4mAI multiplexed for LED = 9*4mA (number of rows*Iav)Vdrop LED at 36mA = 2VVdrop UDN 2981 at 36mA = 1.5VVdrop ULN2803 at 36*10 mA = 1.2V (number of LED’s per row * multiplexed current)

Using KVL

Vcc = Vdrop led + VCE sat UDN2981 + VCE sat ULN2803 + I*R

R = VCC – (Vdrop LED + VCEsat UDN2981 + VCEsat ULN2803)/I

Substituting the above values R = 8.5 ohmsUsing the nearest value = 10ohms

Calculation for SOD – VCE drop for Darlington pair = 150 mvThere extra voltage drop = 1.2 - .15 = 1.05V must come across the resistorR extra = 1.05V/36mA = 30 ohmUsed the nearest value of 33 ohmHence total resistance for the row with Darlington pair to have the same brightness = 43 ohmsCalculation for its base resistorVcc – (IC/(HFE net))*R = Vbe1 + Vbe2 Vbe1 = Vbe2 = 0.7VHFE net = 125*25R = 31KOhmUsing the nearest value of 33KOhm

(All the data has been taken from the data sheet of the IC UDN2981, ULN2803, BC547, BD139 and Vdrop LED was

experimentally found. Prior to finalizing the values, simulation was performed on Proteous software)

3. Randomness of number generation – The system employed above results in highly random number generation due the fact that 700Hz of ISR rate is much higher than the rates at which humans can interact with a system. Also there is no pseudo – random algorithm involved for the number generation.

Hardware Description

8085 board reference diagram

Power Supply – The 8085 system is powered using an external 5V source using a Micro- USB (bottom side). Capacitors are used to minimize any kind of noise from the source on generated in the system due to high frequency switch. Indication LED is also used to indicate the system is powered on. A XLR-02

connector is provided on the board to power the matrix.

Microprocessor – This is the heart of the system. The 8085 microprocessor fetches the instruction from the memory and executes them. There are male headers connected along side the 8085 so as to help in probing the signals via oscilloscope. An address latch is used along side the 8085 to latch the lower order addresses generated by the processor during the first T state.

Astable Multivibrator – A 555 timer based astable multivibrator used to interrupt the 8085. Interrupt frequency can be adjusted using a potentiometer (bottom side).

EEPROM – An ATMEL 28C64 EEPROM is used to store the code. It is installed in the first 8K block of the 64K memory space available to 8085.

RAM – This is the volatile memory that resets it contents with every power on/off. This is used to store the temporary data generated during the execution of the programme. A HYUNDAI 6264 RAM is used. It is installed in the last 8K block offered by 8085.

Decoding logic – A combination of 74HCT138 (active low) decoder and a 74HCT02 nor gate is used to partially decode the memory space and the ports. HCT is a fabrication technology for the IC. HCT stands for high speed CMOS with TTL thresholds. This ensures compatibility with the older TTL based 8085 system.

Ports - Three ports have been used. Two for column data of the matrix and one for the row data. 74HCT573 latch has been used. The system is capable of being expanded for 4 ports without additional hardware out of which 3 have already been consumed.

User input and Reset – There are two push buttons on the system. The bigger one is connect to the SID pin of the 8085 as is used to provide the user input to the system and the smaller push button resets the system. The reset is a hot reset. That means the 8085 is reset but the contents of the RAM are not cleared which happens on a power on/cold reset.

Matrix driver reference diagram

Software Description

Useful information from the code

Total 216 instructions in the codeTotal size = 465 bytes

ROM address range – 0000h to 1FFFhRAM address range - E000h to FFFFhOutput port 1 – 00h address - LSB of Column dataOutput port 2 – 40h address - MSB of Column dataOutput port 3 + SOD – 80h address - Row dataRST 7.5 interrupt address location – 003ChRandom number counter address - E200hRAM addresses containing 1 to 90 numbers - E001h to E05AhRAM addresses containing led matrix data - E702h to E713hCoordinates of blinking LED - E300h (row number), E301h (column number)Last random number generated - E210hRow pointer - E500hNumber of interrupt cycles - E400hRow data - E501h

Function of registers for main programD - row number of last second ledE - column number of last second ledB - last valid random number generated

Main Programme flow chart

ISR flow chart

Algorithm description of certain blocks used in flow chart:

Switch monitoringInput pin i.e. sid pin is read in a blocking manner (infinite loop) until its pressed. As soon as it is pressed, a delay of 10ms is given for debouncing of switch and sid pin is read again to check if switch is still pressed. Same is repeated until switch is released. A new random number is generated only after the switch is pressed and released.

Calculation of row and column number from data in BThe data in B is repeatedly subtracted by 10 until it becomes lower than 10. The lower than 10 value obtained is the column number and the number of 10s subtracted from data in B gives row number.

Making LED pointed by D and E permanently highIt’s a three step process. Firstly, using the row number, H and L registers are made to store the address of that location in which data for that row is stored. Secondly, as there are 10 columns, therefore, data for a row is of two bytes and accordingly the H L register pair is incremented, if column number is greater than 8. Thirdly, a data value is generated by storing a value of 1 in accumulator and rotating it clockwise as many times as the column number. The data value thus produced is ORed with the value of memory location pointed by H L register pair.

Inverting the state of LED pointed by E300 and E301All the steps are similar to above one, but the only difference is that produced value id XORed instead of ORed with value of memory location pointed by H L register pair to invert the state of LED.

Testing Procedure

Hardware test – Before uploading the sample codes, all the IC’s were tested on an IC tester. The main board was fabricated by PCB Power. Their procedure includes electrical testing of the boards shipped.

Sample code tests –

SID/SOD Test – The aim is to mirror the input on the SID pin of 8085 on its SOD pin. Due to lack of a SOD indication LED on the board, oscilloscope was used to check the out.

Port Test – Square waves were generated and outputted on each of the ports. This ensured the latches were working fine along with the port decoding logic.

RAM Test - A set of 0 -255 numbers was stored in the ram and was outputted on the port to ensure the ram was being written and read correctly.

ISR Test – The SID/SOD test was mapped to be used in the ISR. This ensured that the system was accepting interrupts and returning back to the main programme.

Multiplexing Test 1 – In this test, internal registers of the 8085 were used to multiplex the display without the use of interrupts. This ensured that the internal registers were working correctly along with the matrix and its drivers.

Multiplexing Test 2 – In this test ram and the interrupts were used to test the display. This formed the foundation for the main code.

Main Code Testing

The main code was broken up into various blocks. Each block was tested along with the previously working block. We faced one major problem while testing the main code.

Ghost LED on the matrix – Along with the correct display on the matrix, few LED prior to the correct row were faintly glowing. These are called the Ghost LED’s. This was due to the fact that the data on the columns was being shared between the two rows while multiplexing. This was removed by turning off all the rows before new data was placed on the column.

(On the left – EEPROM programmer. Arduino Nano based. It was used to burn code on the EEPROM being used in 8085 system)(On the right – the 8085 board while testing)

Conclusion

The wonderful choreography behind a working project can only be seen when the hardware and the software work in tandem. One must try to work towards perfection and not give up before its time for best results. Documentation and proper presentation of the project is a must if one truly wishes to attain all the appreciation their hardwork and the project deserves.Last but not the least one of our friends and our mentor correctly pointed out “ We have faced a lot of problems,

which we solve, which has made us better engineers and individuals.”Gallery

Matrix Soldering

Connections Underneath The matrix Driver

Bibliography

Hardcopy Resources –

Microprocessor Architecture, Programming, and Applications with the 8085 by Ramesh Gaonkar Fifth edition, Penram International Publishing.ISBN – 81-87972-09-2

Online Resources – Datasheets of various IC’s

74573 - NXP http://www.nxp.com/documents/data_sheet/74HC_HCT573.pdf

74138 - TI http://www.ti.com/lit/ds/symlink/sn74ls138.pdf

7402 - TIhttp://www.ti.com/product/SN7402

28C64 - ATMELhttp://www.atmel.com/images/doc0270.pdf

6264 - HYUNDAIhttp://www.electro-tech-online.com/datasheets/hy6264a_hyundai.pdf

8085 - INTELelearning.tukenya.ac.ke/mod/resource/view.php?id=262

BC 547 – Fairchild Semiconductorhttps://www.fairchildsemi.com/datasheets/ BC / BC547 .pdf

BD 139 - Fairchild Semiconductor https://www.fairchildsemi.com/datasheets/ bd /bd135.pdf

ULN2803 - TIwww.ti.com/lit/ds/symlink/ uln2803 a.pdf

UDN2981 - Allegro

http://www.soemtron.org/downloads/disposals/udn2982.pdf