ec2207 digital lab manual

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Sri Subramanya college of Engineering and TechnologyDepartment of ECE

EC2207 - DIGITAL ELECTRONICS LAB MANUAL

SYLLABUS

1. Design and implementation of Adders and Subtractors using logic

gates.

2. Design and implementation of code converters using logic gates

(i) BCD to excess- code and voice versa

(ii) Binar! to gra! and vice-versa

. Design and implementation of " bit binar! Adder# subtractor and

BCD adder using $C %"&

". Design and implementation of 2Bit 'agnitude Comparator using

logic gates & Bit 'agnitude Comparator using $C %"&

. Design and implementation of 1 bit odd#even parit! c*ec+er

#generator using $C%"1&,.

. Design and implementation of 'ultiplexer and De-multiplexer using

logic gates and stud! of $C%"1 , and $C %"1 "

%. Design and implementation of encoder and decoder using logic

gates and stud! of $C%"" and $C%"1"%

&. Construction and verification of " bit ripple counter and 'od-1, #

'od-12 ipple counters

. Design and implementation of -bit s!nc*ronous up#do/n counter

1,. $mplementation of S$S0 S$ 0 $S0 and $ 0 s*ift registers using

3lip- flops.

11. Design of experiments 1 & 1, using 4erilog 5D6.

Prepared by M.MarimuthuAssistant Professor/ ECE


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LIST OF EXPERIMENTS

1. Stud! of logic gates.

2. Design and implementation of adders and subtractors using logic

gates.

. Design and implementation of code converters using logic gates.

". Design and implementation of "-bit binar! adder#subtractor and

BCD adder using $C %"& .

. Design and implementation of 2-bit magnitude comparator

using logic gates &-bit magnitude comparator using $C %"& .

. Design and implementation of 1 -bit odd#even parit! c*ec+er#

generator using $C %"1&,.

%. Design and implementation of multiplexer and demultiplexer

using logic gates and stud! of $C %"1 , and $C %"1 ".

&. Design and implementation of encoder and decoder using logic

gates and stud! of $C %"" and $C %"1"%.

. Construction and verification of "-bit ripple counter and 'od-

1,#'od-12 ripple counter.

1,. Design and implementation of -bit s!nc*ronous up#do/n

counter.

11. $mplementation of S$S0 S$ 0 $S0 and $ 0 s*ift

registers using flip-flops.



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INDEX


EXP.

NO

DATE NAME OF THE EXPERIMENT PAGE

NO

MARKS SIGNATURE


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EX NO: 1 STUDY OF LOGIC GATESDATE:

AIM:To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

THEORY:

AND GATE:

The A D gate performs a logical multiplication commonly !no"n as A D function. The

output is high "hen both the inputs are high. The output is lo" level "hen any one of the inputs

is lo".

OR GATE:


S# o. C$MP$ E T SPEC%&%CAT%$ 'T(). A D *ATE %C +,- )

. $0 *ATE %C +,1 )1. $T *ATE %C +,-, ),. A D *ATE %/P %C +,-- )2. $0 *ATE %C +,- )3. 45$0 *ATE %C +, 3 )+. A D *ATE 1 %/P %C +,)- )

. %C T0A% E0 6%T 5 )7. PATC8 C$0D 5 ),


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The $0 gate performs a logical addition commonly !no"n as $0 function.

The output is high "hen any one of the inputs is high. The output is lo" level "hen both

the inputs are lo".

NOT GATE:

The $T gate is called an inverter. The output is high "hen the input is lo".

The output is lo" "hen the input is high.

NAND GATE:

The A D gate is a contraction of A D5 $T. The output is high "hen both

inputs are lo" and any one of the input is lo" .The output is lo" level "hen both inputs

are high.

NOR GATE:

The $0 gate is a contraction of $05 $T. The output is high "hen both inputs

are lo". The output is lo" "hen one or both inputs are high.

X-OR GATE:

The output is high "hen any one of the inputs is high. The output is lo" "hen

both the inputs are lo" and both the inputs are high.

PROCEDURE:9i: Connections are given as per circuit diagram.

9ii: #ogical inputs are given as per circuit diagram.

9iii: $bserve the output and verify the truth table .

A D *ATE;SYMBOL: PIN DIAGRAM:



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OR GATE:

$T *ATE;

SYMBOL: PIN DIAGRAM:



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3-INPUT NAND GATE :

NOR GATE:



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RESULT:

The study of logic gates "ere performed by verifying their truthtables.

EX NO: 2 DESIGN OF ADDER AND SUBTRACTOR

DATE:

AIM:To design and construct half adder< full adder< half subtractor and full

subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl. o. C$MP$ E T SPEC%&%CAT%$ 'T(.). A D *ATE %C +,- )

. 45$0 *ATE %C +, 3 )1. $T *ATE %C +,-, ),. $0 *ATE %C +,1 )1. %C T0A% E0 6%T 5 )



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,. PATC8 C$0DS 5 1

THEORY:

HALF ADDER:

A half adder has t"o inputs for the t"o bits to be added and t"o outputs one from

the sum = S> and other from the carry = c> into the higher adder position. Above circuit is

called as a carry signal from the addition of the less significant bits sum from the 45$0

*ate the carry out from the A D gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input? it

consists of three inputs and t"o outputs. A full adder is useful to add three bits at a time

but a half adder cannot do so. %n full adder sum output "ill be ta!en from 45$0 *atet correspond to the one transmitted.

The circuit that generates the parity bit in the transmitter is called a =parity

generator> and the circuit that chec!s the parity in the receiver is called a

=parity chec!er>.

%n even parity< the added parity bit "ill ma!e the total number is even

amount. %n odd parity< the added parity bit "ill ma!e the total number is odd



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amount. The parity chec!er circuit chec!s for possible errors in the

transmission. %f the information is passed in even parity< then the bits

re uired must have an even number of )>s. An error occur during

transmission< if the received bits have an odd number of )>s indicating that

one bit has changed in value during transmission.

PIN DIAGRAM FOR IC 70:

FUNCTION TABLE:INPUTS OUTPUTS

N/ )# "! H(6 Da.aI* /. ?I0 ; I7@

PE PO E J O

E EN 1 0 1 0ODD 1 0 0 1

E EN 0 1 0 1ODD 0 1 1 0

X 1 1 0 0X 0 0 1 1



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LOGIC DIAGRAM:

1 BIT ODD=E EN PARITY CHECKER

TRUTH TABLE:

I7 I I I< I3 I2 I1 I0 I7%I %I %I


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LOGIC DIAGRAM:

1 BIT ODD=E EN PARITY GENERATOR

TRUTH TABLE:

I7 I I I< I3 I2 I1 I0 I7 I I I< I3 I2 I1 I0 A+.(4) E O1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 01 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 11 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0



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PROCEDURE:

9i: Connections are given as per circuit diagram.


9iii: $bserve the output and verify the truth table.

RESULT:

The truth table of )3 bit odd/even parity generator and chec!er "as verified successfully.



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EX NO: 7

DATE:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER ANDDEMULTIPLEXER

AIM:To design and implement multiple er and demultiple er using logic

gates and study of %C +,)2- and %C +,)2,

APPARATUS REQUIRED:

Sl. o. C$MP$ E T SPEC%&%CAT%$ 'T(.). 1 %/P A D *ATE %C +,))

. $0 *ATE %C +,1 )1. $T *ATE %C +,-, )

. %C T0A% E0 6%T 5 )1. PATC8 C$0DS 5 1

THEORY:MULTIPLEXER:

Multiple er means transmitting a large number of information units

over a smaller number of channels or lines. A digital multiple er is a

combinational circuit that selects binary information from one of many input

lines and directs it to a single output line. The selection of a particular input

line is controlled by a set of selection lines. ormally there are n input line

and n selection lines "hose bit combination determine "hich input is

selected.DEMULTIPLEXER:

The function of Demultiple er is in contrast to multiple er function. %t

ta!es information from one line and distributes it to a given number of



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output lines. &or this reason< the demultiple er is also !no"n as a data

distributor. Decoder can also be used as demultiple er.

%n the ); , demultiple er circuit< the data input line goes to all of the

A D gates. The data select lines enable only one gate at a time and the data

on the data input line "ill pass through the selected gate to the associated

data output line.

BLOCK DIAGRAM FOR


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TRUTH TABLE:

S1 S0 Y $ OUTPUT0 0 D00 1 D11 0 D21 1 D3

BLOCK DIAGRAM FOR 1:< DEMULTIPLEXER:



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FUNCTION TABLE:

S1 S0 INPUT0 0 X D0 $ X S1% S0%0 1 X D1 $ X S1% S01 0 X D2 $ X S1 S0%1 1 X D3 $ X S1 S0

Y $ X S1% S0% & X S1% S0 & X S1 S0% & X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:



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TRUTH TABLE:

INPUT OUTPUTS1 S0 I=P D0 D1 D2 D30 0 0 0 0 0 0



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0 0 1 1 0 0 00 1 0 0 0 0 00 1 1 0 1 0 01 0 0 0 0 0 0

1 0 1 0 0 1 01 1 0 0 0 0 01 1 1 0 0 0 1

PIN DIAGRAM FOR IC 7


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A decoder is a multiple input multiple output logic circuit "hich

converts coded input into coded output "here input and output codes are

different. The input code generally has fe"er bits than the output code. Each

input code "ord produces a different output code "ord i.e there is one to one

mapping can be e pressed in truth table. %n the bloc! diagram of decoder

circuit the encoded information is present as n input producing n possible

outputs. n output values are from - through out n F ).



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TRUTH TABLE:

INPUT OUTPUTY1 Y2 Y3 Y< Y Y Y7 A B C1 0 0 0 0 0 0 0 0 10 1 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 1 10 0 0 1 0 0 0 1 0 00 0 0 0 1 0 0 1 0 10 0 0 0 0 1 0 1 1 00 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:



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TRUTH TABLE:

INPUT OUTPUTE A B D0 D1 D2 D31 0 0 1 1 1 10 0 0 0 1 1 10 0 1 1 0 1 1

0 1 0 1 1 0 10 1 1 1 1 1 0

PROCEDURE:



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RESULT:

The truth tables of encoder and decoder "ere verified

EX NO:

DATE:



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CONSTRUCTION AND ERIFICATION OF < BIT RIPPLECOUNTER AND MOD 10=MOD 12 RIPPLE COUNTER

AIM:

To design and verify , bit ripple counter mod )-/ mod ) ripple

counter.

APPARATUS REQUIRED:

Sl. o. C$MP$ E T SPEC%&%CAT%$ 'T(.). L6 %P $P %C +,+3

. A D *ATE %C +,-- )1. %C T0A% E0 6%T 5 ),. PATC8 C$0DS 5 1-

THEORY:

A counter is a register capable of counting number of cloc! pulse

arriving at its cloc! input. Counter represents the number of cloc! pulsesarrived. A specified se uence of states appears as counter output. This is the

main difference bet"een a register and a counter. There are t"o types of

counter< synchronous and asynchronous. %n synchronous common cloc! is

given to all flip flop and in asynchronous first flip flop is cloc!ed by e ternal

pulse and then each successive flip flop is cloc!ed by ' or ' output of

previous stage. A soon the cloc! of second stage is triggered by output of

first stage. @ecause of inherent propagation delay time all flip flops are not

activated at same time "hich results in asynchronous operation.



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LOGIC DIAGRAM FOR < BIT RIPPLE COUNTER:



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TRUTH TABLE:

CLK QA QB QC QD0 0 0 0 01 1 0 0 02 0 1 0 03 1 1 0 0

< 0 0 1 01 0 1 00 1 1 0

7 1 1 1 0> 0 0 0 1

1 0 0 110 0 1 0 1



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11 1 1 0 112 0 0 1 113 1 0 1 11< 0 1 1 1

1 1 1 1 1

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD0 0 0 0 01 1 0 0 02 0 1 0 0



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3 1 1 0 0< 0 0 1 0

1 0 1 00 1 1 0

7 1 1 1 0> 0 0 0 1

1 0 0 110 0 0 0 0

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD0 0 0 0 01 1 0 0 02 0 1 0 03 1 1 0 0< 0 0 1 0

1 0 1 00 1 1 0

7 1 1 1 0> 0 0 0 1

1 0 0 110 0 1 0 1



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11 1 1 0 112 0 0 0 0

PROCEDURE:




RESULT:

The "or!ing of , bit ripple counter< mod )- and mod ) counters "ere verified by their

truth tables.



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EX NO: 10

DATE:DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS

UP=DO'N COUNTER

AIM:To design and implement 1 bit synchronous up/do"n counter.

APPARATUS REQUIRED:

Sl. o. C$MP$ E T SPEC%&%CAT%$ 'T(.). L6 %P $P %C +,+3

. 1 %/P A D *ATE %C +,)) )1. $0 *ATE %C +,1 ),. 4$0 *ATE %C +, 3 )2. $T *ATE %C +,-, )3. %C T0A% E0 6%T 5 )+. PATC8 C$0DS 5 12

THEORY:

A counter is a register capable of counting number of cloc! pulse

arriving at its cloc! input. Counter represents the number of cloc! pulses

arrived. An up/do"n counter is one that is capable of progressing in

increasing order or decreasing order through a certain se uence. An up/do"n

counter is also called bidirectional counter. Gsually up/do"n operation of

the counter is controlled by up/do"n signal. hen this signal is high counter



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goes through up se uence and "hen up/do"n signal is lo" counter follo"s

reverse se uence.

K MAP

STATE DIAGRAM:



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TRUTH TABLE:I* /.

U =D",*P#) )*. S.a.)Q A Q B Q C

N) . S.a.)Q A&1 Q B&1 Q C&1

AA K A

BB K B

CC K C

0 0 0 0 1 1 1 1 X 1 X 1 X0 1 1 1 1 1 0 X 0 X 0 X 10 1 1 0 1 0 1 X 0 X 1 1 X0 1 0 1 1 0 0 X 0 0 X X 10 1 0 0 0 1 1 X 1 1 X 1 X0 0 1 1 0 1 0 0 X X 0 X 10 0 1 0 0 0 1 0 X X 1 1 X0 0 0 1 0 0 0 0 X 0 X X 11 0 0 0 0 0 1 0 X 0 X 1 X1 0 0 1 0 1 0 0 X 1 X X 11 0 1 0 0 1 1 0 X X 0 1 X1 0 1 1 1 0 0 1 X X 1 X 11 1 0 0 1 0 1 X 0 0 X 1 X1 1 0 1 1 1 0 X 0 1 X X 1



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1 1 1 0 1 1 1 X 0 X 0 1 X1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:9i: Connections are given as per circuit diagram.



RESULT:

The truth table of 1 bit synchronous up/do"n counter "as verified.

EX NO: 10

DATE :DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:

To design and implement9i: Serial in serial out9ii: Serial in parallel out9iii: Parallel in serial out9iv: Parallel in parallel out

APPARATUS REQUIRED:

Sl. o. C$MP$ E T SPEC%&%CAT%$ 'T(.). D %P $P %C +,+,

. $0 *ATE %C +,1 )1. %C T0A% E0 6%T 5 ),. PATC8 C$0DS 5 12



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THEORY:

A register is capable of shifting its binary information in one or both

directions is !no"n as shift register. The logical configuration of shift

register consist of a D5&lip flop cascaded "ith output of one flip flop

connected to input of ne t flip flop. All flip flops receive common cloc!

pulses "hich causes the shift in the output of the flip flop. The simplest

possible shift register is one that uses only flip flop. The output of a given

flip flop is connected to the input of ne t flip flop of the register. Each cloc!

pulse shifts the content of register one bit position to right.

PIN DIAGRAM:

LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:



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TRUTH TABLE:

CLK

S)#(a (* S)#(a "/.

1 1 0

2 0 0

3 0 0

< 1 1

X 0

X 0

7 X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:



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TRUTH TABLE:

CLK DATA

OUTPUTQ A Q B Q C Q D

1 1 1 0 0 02 0 0 1 0 03 0 0 0 1 1< 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O=P0 1 0 0 1 11 0 0 0 0 02 0 0 0 0 03 0 0 0 0 1



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The outputs of shift register types "ere verified "ith their truth tables.

EX NO: 11

DATE:DESIGN AND IMPLEMENTATION OF ADDERSJ SUBTRACTORSJ< BIT RIPPLE COUNTERJ SHIFT REGISTERS USING ERILOG

HDL LANGUAGE

AIM:

To design and implement the follo"ing using verilog 8D#8alf adder and subtractor &ull adder and subtractor , bit ripple carry counter Serial in serial outSerial in parallel outParallel in serial outParallel in parallel out

APPARATUS REQUIRED:

Sl. o. C$MP$ E T SPEC%&%CAT%$ 'T(.). PC "ith 4ilin 5 )



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soft"are

P0$*0AM &$0 8A#& ADDE0 GS% * E0%#$*;module halfNadder9a< b< sum< carry:?

input a?input b?output sum?output carry?

or g)9sum


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$GTPGT;

P0$*0AM &$0 8A#& SG@T0ACT$0 GS% * E0%#$*;module halfNsub9a


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or g)9e


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P0$*0AM &$0 , @%T 0%PP#E C$G TE0 GS% * E0%#$*;module co9


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input din?"ire din? input cl!?"ire cl!? input reset?"ire reset?output dout? reg dout?reg O,;- s?al"ays Q 9posedge 9cl!:: beginif 9reset:dout I -?else beginsO- I din ?sO) I sO- ?sO I sO) ?dout I sO ?

endendendmodule



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P0$*0AM &$0 S%P$ S8%&T 0E*%STE0

module hghg9din< cl!< reset< dout:?input din? "ire din? input cl!? "ire cl!? input reset? "ire reset? output O1;- dout?"ire O1;- dout?reg O1;- s?al"ays Q 9posedge 9cl!:: beginif 9reset:s I -?else beginsO1 I din?sO I sO1 ?sO) I sO ?sO- I sO) ?endendassign dout s?endmodule



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P0$*0AM &$0 P%S$ S8%&T 0E*%STE0

module parallelNinNserialNout 9 din


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endendendmodule

P0$*0AM &$0 P%P$ S8%&T 0E*%STE0 module P%P$ 9 din


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