ec303_lab2_studentcopy

8/3/2019 EC303_Lab2_studentcopy

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POLITEKNIK TUANKU SYED SIRAJUDDIN

JABATAN KEJURUTERAAN ELEKTRIK

COURSE CODE : EC303 COURSE : Computer Architecture

Organization

LAB : Lab Exercise DATE :

TITLE :COMBINATIONAL AND SEQUENCIAL LOGIC

Objective : Upon completion of this experiment, students should be able to:Differentiate between combinational and sequential logic circuits.

Know the characteristics of an SR bistable anda clocked SR bistable and simulate th

timing diagram

Know the JK and D bistable circuit and simulate the timing diagram

Equipment/Software : QUARTUS II 8.1 WEB EDITION

THEORY:

Combinational logic circuits are circuits having inputs and outputs where the outpu

states are fixed by the particular input states. For a particular input state, the output

will always be the same logic values.

Sequential logic circuits have inputs and outputs as for combinational circuits but th

output states are not entirely dependent on the current input states but depend o

the previous input states, i.e. there is an element of memory in the circuit thremembers previous states and this affects the output settings for a particular inpu

state.

THE SR ( SET-RESET ) BISTABLE

The SR bistable is a circuit having two inputs labeled S and R and the two output

labeled Q and Q. The two outputs should be of opposite logic states at any time, i.eif one is at logic 1, the other is at logic 0.

Table 1.1 is the corresponding truth table for an SR bistable with the inputs active

the high logic state.

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INPUTS OUTPUTSSTATUS

S R Q Q

0 0 0 1 HOLD

0 1 0 1 RESET

1 0 1 0 SET

1 1 0 0 INVALID

Table 1.1

THE CLOCKED SR BISTABLE CIRCUIT

Figure 1.1 shows the block diagram for a clocked SR bistable and waveforms for

circuit having inputs active high, the clock signal being level sensitive.

With this circuit the output state does not change immediately the SR inputs are se

but occurs at the receipt of an input to the clock input and this enables changes to b

synchronized with changes at other gates. The circuit may operate with the cloc

input level sensitive or it may be edge sensitive to either a rising or falling edge.

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Figure 1.1: SR BIstable Circuit

THE JK BISTABLE CIRCUIT

The 74LS112 or 74LS76 device provided is clocked on the falling, negative goin

edge of the clock pulse as indicated by the circle on the clock input connection of th

diagram as shown in Figure 1.2 and active low preset and clear inputs a

provided.

Figure 1.2

INPUTS OUTPUTS OUTPUT

STATEJ K Q Q

0 0 0 0 HOLD

0 1 0 1 RESET

1 0 1 0 SET

1 1 0 0 TOGGLE

Table 1.2

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THE D-TYPE (DATA) BISTABLE

Figure 1.3 shows the block diagram of the 0-type bistable 74LS74. This has one dat

input, two outputs, as for the SR bistable, a clock input and separate preset and clea

input facilities to allow the output state to be preset initially in the desired state.

Figure 1.3

The preset and clear facilities are active in the low state, as indicated by the circle o

their input connections and these inputs must be held at logic level 1 normally an

pulled down to 0 momentarily to activate the particular facility required.

With this circuit, data presented at the data input connection D is fed through to th

output Q when an active clock input is received, the data can then be changed an

the revised data will be fed through at the next active clock input. The 74LS74 devicis edge triggered, the active clock input being rising, or positive, edge.

D-type bistable can also be constructed using JK flip flop by connecting an inverte

between the J and K input. If the input of D is high (logic 1), the input J is also hig

and input for K is low, the output will be high (SET). When the input of D is low (log

0), the input to J is low and K is high, the output will be low (RESET). Refer to th

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truth table in Truth table 1.3

INPUT OUTPUT AFTER CLK

0 0

1 1

Table 1.3

PROCEDURE :

Experiment 1: SR BISTABLE CIRCUIT

1. Construct the circuits as shown as Figure 1.1 and compile the circuit withoany error

2. Simulate the timing diagram and set the input sequence such as the Table 1.4

INPUTS

OUTPUTSOUTPU

T

STATE

BEFORE CLOCK

PULSE

AFTER CLOCK

PULSES R CLK Q Q Q Q

0 0 1

0 1 1

1 0 1

1 1 1

0 0 1

0 1 1

1 0 1

1 1 1

Table 1.4

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Experiment 2: JK BISTABLE CIRCUIT

1. Construct the circuits as shown as Figure 1.1 and compile the circuit withoany error

2. Simulate the timing diagram and set the input sequence such as the Table 1.4

INPUTS

OUTPUTS OUTPU

T

STATEBEFORE CLK

PULSE

AFTER CLK

PULSE

J K QN QN QN+1 QN+1

0 0 0 10 1 0 1

1 0 0 1

1 1 0 1

0 0 1 0

0 1 1 0

1 0 1 0

1 1 1 0

Table 1.5

Experiment 3: D TYPE BISTABLE CIRCUIT

1. Construct the circuit as shown at Figure 1.3.2. Compile the circuit and simulate the timing diagram based the input from tab

1.6.

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INPUTS OUTPUTS

D CLK Q Q

0 0

0 1

1 0

1 1

1 0

0 0

0 1

Table 1.6

Questions:

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