ec6302 digital electronics 2 marks with answers

5/22/2018 EC6302 Digital Electronics 2 Marks With Answers

1/18

EC6302 DIGITAL ELECTRONICS

2 Marks with AnswersUnit 1

1 De!ine "inar# $%&i'(

Binary logic consists of binary variables and logical operations. The variables aredesignated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only twodistinct values: 1 and . There are three basic logic operations: A!", #$, and !#T.

2 )hat are the "asi' *i&ita$ $%&i' &ates(The three basic logic gates are

A!" gate#$ gate!#T gate

3 )hat is a L%&i' &ate(

%ogic gates are the basic ele&ents that &a'e up a digital syste&. The electronic gate is acircuit that is able to operate on a nu&ber of binary inputs in order to perfor& aparticular logical function.

+ Gi,e the '$assi!i'ati%n %! $%&i' !a-i$ies

Bipolar (nipolar

)aturated !on )aturated *+#)

!+#)

C+#)

$T% )chott'y TT%

C% "T%

- - %

TT%

. )hi'h &ates are 'a$$e* as the /ni,ersa$ &ates( )hat are its a*,anta&es(

The !A!" and !#$ gates are called as the universal gates. These gates are used toperfor& any type of logic application.

6 C$assi!# the $%&i' !a-i$# "# %erati%n(

The Bipolar logic fa&ily is classified into)aturated logic(nsaturated logic.

The $T%, "T%, TT%, -%, /T% logic co&es under the saturated logic fa&ily.The )chott'y TT%, and C% logic co&es under the unsaturated logic fa&ily.

State the '$assi!i'ati%ns %! ET *e,i'es ET is '$assi!ie* as1. 0unction ield ffect Transistor 20T3. +etal oxide se&iconductor fa&ily 2+#)3.

Menti%n the '$assi!i'ati%n %! sat/rate* "i%$ar $%&i' !a-i$ies.The bipolar logic fa&ily is classified as follows:

$T%4 $esistor Transistor %ogic"T%4 "iode Transistor logic -%4-ntegrated -n5ection %ogic TT%4


2/18

Transistor Transistor %ogic C%4&itter Coupled %ogic

4 Menti%n the i-%rtant 'hara'teristi's %! *i&ita$ IC5s(an out

*ower dissipation*ropagation "elay!oise +arginan -n

#perating te&perature

*ower supply re6uire&ents

10 De!ine an%/t(

an out specifies the nu&ber of standard loads that the output of the gate can drive without i&pair&ent of its nor&al operation.

11 De!ine %wer *issiati%n(

*ower dissipation is &easure of power consu&ed by the gate when fully driven by all itsinputs.

12 )hat is r%a&ati%n *e$a#(

*ropagation delay is the average transition delay ti&e for the signal to propagate fro&

input to output when the signals change in value. -t is expressed in ns.

13 De!ine n%ise -ar&in(

-t is the &axi&u& noise voltage added to an input signal of a digital circuit that does notcause an undesirable change in the circuit output. -t is expressed in volts.

1+ De!ine !an in(

an in is the nu&ber of inputs connected to the gate without any degradation in thevoltage level.

1. )hat is Oeratin& te-erat/re(

All the gates or se&iconductor devices are te&perature sensitive in nature. Thete&perature in which the perfor&ance of the -C is effective is called as operating te&perature.

#perating te&perature of the -C vary fro&

C to 7

c.

16)hat is 7i&h Thresh%$* L%&i'(

)o&e digital circuits operate in environ&ents, which produce very high noise signals.or operation in such surroundings there is available a type of "T% gate which possesses a highthreshold to noise i&&unity. This type of gate is called /T% logic or /igh Threshold %ogic.

1 )hat are the t#es %! TTL $%&i'(

1. #pen collector output. Tote&4*ole #utput8. Tri4state output.

1 )hat is *e$eti%n -%*e %erati%n MOS(-f the channel is initially doped lightly with p4type i&purity a conducting channel exists

at zero gate voltage and the device is said to operate in depletion &ode.

14 )hat is enhan'e-ent -%*e %erati%n %! MOS(

-f the region beneath the gate is left initially uncharged the gate field &ust induce achannel before current can flow. Thus the gate voltage enhances the channel current and such adevice is said to operate in the enhance&ent &ode.


3/18

20 Menti%n the 'hara'teristi's %! MOS transist%r(

1. The n4 channel +#) conducts when its gate4 to4 source voltage is positive.. The p4 channel +#) conducts when its gate4 to4 source voltage is negative8. ither type of device is turned of if its gate4 to4 source voltage is zero.

21 7%w s'h%ttk# transist%rs are !%r-e* an* state its /se(

A schott'y diode is for&ed by the co&bination of &etal and se&iconductor. Thepresence of schott'y diode between the base and the collector prevents the transistor fro& goinginto saturation. The resulting transistor is called as schott'y transistor.

The use of schott'y transistor in TT% decreases the propagation delay without a sacrifice

of power dissipation.

22 List the *i!!erent ,ersi%ns %! TTL

1.TT% 2)td.TT%3 .%TT% 2%ow *ower TT%38./TT% 2/igh )peed TT%3 9.)TT% 2)chott'y TT%3

.%)TT% 2%ow power )chott'y TT%3

23 )h# t%te- %$e %/t/ts 'ann%t "e '%nne'te* t%&ether

Tote& pole outputs cannot be connected together because such a connection&ight produce excessive current and &ay result in da&age to the devices.

2+ State a*,anta&es an* *isa*,anta&es %! TTL

Adv: asily co&patible with other -Cs%ow output i&pedance

"isadv:

;ired output capability is possible only with tristate and open collector type)pecial circuits in Circuit layout and syste& design are re6uired.

2. )hen *%es the n%ise -ar&in a$$%w *i&ita$ 'ir'/its t% !/n'ti%n r%er$#

;hen noise voltages are within the li&its of


4/18

Unit II

1 De!ine '%-"inati%na$ $%&i'

;hen logic gates are connected together to produce a specified output for certain

specified co&binations of input variables, with no storage involved, the resulting circuit iscalled co&binational logic.

2 E8$ain the *esi&n r%'e*/re !%r '%-"inati%na$ 'ir'/itsThe proble& definition

"eter&ine the nu&ber of available input variables > re6uired #?* variables.Assigning letter sy&bols to -?# variables

#btain si&plified Boolean expression for each #?*.#btain the logic diagra&.

3 De!ine 7a$! a**er an* !/$$ a**er

The logic circuit that perfor&s the addition of two bits is a half adder. The circuit thatperfor&s the addition of three bits is a full adder.

+ De!ine De'%*er(

A decoder is a &ultiple 4 input &ultiple output logic circuit that converts codedinputs into coded outputs where the input and output codes are different.

. )hat is "inar# *e'%*er(

A decoder is a co&binational circuit that converts binary infor&ation fro& n input linesto a &axi&u& of nout puts lines.

6 De!ine En'%*er(

An encoder has ninput lines and n output lines. -n encoder the output lines generate thebinary code corresponding to the input value.

)hat is ri%rit# En'%*er(A priority encoder is an encoder circuit that includes the priority function. -n priority

encoder, if or &ore inputs are e6ual to 1 at the sa&e ti&e, the input having the highest prioritywill ta'e precedence.

De!ine -/$ti$e8er(

+ultiplexer is a digital switch. -f allows digital infor&ation fro& several sources to berouted onto a single output line.

4 )hat *% #%/ -ean "# '%-arat%r

A co&parator is a special co&binational circuit designed pri&arily to co&pare therelative &agnitude of two binary nu&bers.

Unit III


5/18

1 List "asi' t#es %! r%&ra--a"$e $%&i' *e,i'es

. $ead only &e&ory

. *rogra&&able logic Array

. *rogra&&able Array %ogic

2 E8$ain ROM

A read only &e&ory2$#+3 is a device that includes both the decoder and the #$ gateswithin a single -C pac'age. -t consists of n input lines and & output lines. ach bit co&binationof the input variables is called an address. ach bit co&bination that co&es out of the output

lines is called a word. The nu&ber of distinct addresses possible with n input variables is

n

.

3 De!ine a**ress an* w%r*9

-n a $#+, each bit co&bination of the input variable is called on address. ach bitco&bination that co&es out of the output lines is called a word.

+ State the t#es %! ROM

. +as'ed $#+.

. *rogra&&able $ead only +e&ory

. rasable *rogra&&able $ead only &e&ory.

. lectrically rasable *rogra&&able $ead only +e&ory.

. )hat is r%&ra--a"$e $%&i' arra#( 7%w it *i!!ers !r%- ROM(

-n so&e cases the nu&ber of don@t care conditions is excessive, it is &ore econo&ical touse a second type of %)- co&ponent called a *%A. A *%A is si&ilar to a $#+ in concepthowever it does not provide full decoding of the variables and does not generates all the&inter&s as in the $#+.

. )hi'h &ate is e:/a$ t% ANDin,ert Gate(!A!" gate.

7. )hi'h &ate is e:/a$ t% ORin,ert Gate(!#$ gate.

;/""$e* OR &ate is e:/a$ t%!A!" gate

4 ;/""$e* AND &ate is e:/a$ t%

!#$ gate

10 E8$ain


6/18

*$#+ also use +#) circuitry. "ata is stored as charge or no charge on aninsulated layer or an insulated floating gate in the device. *$#+ allowsselective erasing at the register level rather than erasing all the infor&ation sincethe infor&ation can be changed by using electrical signals.

13 )hat is RAM(

$ando& Access +e&ory. $ead and write operations can be carried out.

1+ )hat is r%&ra--a"$e $%&i' arra#( 7%w it *i!!ers !r%- ROM(

-n so&e cases the nu&ber of don@t care conditions is excessive, it is &ore econo&ical to

use a second type of %)- co&ponent called a *%A. A *%A is si&ilar to a $#+ in concepthowever it does not provide full decoding of the variables and does not generates all the&inter&s as in the $#+.

1. )hat is -ask r%&ra--a"$e(

;ith a &as' progra&&able *%A, the user &ust sub&it a *%A progra& table to the&anufacturer.

16 )hat is !ie$* r%&ra--a"$e $%&i' arra#(

The second type of *%A is called a field progra&&able logic array. The user by &eansof certain reco&&ended procedures can progra& the *%A.

17.List the -a=%r *i!!eren'es "etween


7/18

2. )hat *%es

1 )hat are the '$assi!i'ati%n %! se:/entia$ 'ir'/its(

The se6uential circuits are classified on the basis of ti&ing of their signals into twotypes. They are,


8/18

13)ynchronous se6uential circuit.3Asynchronous se6uential circuit.

2 De!ine $i !$%

The basic unit for storage is flip flop. A flip4flop &aintains its output state either at 1 or until directed by an input signal to change its state.

3)hat are the *i!!erent t#es %! !$i!$%(

There are various types of flip flops. )o&e of the& are &entioned below they are,$) flip4flop

)$ flip4flop" flip4flop0= flip4flopT flip4flop

+)hat is the %erati%n %! D !$i!$%(

-n " flip4flop during the occurrence of cloc' pulse if "F1, the output G is set and if"F, the output is reset.

. )hat is the %erati%n %! ?@ !$i!$%(

;hen = input is low and 0 input is high the G output of flip4flop isset. ;hen = input is high and 0 input is low the G output of flip4flop isreset. ;hen both the inputs = and 0 are low the output does not change ;hen both the inputs = and 0 are high it is possible to set or reset theflip4flop 2ie3 the output toggle on the next positive cloc' edge.

6 )hat is the %erati%n %! T !$i!$%(

T flip4flop is also 'nown as Toggle flip4flop. ;hen TF there is no change in the output.

;hen TF1 the output switch to the co&ple&ent state 2ie3 the outputtoggles.

De!ine ra'e ar%/n* '%n*iti%n

-n 0= flip4flop output is fed bac' to the input. Therefore change in the output resultschange in the input. "ue to this in the positive half of the cloc' pulse if both 0 and = are high

then output toggles continuously. This condition is called Hrace around condition@.

)hat is e*&etri&&ere* !$i!$%(

The proble& of race around condition can solved by edge triggering flip flop. The ter&edge triggering &eans that the flip4flop changes state either at the positive edge or negative edgeof the cloc' pulse and it is sensitive to its inputs only at this transition of the cloc'.

4 )hat is a -asters$a,e !$i!$%(

A &aster4slave flip4flop consists of two flip4flops where one circuit serves as a &asterand the other as a slave.

10 De!ine rise ti-e

The ti&e re6uired to change the voltage level fro& 1I to JI is 'nown as riseti&e2tr3.


9/18

11De!ine !a$$ ti-e

The ti&e re6uired to change the voltage level fro& JI to 1I is 'nown as fall ti&e2tf3.

12De!ine skew an* '$%'k skew

The phase shift between the rectangular cloc' wavefor&s is referred to as s'ew and theti&e delay between the two cloc' pulses is called cloc' s'ew.

13De!ine set/ ti-e

The setup ti&e is the &ini&u& ti&e re6uired to &aintain a constant voltage levels at theexcitation inputs of the flip4flop device prior to the triggering edge of the cloc' pulse in order forthe levels to be reliably cloc'ed into the flip flop. -t is denoted as t setup.

1+ De!ine h%$* ti-e

The hold ti&e is the &ini&u& ti&e for which the voltage levels at the excitation inputs&ust re&ain constant after the triggering edge of the cloc' pulse in order for the levels to bereliably cloc'ed into the flip flop. -t is denoted as thold.

1.)hat is !/n*a-enta$ -%*e

A transition fro& one stable state to another occurs only in response to a change in theinput state. After a change in one input has occurred, no other change in any input occurs untilthe circuit enters a stable state. )uch a &ode of operation is referred to as a funda&ental &ode.

16 )rite sh%rt n%te %n share* r%w state assi&n-ent

$aces can be avoided by &a'ing a proper binary assign&ent to the state variables. /ere,the state variables are assigned with binary nu&bers in such a way that only one state variablecan change at any one state variable can change at any one ti&e when a state transition occurs. Toacco&plish this, it is necessary that states between which transitions occur be given ad5acentassign&ents. Two binary are said to be ad5acent if they differ in only one variable.

1 )rite sh%rt n%te %n %ne h%t state assi&n-ent

The one hot state assign&ent is another &ethod for finding a race free state assign&ent.-n this &ethod, only one variable is active or hot for each row in the original flow table, ie, itre6uires one state variable for each row of the flow table. Additional row are introduced toprovide single variable changes between internal state transitions.

1 De!ine r%a&ati%n *e$a#

A propagation delay is the ti&e re6uired to change the output after the application of theinput.

14 De!ine re&isters

A register is a group of flip4flops flip4flop can store one bit infor&ation. )o an n4bit register has agroup of n flip4flops and is capable of storing any binary infor&ation?nu&ber containing n4bits.

20 De!ine shi!t re&isters

The binary infor&ation in a register can be &oved fro& stage to stage within the registeror into or out of the register upon application of cloc' pulses. This type of bit &ove&ent or

shifting is essential for certain arith&etic and logic operations used in &icroprocessors. Thisgives rise to group of registers called shift registers.

21)hat are the *i!!erent t#es %! shi!t t#e(There are five types. They are,

)erial -n )erial #ut )hift $egister)erial -n *arallel #ut )hift $egister*arallel -n )erial #ut )hift $egister

*arallel -n *arallel #ut )hift $egister


10/18

Bidirectional )hift $egister

22.E8$ain the !$i!$% e8'itati%n ta"$es !%r RS.$) flip4flop

-n $) flip4flop there are four possible transitions fro& the present state to the nextstate. They are,

transition: This can happen either when $F)F or when $F1 and )F.

1 transition: This can happen only when )F1 and $F. 1 transition: This can happen only when )F and $F1.

1 1 transition: This can happen either when )F1 and $F or )F and$F.

23 De!ine se:/entia$ 'ir'/it(

-n se6uential circuits the output variables dependent not only on the present inputvariables but they also depend up on the past history of these input variables.

2+ Gi,e the '%-aris%n "etween '%-"inati%na$ 'ir'/its an* se:/entia$ 'ir'/its

Co&binational circuits )e6uential circuits

+e&ory unit is not re6uired +e&ory unity is re6uired

*arallel adder is a co&binational circuit )erial adder is a se6uential circuit

2. )hat *% #%/ -ean "# resent state(

The infor&ation stored in the &e&ory ele&ents at any given ti&e define.s the presentstate of the se6uential circuit.

26 )hat *% #%/ -ean "# ne8t state(

The present state and the external inputs deter&ine the outputs and the next state ofthe se6uential circuit.

2 State the t#es %! se:/entia$ 'ir'/its(

a. )ynchronous se6uential circuitsb. Asynchronous se6uential circuits

2 De!ine s#n'hr%n%/s se:/entia$ 'ir'/it

-n synchronous se6uential circuits, signals can affect the &e&ory ele&ents only atdiscrete instant of ti&e.


11/18

Unit >

1 De!ine As#n'hr%n%/s se:/entia$ 'ir'/it(

-n asynchronous se6uential circuits change in input signals can affect &e&ory ele&entat any instant of ti&e.

2Gi,e the '%-aris%n "etween s#n'hr%n%/s As#n'hr%n%/s se:/entia$ 'ir'/its(

)ynchronous se6uential circuits Asynchronous se6uential circuits.

+e&ory ele&ents are cloc'ed flip4flops +e&ory ele&ents are either unloc'ed flip 4flops or ti&e delay ele&ents.

asier to design +ore difficult to design

3 The !%$$%win& wa,e !%r-s are a$ie* t% the in/ts %! SR $at'h Deter-ine the Bwa,e!%r- Ass/-e initia$$# B 1

/ere the latch input has to be pulsed &o&entarily to cause a change in the latch output state,and the output will re&ain in that new state even after the input pulse is over.

+ )hat is ra'e ar%/n* '%n*iti%n(

-n the 0= latch, the output is feedbac' to the input, and therefore changes in the outputresults change in the input. "ue to this in the positive half of the cloc' pulse if 0 and = areboth high then output toggles continuously. This condition is 'nown as race around condition.

.Gi,e the '%-aris%n "etween s#n'hr%n%/s As#n'hr%n%/s '%/nters

Asynchronous counters )ynchronous counters

-n this type of counter flip4flops are -n this type there is no connection betweenconnected in such a way that output of 1st output of first flip4flop and cloc' input of

flip4flop drives the cloc' for the next flip4 the next flip 4 flop

flop.

All the flip4flops are !ot cloc'ed All the flip4flops are cloc'ed

si&ultaneously si&ultaneously

6 The t * !%r ea'h !$i!$% is .0 ns Deter-ine the -a8i-/- %eratin& !re:/en'# !%rMOD 32 ri$e '%/nter

f &ax 2ripple3 F x ns F 9 +/K

)hat are se'%n*ar# ,aria"$es(

4present state variables in asynchronous se6uential circuits

)hat are e8'itati%n ,aria"$es(

4next state variables in asynchronous se6uential circuits

4 )hat is !/n*a-enta$ -%*e se:/entia$ 'ir'/it(input variables changes if the circuit isstable

4inputs are levels, not pulses


12/18

4only one input can change at a given ti&e

10 )hat are /$se -%*e 'ir'/it(4inputs are pulses4width of pulses are long for circuit to respond to the input4pulse width &ust not be so long that it is still present after the new state is reached

11 )hat are the si&ni!i'an'e %! state assi&n-ent(

-n synchronous circuits4state assign&ents are &ade with the ob5ective of circuitreduction

Asynchronous circuits4its ob5ective is to avoid critical races

12 )hen *% ra'e '%n*iti%n %''/r(

4two or &ore binary state variables change their value in response to the change in i?pvariable

13)hat is n%n 'riti'a$ ra'e(

4final stable state does not depend on the order in which the state variable changes4race condition is not har&ful

1+)hat is 'riti'a$ ra'e(

4final stable state depends on the order in which the state variable changes4race condition is har&ful

1. )hen *%es a '#'$e %''/r(

4asynchronous circuit &a'es a transition through a series of unstable state

16)hat are the *i!!erent te'hni:/es /se* in state assi&n-ent(

4shared row state assign&ent4one hot state assign&ent

1)hat are the stes !%r the *esi&n %! as#n'hr%n%/s se:/entia$ 'ir'/it(construction of pri&itive flow table

4reduction of flow table4state assign&ent is &ade

4realization of pri&itive flow table

1)hat is haar*(

4unwanted switching transients

14)hat is stati' 1 haar*(

4output goes &o&entarily when it should re&ain at 1

20)hat is stati' 0 haar*(

4output goes &o&entarily 1 when it should re&ain at

21 )hat is *#na-i' haar*(

4output changes 8 or &ore ti&es when it changes fro& 1 to or to 1

22)hat is the 'a/se !%r essentia$ haar*s(4une6ual delays along or &ore path fro& sa&e input

23)hat is !$%w ta"$e(4state table of an synchronous se6uential networ'


13/18

2+ )hat is ri-iti,e !$%w 'hart( %nestable state per row

2.)hat is '%-"inati%na$ 'ir'/it(

#utput depends on the given input. -t has no storage ele&ent.

26De!ine -er&er &rah

The &erger graph is defined as follows. -t contains the sa&e nu&ber of vertices as thestate table contains states. A line drawn between the two state vertices indicates each co&patiblestate pair. -t two states are inco&patible no connecting line is drawn.

2De!ine '$%se* '%,erin&

A )et of co&patibles is said to be closed if, for every co&patible contained in the set, allits i&plied co&patibles are also contained in the set. A closed set of co&patibles, whichcontains all the states of +, is called a closed covering.

2De!ine state ta"$e

or the design of se6uential counters we have to relate present states and next states.The table, which represents the relationship between present states and next states, is calledstate table.

24 De!ine t%ta$ state

The co&bination of level signals that appear at the inputs and the outputs of the delaysdefine what is called the total state of the circuit.

30)hat are the stes !%r the *esi&n %! as#n'hr%n%/s se:/entia$ 'ir'/it(

1. Construction of a pri&itive flow table fro& the proble& state&ent.

. *ri&itive flow table is reduced by eli&inating redundant states using the statereduction

8. )tate assign&ent is &ade9. The pri&itive flow table is realized using appropriate logic ele&ents.

31 De!ine ri-iti,e !$%w ta"$e 9

-t is defined as a flow table which has exactly one stable state for each row in the table.The design process begins with the construction of pri&itive flow table.

8.)hat are the t#es %! as#n'hr%n%/s 'ir'/its (

1. unda&ental &ode circuits. *ulse &ode circuits

33 Gi,e the '%-aris%n "etween state Assi&n-ent S#n'hr%n%/s 'ir'/it an* stateassi&n-ent as#n'hr%n%/s 'ir'/it

-n synchronous circuit, the state assign&ents are &ade with the ob5ective of circuitreduction. -n asynchronous circuits, the ob5ective of state assign&ent is to avoid critical races.

3+ )hat are ra'es(

;hen or &ore binary state variables change their value in response to a change in aninput variable, race condition occurs in an asynchronous se6uential circuit. -n case of une6ualdelays, a race condition &ay cause the state variables to change in an unpredictable &anner.

3. De!ine n%n 'riti'a$ ra'e

-f the final stable state that the circuit reaches does not depend on the order in which thestate variable changes, the race condition is not har&ful and it is called a non critical race.

36 De!ine 'riti'a$ ra'e(


14/18

-f the final stable state depends on the order in which the state variable changes, the racecondition is har&ful and it is called a critical race.

3 )hat is a '#'$e(

A cycle occurs when an asynchronous circuit &a'es a transition through a series ofunstable states. -f a cycle does not contain a stable state, the circuit will go fro& one unstable tostable to another, until the inputs are changed.

3 )rite a sh%rt n%te %n !/n*a-enta$ -%*e as#n'hr%n%/s 'ir'/it

unda&ental &ode circuit assu&es that. The input variables change only when thecircuit is stable. #nly one input variable can change at a given ti&e and inputs are levels and notpulses.

34 )rite a sh%rt n%te %n /$se -%*e 'ir'/it

*ulse &ode circuit assu&es that the input variables are pulses instead of level. Thewidth of the pulses is long enough for the circuit to respond to the input and the pulse width&ust not be so long that it is still present after the new state is reached.

+0 De!ine se'%n*ar# ,aria"$es

The delay ele&ents provide a short ter& &e&ory for the se6uential circuit. The presentstate and next state variables in asynchronous se6uential circuits are called secondary variables.

+1 De!ine !$%w ta"$e in as#n'hr%n%/s se:/entia$ 'ir'/it-n asynchronous se6uential circuit state table is 'nown as flow table because of the

behaviour of the asynchronous se6uential circuit. The stage changes occur in independent of acloc', based on the logic propagation delay, and cause the states to .flow. fro& one to another.

+2 A /$se -%*e as#n'hr%n%/s -a'hine has tw% in/ts I! r%*/'es an %/t/t whene,ertw% '%nse'/ti,e /$ses %''/r %n %ne in/t $ine %n$# The %/t/t re-ains at 1 /nti$ a /$sehas %''/rre* %n the %ther in/t $ine )rite *%wn the state ta"$e !%r the -a'hine


15/18

+3 )hat is !/n*a-enta$ -%*e

A transition fro& one stable state to another occurs only in response to a change inthe input state. After a change in one input has occurred, no other change in any inputoccurs until the circuit enters a stable state. )uch a &ode of operation is referred to as afunda&ental &ode.

++ )rite sh%rt n%te %n share* r%w state assi&n-ent

$aces can be avoided by &a'ing a proper binary assign&ent to the state variables.

/ere, the state variables are assigned with binary nu&bers in such a way that only one statevariable can change at any one state variable can change at any one ti&e when a statetransition occurs. To acco&plish this, it is necessary that states between which transitionsoccur be given ad5acent assign&ents. Two binary are said to be ad5acent if they differ inonly one variable.

+. )rite sh%rt n%te %n %ne h%t state assi&n-ent

The one hot state assign&ent is another &ethod for finding a race free stateassign&ent. -n this &ethod, only one variable is active or hot for each row in the originalflow table, ie, it re6uires one state variable for each row of the flow table. Additional roware introduced to provide single variable changes between internal state transitions.


16/18

Theory;or'ing principleAdvantages

.xplain with necessary diagra&s +#) > C+#). *+#)!+#)

C+#) "iagra&s

UnitII

7."esign a 94bit binary adder?subtractor circuit. Basic e6uations

Co&parison of e6uations "esign using twosco&ple&ent Circuit diagra&

E."esign and explain a co&parator to co&pare two identical words. Two nu&bersrepresented by A F A8AA1A > B F B8BB1B -f two nu&bers e6ual * F Ai Bi

#btain the logic xpression . #btain the logicdiagra&.

J.xplain in detail the loo' ahead carry generator. Bloc' diagra&

xplanation %ogic diagra&

UnitIII

1. "esign a logic circuit to convert the BC" code to xcess L 8 code. Truth Table forBC" to xcess L 8 conversion.=4&ap si&plification

%ogic circuit i&ple&enting the Boolean xpression 11.xplain indetail about *%A and *A%.

%ogic difference between *ro& > *%A %ogic diagra&i&ple&enting a function %ogic difference between *ro&> *A% %ogic diagra& i&ple&enting a function

1. -&ple&ent 2A,B,C,"3F 21,8,9,11,1,18,19,13 using &ultiplexer.

-&ple&entation

Table

explanation

18. -&ple&ent ;2A,B,C,"3 F 2,1,183

M2A,B,C,"3 F 27,E,J,1,11,1,18,19,13

N2A,B,C,"3 F 2,,8,9,,,7,E,1,11,13

K 2A,B,C,"3 F 21,,E,1,183 using *A%213

Table

*A% i&ple&entation

UnitI>

19.xplain the wor'ing of BC" $ipple Counter with the help of state diagra& and logic


17/18

diagra&.

BC" $ipple Counter Count se6uenceTruth Table

)tate diagra& representing the Truth TableTruth Table for the 04= lip lop%ogic "iagra&

1."esign a se6uential detector which produces an output 1 every ti&e the input se6uence111 is detected.

Construct state diagra&

#btain the flow table#btain the flow table > output tableTransition table

)elect flip flopxcitation table%ogic diagra&

1. xplain in detail about serial in serial out shift register.Bloc' diagra&

Theoretical explanation%ogic diagra& ;or'ing

Unit>

17.xplain with neat diagra& the different hazards and the way to eli&inate the&.

Classification of hazards)tatic hazard > "yna&ic hazard definitions= &ap for selected functions+ethod of eli&inationssential hazards

1E.)tate with a neat exa&ple the &ethod for the &ini&ization of pri&itive flow table.Consider a state diagrabtain the flow table

(sing i&plication table reduce the flow table (sing&erger graph obtain &axi&al co&patibles covered conditions*lot the reduced flow table

1J."esign a asynchronous se6uential circuit with inputs T and C. The output attains a value of 1when T F 1 > c &oves fro& 1 to . #therwise the output is .

#btain the state diagrabtain the flow table

(sing i&plication table reduce the flow table (sing&erger graph obtain &axi&al co&patibles covered conditions*lot the reduced flow table#btain transition table xcitationtable%ogic diagra&

. xplain in detail about $aces. Basicsof races

*roble& created due to racesClassification of races $e&edy forraces


18/18

cycles

1. xplain the different &ethods of state assign&ent Threerow state assign&ent

)hared row state assign&ent ourrow flow table

+ultiple row state assign&ent*revention of races.

ec6302 digital electronics 2 marks with answers

Documents