1

UNIVERSITY PART-B ANSWERS

UNIT-1

1. Discuss about the DC load line and Q point. (OR) What is D.C. load line, how will

you select the operating point, explain it using common emitter amplifier

characteristics as an example?[NOV/DEC-06,09,11,12][MAY/JUN-12,13]

DC load line:-

It is the line on the output characteristics of a transistor circuit which gives

the values of IC and VCE corresponding to zero signal (or) DC conditions.

The transistor is biased with a common supply such that the base emitter

junction is forward biased and the collector base junction is reversed biased, i.e.

Transistor is in the active region.

In the absence of ac signal, the capacitors provide very high impedance, i.e. open

circuit. Therefore, the equivalent circuit for common emitter amplifier because, as shown

fig.

Applying Kirchhoffs voltage law to the collector circuit shown in fig.

We get,

VCC-IC (RC+RE) VCE = 0

VCC = IC (RC+RE) + VCE ---------- 1

Where IC (RC+RE) is the voltage drop across RC and RE ,

and VCE is the collector emitter voltage. If we arrange the

2

terms in equation 1 as

EC

CCCE

EC

CRR

VV

RRI

1

dc

CCCE

dc R

VV

R

1 ECdc RRR ---------- 2

And compare this equation with equation of straight line y = mx +c, where m is the

slope of the line and c is the intercept on y axis, then we can draw a straight line on the graph

of IC Vs VCE which is having slope (-1/Rdc) & y intercept VCC/Rdc. To determine the two points

on the line we assume VCE = VCC & VCE = 0.

1. When VCE = VCC; IC = 0 and we get a point of cut-off 2. When VCE = 0; IC = VCC/Rdc & we get a point saturation region

Q

point:

The term biasing appearing for the application of dc voltages to establish a fixed level of

current and voltage. For transistor amplifiers the resulting dc current and voltage establish an

operating point on the characteristics that define the region that will be employed for

amplification of the applied signal. Since the operating point is a fixed point on the

3

characteristics, it is also called the quiescent point (abbreviated Q-point).The intersection

of the two points is called operating point.

By definition, quiescent means quiet, still, inactive. The above figure as a general output

device characteristic with three operating points indicated. The biasing circuit can be designed to

set the device operation at any of these points or others within the active region. Fig shows the

horizontal line for the maximum collector current ICmax and a vertical line at the

maximum collector-to-emitter voltage VCEmax. At the lower end of the scales are the cutoff

region, defined by IB0 A, and the saturation region, defined by VCE VCEsat. The BJT device

could be biased to operate outside these maximum limits, but the result of such operation would

be either a considerable shortening of the lifetime of the device or destruction of the device.

Confining ourselves to the active region, one can select many different operating areas or points.

Fig. Transistor is driven into active region because the Q point is close to the Active

for the driven input signal.

4

The chosen Q-point often depends on the intended use of the circuit. biased the BJT at a

desired operating point, the effect of temperature must also be taken into account. Temperature

causes the device parameters such as the transistor current gain () and the transistor leakage

current (ICEO) to change. Higher temperatures result in increased leakage currents in the device,

thereby changing the operating condition set by the biasing network. The result is that the

network design must also provide a degree of temperature stability so that temperature changes

result in minimum changes in the operating point. This maintenance of the operating point can be

specified by a stability factor, S, which indicates the degree of change in operating point due to a

temperature variation. A highly stable circuit is desirable,

and the stability of a few basic bias circuits will be compared.

For the BJT to be biased in its linear or active operating region the following must be true:

1. The baseemitter junction must be forward-biased (p-region voltage more positive),

with a resulting forward-bias voltage of about 0.6 to 0.7 V.

2. The basecollector junction must be reverse-biased (n-region more positive), with

the reverse-bias voltage being any value within the maximum limits of the device.

Region Active-region

operation

Cutoff-region

operation

Saturation-region

operation

Baseemitter junction

Forward biased

Reverse biased Forward biased

Basecollector junction Reverse biased Reverse biased Forward biased

5

2. Explain the fixed biasing of BJT with analysis.[MAY/JUN-10]

Biasing:- The process of giving proper supply voltages and resistances for obtaining the Q

point is called biasing.

The fixed biasing is otherwise called as base bias. For the dc analysis the network can be isolated

from the indicated ac levels by replacing the capacitors with an open circuit equivalent. In

addition, the dc supply VCC can be separated into two supplies (for analysis purposes only) as

shown in Fig to permit a separation of input and output circuits. It also reduces the linkage

between the two to the base current IB. The VCC is connected directly to RB and RC just as in Fig.

Circuit Diagram:

Base Circuit:

Consider first the baseemitter circuit loop :Writing Kirchhoffs voltage equation in the clockwise direction for the loop, we obtain

Note the polarity of the voltage drop across RB as established by the indicated direction of IB.

Solving the equation for the current IB will result in the following:

6

Equation -2 is certainly not a difficult one to remember if one simply keeps in mind that the base

current is the current through RB and by Ohms law that current is the voltage across RB divided by the resistance RB. The voltage across RB is the applied voltage VCC at one end less the drop

across the base-to-emitter junction (VBE). In addition, since the supply voltage VCC and the baseemitter voltage VBE are constants, the selection of a base resistor, RB, sets the level of base current

for the operating point.

Collector Circuit:

The collectoremitter section of the network is the indicated direction of current IC and the resulting polarity across RC. The magnitude of the collector current is related directly to IB

through

The base current is controlled by the level of RB and IC is related to IB by a constant , the magnitude of IC is not a function of the resistance RC. Change RC to any level and it will not

affect the level of IB or IC as long as we remain in the active region of the device. However, as

we shall see, the level of RC will determine the magnitude of VCE, which is an important

parameter. Applying Kirchhoffs voltage law in the clockwise direction around the indicated closed loop of Fig. will result in the following:

and

which states in words that the voltage across the collectoremitter region of a transistor in the fixed-bias configuration is the supply voltage less the drop across RC

where VCE is the voltage from collector to emitter and VC and VE are the voltages from collector

and emitter to ground respectively. But in this case, since VE = 0 V,we have

In addition,since

And VE=0V

7

3. Determine the following for the fixed bias configuration of fig. [MAY/JUN-10]

(a) IBQ and ICQ. (c) VB and VC.

(b) VCEQ. (d) VBC

3. Explain the collector to base biasing of BJT with analysis.[NOV/DEC-09]

The fig shows the dc bias with voltage feedback. It is also called the collector to base boas. It is

an improvement over the fixed bias method. In this biasing resistor is connected between the

collector and base of the transistor to provide a feedback path. Thus IB flows through RB

and(IC+IB) flow through the RC.

Circuit Diagram:

Circuit Analysis:

Base Circuit:

Let us consider the base circuit, apply the voltage law to the base circuit we get,

VCC = (RB+RC)IB+ICRC+VBE = (RB+RC)IB+ IB RC+VBE IB = VCC-VBE / RB+ RC >>1

8

Collector Circuit:

Apply KVL to the output circuit

VCC = (IC+ IB) RC +VCE VCE = VCC-(IC+IB)RC

4. Determine the quiescent levels of ICQ and VCEQ for the network of Fig.

5. Explain the Voltage divider biasing of BJT with analysis.[NOV/DEC -07,12] In the previous bias configurations the bias current ICQ and voltage VCEQ were a function of

the current gain () of the transistor. However, since is temperature sensitive, especially for silicon transistors, and the actual value of beta is usually not well defined, it would be desirable

to develop a bias circuit that is less dependent, or in fact, independent of the transistor beta If

analyzed on an exact basis the sensitivity to changes in betais quite small. If the circuit

parameters are properly chosen, the resulting levels of ICQ and VCEQ can be almost totally

independent of beta.

Circuit Diagram:

Base Circuit:

Let us consider base circuit,Voltage across

base R2 is the voltage VB,Apply KVL voltage

divider theorem to find the VB, we get,

9

I>> IB

Collector Circuit:

Let us consider collector circuit, voltage across RE(VE) can be obtained as,

Apply KVL to the collector circuit,

Simplified Circuit of Voltage Divider Bias:

Her R1 and R2 are replaced by RB and VT, where RB is the Thevenins voltage. RB can be

calculated as,

6. For the circuit as shown in fig. =100 for the si transistor. Calculate VCE an

10

7. For the circuit shown in fig.IC=2mA, =100 , Calculate RE,VEC and stability factor.

11

8. 8. Stability factor for a fixed bias circuit. [MAY/JUN-10] [NOV/DEC-09]

12

9. Explain about the fixed bias configuration for JFET with analysis.

The simplest of biasing arrangements for the n-channel JFET. Referred to as the fixed-bias

configuration, it is one of the few FET configurations that can be solved just as directly using

either a mathematical or graphical approach. The configuration of Fig. 6.1 includes the ac levels

Vi and Vo and the coupling capacitors (C1 and C2). Recall that the coupling capacitors are open circuits for the dc analysis. Circuit Diagram:

DC analysis:

The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as

appearing in the network.The fact that the negative terminal of the battery is connected directly

to the defined positive potential of VGS clearly reveals that the polarity of VGS is directly

opposite to that of VGG. Applying Kirchhoffs voltage law,

Since VGG is a fixed dc supply, the voltage VCC is fixed in magnitude, and hence the name fixed

circuit.

The drain to source voltage of output circuit can be determined by applying KVL.

13

The Q point of the JFET amplifier with fixed bias circuit is given by:

Since VGS is a fixed quantity for this configuration, its magnitude and sign can simply be

substituted into Shockleys equation and the resulting level of ID calculated. Graphical Analysis: A graphical analysis would require a plot of Shockleys equation as shown in. Recall that choosing VGS= VP/2 will result in a drain current of IDSS/4 when plotting the

equation. For the analysis of this chapter, the three points defined by IDSS, VP, and the intersection

just described will be sufficient for plotting the curve.

The fixed level of VGS has been superimposed as a vertical line at VGS= -VGG. At any point on the

vertical line, the level of VGS is VGG the level of ID must simply be determined on this vertical line. The point where the two curves intersect is the common solution to the configuration-

commonly referred to as the quiescent or operating point. The subscript Q will be applied to

drain current and gate-to-source voltage to identify their levels at the Q-point. Note in Fig. 2 that

the quiescent level of ID is determined by drawing a horizontal line from the Q-point to the

vertical ID axis as shown in Fig. 2.

The drain-to-source voltage of the output section can be determined by applying Kirchhoffs voltage law as follows

14

Determine the following for the network of Fig.

(a) VGSQ.

(b) IDQ.

(c) VDS.

(d) VD.

(e) VG. (f) VS.

Graphical Approach:

The resulting Shockley curve and the vertical line at VGS=-2 V are provided in above fig. It is

certainly difficult to read beyond the second place without significantly in\

15

10. Discuss the various techniques of stabilization of Q-point in a transistor. [NOV/DEC-

09]

16

17

18

19

11. The amplifier shown in Fig. an n-channel FET for which, ID=0.8mA, VP=-20V and

IDSS=1.6mA. Assume that rd>Rd. Find (1) VGS (2) gm (3) Rs. [NOV/DEC-2007]

20

UNIT-2

PART-B

ANNA UNIVERSITY QUESTIONS

1) Compare CB,CE and CC amplifiers [NOV/DEC-09,11][APR/MAY-10,13]

Characteristics Common base Common emitter Common collector

Input resistance Very low Low High

output resistance Very high High Low

Input voltage

applied between

Emitter and base Base and emitter Base and collector

Output voltage

taken between

Collector and base Collector and

emitter

Emitter and

collector

Current

amplification factor E

C

I

I

B

C

I

I

B

E

I

I

Current gain Less than unity High High

Voltage gain Medium Medium low

applications As a input stage of

multistage

amplifiers

For audio signal

amplification

For impedance

matching

CE Amplifier

Circuit

CC Amplifier

Circuit

21

2) Derive the expression for the following of a small signal transistor amplifier in terms

of the h-parameters,

a) Current gain

b) Voltage gain

c) Input impedance

d) Output admittance [APR/MAY-10,11][NOV/DEC-06,12]

Let us consider transistor amplifier as a black box as shown ,

CB Amplifier

Circuit

22

23

24

Table Summarizing the Equations

25

3) Explain The Operation Of Emitter Coupled Differential Amplifier.

[APR/MAY-10][NOV/DEC-06,09,11]

The transistorized differential amplifier is also called as emitter coupled differential

amplifier.

1

1

26

27

28

4) For the CC transistor amplifier circuit, find the expression for input impedance and

voltage gain. Assume suitable model for transistor. [ NOV/DEC-09]

For a common collector model ,collector is made as common and output is taken

from emitter . the current direction is now exactly opposite that of CE model because the current

always points towards emitter.

29

5) With mathematical substantiation draw the basic circuit of Darlington pair and explain.

[NOV/DEC-08]

DARLINGTON TRANSISTORS

The direct coupling of two stages of emitter follower amplifier and this cascaded

connection of two emitter followers is called the Darlington connection.

30

31

32

33

34

35

6) Explain bootstrapped Darlington circuit with neat sketch [NOV/DEC-06]

Bootstrapped Darlington Circuit

36

In bootstrap emitter follower while eliminating the shunting effect of 1 2R and R

there exists a maximum limit on the input resistance. This maximum limit is put by the

collector to base resistance of transistor that appears in parallel with input resistance. This

is expressed in admittance form by the parameter obh of the transistor.

37

38

7. Explain the common emitter amplifier.

To make the transistor work as an amplifier, it is to be biased to operate in the active region,

(i.e.) base emitter junction is to be forward biased, while base collector junction to be

reversed biased.

Let us consider the common emitter amplifier circuit using self bias or voltage divider bias as

shown above.

In the absence of input signal, only dc voltages are present in

the circuit. This is known as zero-signal or no signal condition

or quiescent condition for the amplifier. The dc collector

emitter voltage VCE , the dc collector current IC and dc base

current IB is the quiescent operating point for the amplifier. On

this dc quiescent operating point, we super impose ac signal by

application of ac sinusoidal voltage at the input. Due to this

base current varies sinusoidally as show in fig.

The output current i.e. the collector current is times larger than the input base current in

common emitter configuration. Hence the collector current will also vary sinusoidally about

its quiescent value, ICQ. The output voltage will also vary sinusoidally as shown below.

39

The variations in the collector current and the voltage between collector and emitter due to

change in the base current are shown below with the help of load line.

The collector current varies above and below its Q point value in-phase with the base current

and the collector to emitter voltage varies above and below its Q point value 180 out of,

phase with the base voltage.

When one cycle of input is completed, one cycle of output will also be completed. This means

the frequency of output sinusoidal is the same as the frequency of input sinusoid.

40

8. Explain the practical common emitter amplifier circuit.

It consists of different circuit component. The functions of these components are as

follows.

Biasing circuit

The resistances R1, R2 and RE form the voltage divider biasing circuit for the CE

amplifier. It sets the proper operating point for the CE amplifier.

Function of Input capacitor C1 in CE amplifier circuit

This capacitor couples the signal to the base of the transistor. It blocks any dc

component present in the signal and passes only ac signal for amplification.

Need for emitter bypass capacitor CE is used in CE amplifier circuit

An emitter bypass capacitor CE is connected in parallel with the emitter resistance RE to

provide a low reactance path to the amplified ac signal. If it is not inserted, the amplified ac

signal passing through RE will cause a voltage drop across it. This will reduce the output

voltage, reducing the gain of the amplifier.

Need for output coupling capacitor C2

The coupling capacitor C2 couples the output of the amplifier to the load or to the next stage of

the amplifier. It blocks dc and passes only ac part of the amplified signal.

Need for C1, C2 and CE

41

We know that the impedance of capacitor is given as,

Xc = 1

2 f c

Thus, at signal frequencies, all the capacitors have extremely small impedance and it can be

treated as an ac short circuit. For bias / dc conditions of the transistor all the capacitors act as a

dc open circuit.

Consider that the signal source is connected directly to the base of the transistor as shown

below.

The source resistance Rs is in parallel with R2 and this will

reduce the bias voltage at the transistor base and consequently

alter the collector current, which is not desired. By connecting RL

directly, the dc levels of Vcc and VCE will change. So to avoid this

and maintain the stability of bias condition coupling

capacitors are connected. By connecting C1, any dc component in

the signal is opposed and only ac signal is routed to the

transistor amplifier.

The emitter resistance RE provides bias stabilization. But it also reduces the voltage

swing at the output. The emitter bypass capacitor CE provides a low reactance path to the

amplified ac signal increasing the output voltage swing.

For the proper operation of the circuit, polarities of the capacitors must be connected

correctly. The ve terminal must always be connected at a dc voltage level lower than the dc

level of +ve terminal.

9. Explain the common collector amplifier circuit in detail.

The dc biasing is provided by R1, R2 and

RE, the load resistance is capacitor coupled to the

emitter terminal of the transistor.

42

When a signal is applied via to the base of the transistor, VB is increased and

decreased as the signal goes positive and negative respectively.

From the figure, we can write that,

VE = VB VBE.

Considering VBE fairly constant, variation in the VB appears at emitter and emitter voltage VE

will vary same as base voltage VB. Since the emitter is output terminal, the output voltage from a

common collector circuit is the same as its input voltage

10. Obtain the gain, input impedance and output impedance of single stage BJT amplifier

using midband analysis.

[OR]

Derive the expressions for the current gain, input impedance, voltage gain and output

admittance of a small signal transistor amplifier in terms of the h-parameters. [May-2006]

The above shows basic amplifier circuit. To form a transistor amplifier only it is necessary to

connect an external load and

signal source, along with proper

biasing. We can replace transistor

circuit with its small signal hybrid

model.

43

Let us analyze hybrid model to find the current gain, the input impedance, the voltage gain, and

output impedance.

Current Gain (Ai)

For transistor amplifier Ai is defined as the ratio of output to input currents. It is given by,

1

2

1 I

I

I

IA Li

Here IL and I2 are equal in magnitude but opposite in sign. i.e., IL= -I2

From the circuit equivalent circuit we have,

I2 = hf I1 + h0 V2

Substituting V2 = - I2 RL in the equation we obtain,

I2 = hf I1 + h0 (- I2 RL)

I2 + h0 I2 RL = hf I1

I2(1 + h0 RL) = hf I1

L

f

i

L

f

Rh

h

I

IA

Rh

h

I

I

01

2

01

2

1

1

Current Gain (Ais)

It is the current gain taking into account the source resistance, RS if the model is

driven by the current source instead of voltage source. It is given by

Is

IAA

Is

I

I

I

Is

IA

isi

si

1

1

1

22

*

*

L

f

iRh

hA

01

44

Looking at above fig (b) and using current divider equation we get

RsZi

AiRsA

RsZi

Rs

Is

I

RsZi

IsRsI

is

1

1

Input impedance (Zi)

Ri is the input resistance looking into the amplifier input terminals (1, 1). It is given by,

1

1

I

VRi

From the input circuit of equivalent circuit, we have

LiL

ri

i

ri

RIARIVngSubstituti

I

VhIh

I

VZ

VhIhV

122

1

21

1

1

211

In the above equation we get,

L

Lfr

ii

L

f

i

LiriLir

ii

Rh

RhhhZgetWe

Rh

hAngSubstituti

RAhhI

RIAhhZ

0

0

1

1

1,..........

1........

Dividing numerator and denominator by RL we get,

RsZi

AiRsAis

45

L

L

L

fr

ii

L

fr

ii

RYWhere

hY

hhhZ

hR

hhhZ

1......

1

0

0

From this equation we can note that input impedance is a function of the load

impedance.

Voltage Gain (AV)

It is the ratio of output voltage V2 to the input voltage V1. It is given by

ii

lili

V

LiV

ZV

ISince

Z

RA

V

RIAA

RIAVngSubstitutiV

VA

1.........

..........

1

1

1

1

12

1

2

Voltage Gain (AVS)

It is voltage gain including the source. It is given by,

MV

VAA

V

V

V

V

V

VA

S

VVS

SS

VS

.................*

*

1

1

1

22

Applying potential divider thermo we can write,

i

liV

Z

RAA

0hY

hhhZ

L

fr

ii

46

ZiR

Zi

V

V

VZiR

ZiV

SS

S

S

1

1

Substituting value of SV

V1 in equation M we get,

Zi

AiRA

RiR

AiRA

ZiR

ZiAA

L

SV

S

LVS

S

VVS

*

Output Admittance Y0

It is the ratio of output current I2 to the output voltage V2. It is given by,

withV

IY

2

20 VS=0

We Know, I2 = hf I1 + h0 V2.

Dividing above equation by V2 we get,

2

2

V

I= 0

2

1 hV

Ih f

Y0= NhV

Ih f ..............0

2

1

From fig with VS = 0 we can write,

RS I1 + hi I1 + hr V2 = 0

iS

r

riS

hR

h

V

I

VhIhR

2

1

21)(

Substituting value of 2

1

V

I in equation N We get,

Zi

AiRA L

SV

47

From this equation we can note that output admittance is a function of the source

resistance.

11. Give the comparison between CB, CE and CC amplifiers

S.No Characteristics Common

Base Common Emitter

Common Collector

1 Input Resistance Very Low

(20) Low (1 K)

High (500 K)

2 Output Resistance Very High

(1 M)

High

(40K)

Low (50 )

3 Input Current IE IB IB

4 Output Current IC IC IE

5 Input Voltage applied

between Emitter and

Base Base and Emitter

Base and Collector

6 Output Voltage taken

from Collector and

Base Collector and

Emitter Emitter and

Collector

7 Current amplification

factor E

C

I

I

B

C

I

I

B

E

I

I

8 Current Gain Less than

Unity High(20 to

few hundred) High(20 to

few hundred)

9 Voltage Gain Medium Medium Low

10 Applications

As a input stage of

multistage amplifier

For audio signal

amplification

For impedance matching

Y0=iS

rf

hR

hhh

0

48

12. State and prove the Millers theorem. [ APR/MAY-13]

Millers Theorem

Millers theorem states that the current I1 drawn from node 1 through the impedance Z

can be obtained by disconnecting node 1 from Z and by bringing impedance )1( K

Z

from node

1 to ground, )1( K

ZK from node 2 to ground.

If Z is the impedance connected between two nodes, node 1 and node 2.

Z is replaced by two separate impedances Z1 and Z2. Where Z1 is connected between node 1

and ground and Z2 is connected between node 2 and ground.

The Vi and V0 are the voltages at the node 1 and node 2 respectively.

The values of Z1 and Z2 can be derived from the ratio of V0 and Vi denoted as K.

The values of impedance Z1 and Z2 are

1Z)1( K

Z

; 2Z

)1( K

ZK

Proof of Millers Theorem

Millers theorem stats that, the effect of resistance Z on the input circuit is a ratio of input

voltage Vi to the current I which flows from the input to the output.

Therefore,

49

Z

AV

Z

V

VV

Z

VVIWhere

I

VZ

Vii

i

i

i

11

,

0

0

1

K

Z

A

Z

I

VZ

V

i

111 KA

V

VV

i

0

Millers theorem states that, the effect of resistance Z on the output circuit is a ratio of output

voltage V0 to the current I which flows from the output to the input.

Therefore,

Z

A

AV

Z

AV

Z

V

VV

Z

VVIWhere

I

VZ

V

V

V

i

i

1111

,

00

0

0

0

0

2

1111

02

K

ZK

A

ZA

A

A

ZVZ

V

V

V

V

KAV

VV

i

0

K

ZZ

11

12

K

ZKZ

50

13. Explain the techniques of improving input impedance. [ NOV/DEC-11,12]

51

52

53

54

55

14. Draw a Small signal equivalent circuit for Common Emitter amplifier (or) Methods of

analyzing of a transistor.

56

57

15. Draw and explain the JFET low frequency small signal model.

58

16. Draw the small signal analysis of common source amplifier with fixed bias.

59

60

.

17.

Explai

n the methods of coupling multistage amplifier

61

62

18. (i). Draw a cascade amplifier and its equivalent circuit. What are the special features

of cascade amplifier?

63

(ii). Derive the voltage gain, input impedance and output impedance of the above

cascade amplifier.

Cascade amplifier:-

The cascade amplifier consists of a common emitter amplifier stage in eries

with a common base amplifier.

Transistor T1 and its associated components operate as a common emitter

amplifier stage, while the circuit of T2 functions as a common base output

stage.

The cascade amplifier gives the high input impedance of a common emitter

amplifier, as well as the good voltage gain and high frequency performance

of a common base circuit.

For the dc bias conditions of the circuit, it is seen that the emitter current for T1 is

set by VE1 and RE1.

Collector current IC1 approximately equals IE1 and IE2 is same as IC1. Therefore, IC2

approximately equals IE1.This current remains constant regardless of the level of

VB2, as long as VCE1 remains enough for current operation of T1.

The AC equivalent circuit for cascade amplifier is drawn by shorting dc supply

and capacitors

64

The simplified h-parameter equivalent circuit for cascade amplifier is drawn by

replacing transistors with their simplified equivalent circuits.

Analysis of second stage (CB amplifier):-

a). Current gain (Ai2);-

fe

fe

ih

hA

12

b). Input resistance (Ri2):-

fe

iei

h

hR

12

65

c). Voltage gain (AV2):-

2

222

i

LiV

R

RAA

Analysis of first stage (CE amplifier):-

a). Current gain (Ai1);-

Ai1 = - hfe

b). Input resistance (Ri1):-

Ri1 = hie

c). Voltage gain (AV1):-

1

111

i

LiV

R

RAA

Overall voltage gain (AV):-

AV = AV1 * AV2

Overall input resistance (Ri):-

Ri = Ri1 || RB

RI = Ri1 || R3 || R4

Overall voltage gain (AVs):-

Si

iVVS

S

i

iS

VS

RR

RAA

V

V

V

V

V

VA

00

Overall current gain (Ais):-

1

11

1

12

2

2

1

1

1

1

2

2

2

2

00

:;iB

B

S

bi

b

Ci

e

C

S

b

b

C

C

e

e

C

CS

iS

RR

R

I

IA

I

IA

I

I

I

I

I

I

I

I

I

I

I

I

I

IA

66

1

1

2

22

2

0

iB

Bi

e

Ci

C

iSRR

RA

I

IA

I

IA

Output resistance (R0):-

R01 =

R02 =

R0 = R02 || RL

19. Draw the circuit diagram for a differential amplifier using BJTs. Describe common

mode and differential modes of working. [ APR/MAY-10,12] [ NOV/DEC-06,08]

Differential amplifier:-

The differential amplifier amplifies the difference between two input

voltage signals. In an ideal differential amplifier, the output voltage Vo is

proportional to the difference between the two input signals.

V0 ~ (V1 V2).

Assume that the sine wave on the base of Q1 is positive going while on the base

of Q2 is negative going. With a positive going signal on the base of Q1, an

amplified negative going signal develops on the collector of Q1.

Due to positive going signal, current through RE also increases and hence a

positive going wave is developed across RE.

Due to negative going signal on the base of Q2, an amplified positive going signal

develops on the collector of Q2. And a negative going signal develops across RE,

because of emitter follower action of Q2.

67

So signal voltage across RE, due to the effect of Q1 and Q2 are equal in magnitude

and 1800 out of phase, due to matched pair of transistors. Hence these two

signals cancel each other and there is no signal across the emitter resistance.

Hence there is no a.c signal current flowing through the emitter resistance. Hence

RE in this case does not introduce negative feedback.

While V0 is the output taken across collector of Q1 and collector Q2.The two

outputs on collector 1 and 2 are equal in magnitude but opposite in polarity.

The V0 is the difference between these two signals. Hence the difference output

V0 is twice as large as the signal voltage from either collector to ground.

Common Mode Operation:-

In Common mode, the signals applied to the base of Q1 and Q2 are derived from

the same source. So the two signals are equal in magnitude as well as in phase.

In phase signal voltages at the base of Q1 and Q2 causes in phase signal voltages

to appear across RE, which add together. Hence RE carries a signal current and

provides a negative feedback. This feedback reduces the common mode gain of

differential amplifier.

While the two signals causes in phase signal voltages of equal magnitude to

appear across the two collectors of Q1 and Q2

Now the output voltage is the difference between the two collector voltages,

which are equal and also same in phase. Thus the difference output V0 is almost

zero, negligibly small. Ideally it should be zero.

68

20. Derive the DC analysis of differential amplifier.

69

70

21. What is a transfer characteristic of differential amplifier? Derive it. [MAY -

2006]

The transfer characteristic of the differential amplifier is the graph of

differential input Vd against the currents IC1 and IC2.

To obtain the transfer characteristics, the following assumptions are made:

1. The current source circuit used with current IEE has infinite output

resistance.

2. The source resistances RS in the base of transistors Q1 and Q2 are

neglected.

3. The output resistance of each transistor is infinite.

The assumptions are valid for low frequency, large signals.

For a transistor, we can write the equation for its collector current as

T

BE

V

V

SC eII

Where,

IS = reverse saturation current.

VBE = base emitter voltage.

71

VT = voltage equivalent of temperature.

Thus for two transistors we can write the equations for their collector currents as,

T

BE

T

BE

V

V

SC

V

V

SC

eII

eII

2

1

2

1

Where IS1 = IS2 = IS as transistors are matched.

This equation is called as Ebers- Moll equation for the transistor.

S

CTBE

S

CTBE

T

BE

S

C

I

IVV

I

IVV

V

V

I

I

22

11

11

ln

ln

ln

Now consider the loop including two inputs and two base emitter junctions,

neglecting RS, as shown in the fig.

Applying KVL to the loop shown,

VS1 VBE1 + VBE2 VS2 = 0

72

Substituting VBE1 and VBE2 values in above equation, we get,

12

12

2

21

1

lnln

0lnln

SS

S

C

S

C

T

S

S

C

T

S

C

TS

VVI

I

I

IV

VI

IV

I

IVV

dSS

V

VV

C

C

T

SS

C

C

SS

C

CT

SS

S

C

S

C

T

SS

S

C

S

CT

VVV

eI

I

V

VV

I

I

VVI

IV

VV

I

I

I

I

V

VVI

I

I

IV

T

SS

21

2

1

21

2

1

21

2

1

212

1

2121

21

ln

ln

ln

lnln

T

d

V

V

C

C eI

I

2

1.A ; Vd = differential input.

Now current through current source IEE is the addition of the two emitter

currents IE1 and IE2.

IEE = IE1+IE2B

But 211

; CCERC

E IIII

I

Solving equations A and B simultaneously for IC1 and IC2 we get,

T

d

T

d

V

V

EEC

V

V

EEC

e

II

e

II

1

1

1

1

73

From these two equations, the transfer characteristics can be obtained.

UNIT-3

1. Draw the high frequency hybrid model for a transistor in the CE configuration and explain

the significance of each component. [Nov/Dec-09] [ APR/MAY-12]

Hybrid - Common Emitter Transistor Model

Common emitter circuit is most important practical configuration and hence we have chosen this

circuit for the analysis of transistor using hybrid - model for a transistor in the CE configuration.

For this model, all parameters (resistances and capacitances) in the model are assumed to be

independent of frequency. But they may vary with the quiescent operating point.

Elements in the Hybrid - model

Cbe and Cbc :

We know that, forward biased PN junction exhibits a capacitive effect called the

diffusion capacitance. This capacitive effect of normally forward biased base-emitter junction of the

transistor is represented by Cbe or Ce connected between B and E represents the excess minority

carrier storage in the base.

The reverse bias PN junction exhibits a capacitive effect called the transition capacitance. This

capacitive effect of normally reverse biased collector base junction of the transistor is represented by

Cc in the hybrid - model.

74

rbb' : The internal node b is physically not accessible bulk node B represents external base terminal.

The bulk resistance between external base terminal and internal node B is represented as rbb , as

shown in the fig. this resistance is called as base spreading resistance.

Virtual Base:

rbe : The resistance rbe is that portion of the base emitter which may be thought of as being in series

with the collector junction. This establishes a virtual base B for the junction capacitances to be

connected to instead of b. this is illustrated in fig.

rbc: We know that, due to early effect, the varying voltages across the collector to emitter junction

results in base-width modulation. A change in the effective base width causes the emitter current to

change. This feedback effect between output and input is taken into account by connecting gbc or rbc

between n and c.

gm :Due to the small changes in voltage Vbe across the emitter junction, there is excess-minority

carrier concentration injected into the base which is proportional to the Vbe. This effect accounts for

the current generator gm Vbe in fig.

gm is called transconductance and it is given as

eb

C

mV

Ig

'

At constant VCE

rce: The rce is the output resistance. It is also the result of the early effect.

2. Derive the expression for CE short circuit current gain and current gain with resistive load, at

high frequencies. (16 Marks)[Dec-2003, May-2007]

` CE Short circuit gain using hybrid model:

75

For the

analysis of short circuit current gain we have to assume RL = 0.

With RL = 0, i.e. output short circuited rce becomes zero, rbe , Ce and Cbc appear in parallel.

When CC admittance is given as

LmCb

eb

Cb

M RgcjV

icCj 1'

'

'

Hence, the miller capacitance is CM = LmCb Rgc 1'

Here, RL = 0

CM = Cbc (CC)

As rbe >> rbe, rbC is neglected. With these approximations we get simplified hybrid model

for short circuit CE transistor as shown in above figure.

Parallel combination of rbe ,and (Ce+ CC) is given as

76

)C+(Cj+

r=Z

)C+j(+r

)C+j(r

=Z

Ceeb'

eb'

Ce

eb'

Ce

eb'

1

1

1

Further simplified hybrid- model

We can write

b

eb

beb

I

VZ

ZIV

'

'

The current gain for the above circuit can be given as

ebmL

b

ebm

b

L

i VgII

Vg

I

IA '

'

Substituting value of Vbe / Ib ;

)(1 '

'

Ceeb

ebm

i

mi

CCrj

rgA

ZgA

We know that hfe = gm rbe

Current Gain with Resistive Load

)(1 ' Ceeb

fe

iCCrj

hA

77

In the output circuit rce is in parallel with RL. For high frequency amplifiers RL is small as

compared to rce and hence we can neglect rce. Using Millers theorem, we can split rbC and CC to

simplify the analysis.

Further simplification of input circuit

Amplifier gain K is given as

Lm

Lebm

eb

RgK

RVgWhereV

V

VK

'0

'

0

Assuming RL =2K and gm = 50 mA/V

We get K= -100

78

And K

M

K

rCb 40)100(1

4

1

'

MrCb 4'

The value rbC / (1-K) >> rbe (1K) and hence rbC / (1-K) which is in parallel with rbe

can be neglected.

CC also resolved by Millers theorem.

1................11

1

1

1

1

LmCC

LmC

C

RgCCK

C

RgCjK

Cj

As Ce and C are in parallel, the total equivalent capacitance is given as

LmCeeq RgCCC 1

..2

From equation (2) we can say that input capacitance

Is increased. CC (1+gm RL) is called Miller capacitance.

With these approximations input circuit becomes,

as shown in figure (B).

Further simplification for output circuit:-

At output circuit value of CC can be calculated as

CC

C

C

CK

KC

KCj

KK

Cj

1

1001

1

1

At figure (B) we can see that there are two independent time constants, one associated with the

input circuit and one associated with the output circuit.

As input capacitance [Ce + CC(1+gm RL)] is very high in comparison with output capacitance

[CC].

79

As results, output time constant is negligible in comparison with the input time constant and may

be ignored.

100;1

''

Kr

K

Kr CbCb

M4

This value of rbC is very high in comparison with load resistance RL which is parallel with rbC.

Hence rbC can be ignored.

Parallel combination of rbC and Ceq is given as

eqeb

eb

eqeb

eqeb

Crj

r

Cjr

Cjr

Z'

'

'

'

11

1

This gives equivalent circuit as shown in below.

From the above figure we can write, ZIV beb ' b

eb

I

VZ '

The current gain for the circuit can be given as,

80

b

ebm

b

Li

I

Vg

I

IA '

Substituting value of Z we get,

ebmfeeqeb

fe

eqeb

ebm

i rghCfrj

h

Crj

VgA '

''

' ;211

3. What are the effects of coupling, bypass capacitors and internal capacitances on the bandwidth

of the amplifier? (8) [Dec-2003]

Effect of Coupling Capacitors:-

The reactance of a capacitor is fCXC 2

1 .

At medium and high frequencies, the factor f makes XC very small, so that all coupling

capacitors behave as short circuits.

At low frequencies, XC increases. This increase in XC drops the signal voltage across the

capacitor and reduces the circuit gain.

As signal frequencies decrease, the capacitor reactance increases increase and circuit gain

continues to fall, reducing the output voltage.

Effect of Bypass Capacitors:-

At lower frequencies, the bypass capacitor CE is not a short. So, the emitter is not at ac ground.

XC in parallel with RE (RS in case of FET) creates impedance. The signal voltage drops across this

impedance reducing the circuit gain.

eqeb

fe

iCfrj

hA

'21

81

Effect of internal Capacitances:-

At high frequencies, the coupling capacitors acts as short circuit and do not affect the amplifier

frequency response.

However, at high frequencies, the internal capacitances, commonly known as junction capacitances

do come into play, reducing the circuit gain.

In case of the BJT, Cbe is the base emitter junction capacitance and Cbc is the base collector junction

capacitance.

In case of JFET, Cgs is the internal capacitance between gate and source and Cgd is the internal

capacitance between gate and drain.

At higher frequencies, the reactance of the junction capacitances is low.

As frequency increases, the reactance of junction capacitances falls. When these reactances become

small enough, they provide shunting effect as they are in parallel with junctions. This reduces the

circuit gain and hence the output voltage.

1. Derive expressions for the short circuit current gain of common emitter amplifier at HF.

Define alpha cut-off frequency, beta cut-off frequency and transition frequency and derive their

values in terms of the circuit parameters. [May-2005]

CE Short circuit gain using hybrid model

For the analysis of short circuit current gain we have to assume RL = 0.

With RL = 0, i.e. output short circuited rce becomes zero, rbe , Ce and Cbc appear in parallel.

When CC admittance is given as

LmCb

eb

Cb

M RgcjV

icCj 1'

'

'

82

Hence, the miller capacitance is CM = LmCb Rgc 1'

Here, RL = 0 CM = Cbc (CC)

As rbe >> rbe, rbC is neglected. With these approximations we get simplified hybrid model for

short circuit CE transistor as shown in above figure.

Parallel combination of rbe ,and (Ce+ CC) is given as

)(1

)(

1

)(

1

'

'

'

'

Ceeb

eb

Ce

eb

Ce

eb

CCrj

rZ

CCjr

CCjr

Z

Further simplified hybrid- model:-

We can write ZIV beb ' ;

b

eb

I

VZ '

The current gain for the above circuit can be given as

ebmL

b

ebm

b

L

i VgII

Vg

I

IA '

'

Substituting value of Vbe / Ib ;

83

)(1 '

'

Ceeb

ebm

i

mi

CCrj

rgA

ZgA

We know that hfe = gm rbe

..(A)

From the equation (A) we can say that current is not constant.

When frequency is small, the term containing f is very small

Compared to 1 and hence at low frequency, Ai = -hfe.

But as frequency increases Ai reduces as shown in fig.

Let us put

Ceeb CCrf

'2

1

Substituting value of f in equation (A) we get,

2||

...............

1

||

1

2

fe

i

fe

i

fe

i

hA

fAtf

N

f

f

hA

f

fj

hA

f (Cut-off frequency):-

It is the frequency at which transistors short circuit CE current gain drops by 3dB or 1/ 2

times its value at low frequency. It is given as

)(1 ' Ceeb

fe

iCCrj

hA

84

fem

eb

eb

Ce

m

fe

Ce

eb

Ceeb

h

g

rg

CC

g

hfor

CC

gfor

CCrf

'

'

'

'

1;

2

1)(

2)(

2

1

f (Cut-off frequency):-

It is the frequency at which transistors short circuit CB current gain drops by 3dB or 1/ 2

times its value at low frequency. It is given as

efbeb

fb

i

Chrf

where

f

fj

hA

12

1

,

1

'

2||

1

||

22

1

2

''

fb

i

fb

i

eeb

fe

eeb

fe

hA

fAtf

f

f

hA

Cr

h

Cr

hf

The parameter fT:-

It is the frequency at which short circuit CE current gain becomes unity.

At f = fT, equation (N) becomes

2

1

1

f

f

h

T

fe

..(X)

The ratio of fT/f is quite large compared to 1. Hence equation (X) becomes,

85

fhf

f

fh

ff

h

feT

T

fe

T

fe

1

Substituting values of f , we get

Cem

T

Cefe

m

feT

CC

gf

CCh

ghf

2

2

Since Ce >> CC we can write, e

mT

C

gf

2

2. Derive the equation for gm which gives the relation between gm, IC temperature. [May-2003]

Let us consider a p-n-p transistor in the CE configuration with VCC bias in the collector

circuit.

The transconductance is nothing but the ratio of change in the collector current due to small changes

in the voltage VBE across the emitter junction. It is given as,

VCEEB

C

mV

Ig |

'

..(1)

We know that, the collector current in active region is given as

ECOC III And therefore

.tan; tconsIII COEC Substituting value of CI in equation (1) we get,

EBE

E

E

EB

Em VV

V

I

V

Ig '

'

..2

The emitter diode resistance, re is given as

E

E

e

E

Ee

I

V

r

I

Vr

1

Substituting re in place of EE VI we get,

86

e

mr

g

..3

The emitter diode is a forward biased diode and its dynamic resistance is given as,

E

Te

I

Vr

4

Where VT is the volt equivalent of temperature, defined by

q

KTVT

Where K is the Boltzmann constant in joules per degree Kelvin (1.38*10-23J/0K) is the electronic

charge (1.6*10-19

C).

Substituting value of re in equation (3) we get,

ECOC

T

CCO

T

Em III

V

II

V

Ig ;

For pnp transistor IC is negative. For an npn transistor IC is positive, but the foregoing analysis (with

VE = +VBE) leads to .TCOCm VIIg

Hence, for either type of transistor, gm is positive.

COCT

COC

m IIV

IIg

;

..5

Substituting value of VT in equation (5) we get,

T

I

T

I

KT

qIg CCCm

11600

1038.1

106.123

19

..(6)

From equation (6) we can say that transconductance gm is directly proportional to collector current

and inversely proportional to temperature.

3. Define the expression for lower 3dB and higher 3dB frequency for cascaded amplifier.

Lower Cut-off frequency (3dB)

Let us consider the lower 3dB frequency of n identical cascaded stages as fL(n). It is the

frequency for which the overall gain falls to 1/ 2 (3dB) of its midband value.

87

n

L

L

n

L

L

nf

f

nf

f

2

2

12

2

1

1

1

Squaring on both sides we get,

n

L

L

nf

f

2

12

Taking nth

root on both sides we get,

21

21

12

12

nf

f

nf

f

L

Ln

L

Ln

Taking square root on both sides we get

12

12

1

1

n

LL

L

Ln

fnf

nf

f

Where, nfL = Lower 3dB frequency of identical cascaded stages.

Lf = Lower 3dB frequency of single stage.

n = number of stages.

Higher Cut-off frequency (3dB):-

Let us consider the lower 3dB frequency of n identical cascaded stages as fH(n). It is the

frequency for which the overall gain falls to 1/ 2 (3dB) of its midband value.

12

1

n

LL

fnf

88

n

H

H

n

H

H

f

nf

f

nf

2

2

12

2

1

1

1

Squaring on both sides we get,

n

H

H

f

nf

2

12

Taking nth

root on both sides we get,

21

21

12

12

H

Hn

H

Hn

f

nf

f

nf

Taking square root on both sides we get

12

12

1

1

nHH

H

Hn

fnf

f

nf

Where, nf H = Higher 3dB frequency of identical cascaded stages.

Hf = Higher 3dB frequency of single stage.

n = number of stages.

In multistage amplifier fL(n) is always greater than fL and fH(n) is always less than fH.

Therefore, we can say that bandwidth of multistage amplifier is always less than single stage

amplifier.

If stages are not identical fH can be given as

121

nHH fnf

22

2

2

1

1........

111.1

1

nH ffff

89

4. What is rise time? Derive the relation between rise time and upper Cut-off frequency and

bandwidth.

Rise time

The rise time is an indication of how fast the amplifier can respond to a discontinuity in the input

voltage.

Rise Time and its relation to Upper Cut-off frequency

When a step input is applied, the amplifiers high frequency RC networks prevent the

output from responding immediately to the step input.

The output voltage starts from zero and rises towards the steady state value V, with a time constant R2

C2.

The output voltage is given by

221/0 1 CRteVV .(1) The time required for V0 to reach one-tenth of its final value is calculated as

)2....(..........1.0

1.0

9.0

11.0

11.0

221

22

1

/

/

/

221

221

221

CRt

CR

t

e

e

eVV

CRt

CRt

CRt

90

Similarly, the time required for V0 to reach nine-tenths its final value is calculated as

)3....(..........3.2

1.0

9.0

11.0

19.0

222

22

2

/

/

/

222

222

222

CRt

CR

t

e

e

eVV

CRt

CRt

CRt

The difference between these two values (t1 &t2) is called the rise time tr of the circuit.

The time tr is an indication of how fast the amplifier can respond to a discontinuity in the input

voltage.

The rise time is given as

22

222212

2.2

1.03.2

CRt

CRCRttt

r

r

The upper 3dB frequency is given as

222

1

CRfH

Therefore, upper 3dB frequency can be represented in terms of rise time as given below:

rr

Htt

f35.0

2

2.2

Upper 3dB frequency is inversely proportional to the rise time tr.

Relation between Bandwidth and Rise time:-

The frequency range from fL to fH is called the bandwidth of the amplifier. Usually fL

91

r

Ht

fBW35.0

5. Derive the relation between Sag and Lower Cut-off frequency.

The amplifiers low frequency RC networks consists of coupling and bypass capacitors make

amplifiers output to decrease with large time constant. As a result, the output voltage has sag or tilt

associated with it.

The tilt, or sag, in time t1 is given by

%100%

100'

%

11

1

CR

ttilt

V

VVPtilt

The lower dB frequency can be determined from the output response by carefully measuring

the tilt.

We know that, the lower 3dB frequency is given as

112

1

CRfL

Therefore, lower 3dB frequency can be represented in terms of tilt

rtBW

35.0

92

6. What is the effect of coupling and bypass capacitor on the input & output circuit of a BJT

amplifier at low frequencies.

Let us consider a common emitter amplifier. The amplifier has three RC networks that affect its gain

as the frequency is reduced below midrange. These are

RC network formed by the input coupling capacitor C1 and the input impedance of the

amplifier.

1. RC network formed by the output coupling capacitor C2, the resistance looking in at

the collector, and the load resistance.

2. RC network formed by the emitter bypass capacitor CE and the resistance looking in

at the emitter.

93

Input RC network:-

RC network formed by C1 and Vout is the output the input impedance of the amplifier.

voltage of the network.

Applying voltage divider theorem we can write,

in

Cin

inout V

XR

RV

2

1

2

We know that a critical point in the amplifier response is

generally accepted to occur when the output voltage is 70.7 % of the input(Vout= 0.707 Vin).

Thus we can write, at critical point

2

1707.0

2

1

2

Cin

in

XR

R

At the condition Rin = XC1.

At the condition the overall gain is reduced due t the attenuation provided by the input RC network.

The reduction in overall gain is given by

dBV

VA

in

out

V 3707.0log20log20

The frequency fC at this condition is called lower critical frequency and is given by

121

21

1

||2

1

||...

2

1

ChRRf

hRRRWhere

CRf

ie

C

iein

in

C

If the resistance of input source is taken into account the above equation becomes

121

CRRf

inS

C

The phase angle in an input RC circuit is expressed as

in

C

R

X11tan

Output RC Network:-

Output RC network formed by C2, resistance looking in at the collector and the load

resistance.

94

The critical frequency for this RC network is given by,

221

CRRf

LC

C

The phase angle in the output RC circuit is expressed as

LC

C

RR

X21tan

By pass Network: -

RC network formed by the emitter bypass capacitor CE and the resistance looking in at the

emitter.

Here, THie Rh

is the resistance looking in at the emitter. It is derived as follows

ieTHie

b

THb

ie

b

bie

e

e

hRh

I

RIR

h

I

Vh

I

VR

95

Where RTH = R1 || R2 || RS. It is the thevenins equivalent resistance looking from the base of the

transistor towards the input.

The critical frequency for the bypass network is

EE

THie

C

E

C

RCRRh

for

RCf

||2

1)(

2

1

We can see that each network has a critical frequency. It is not necessary that all these frequencies

should be equal. The network which has higher critical frequency than other two networks is called

dominant network. The dominant network determines the frequency at which the overall gains of the

amplifier begin to drop

10. Determine the low frequency response of the amplifier circuit shown in figure. [

APR/MAY-10,11]

Given datas:-

RS = 680 ; R1 = 68 K ; R2 = 22 K .

hie 1.1 K ; C1 = C2 = 0.1F; CE = 10 F.

RC = 2.2K; RL = 10 K ; = 100.

Solution:-

a). Input RC network:-

96

.8.929)(

101.07.10316802

1)(

101.01.1||22||686802

1)(

||||2

1)(

6

6

121

Hzinputf

inputf

KKKinputf

ChRRRinputf

C

C

C

ieS

C

b). Output RC network:-

.45.130)(

101.0102.22

1)(

;2

1)(

6

2

Hzoutputf

KKoutputf

CRRoutputf

C

C

LC

C

C) Bypass RC network:-

7.923)(

101023.172

1)(

10101||100

110028.6532

1)(

28.653680||22||68||||

||2

1)(

6

6

21

bypassf

bypassf

K

bypassf

KKRRRR

CRhR

bypassf

C

C

C

STH

EE

ieTH

C

We have calculated all the three critical frequencies:

a). .8.929)( HzinputfC b). .45.130)( HzoutputfC C). 7.923)( bypassfC

Low frequency response` of the amplifier:-

97

11. What do meant by frequency response of an amplifier? How it is plotted?

98

99

12. Explain about the high frequency of FET.[NOV/DEC-09,12] [ APR/MAY-13]

The output voltage Vo between D and S is given by

Vo =IZ --------------------------------------------------- (1)

Where I= Short-circuit current and

100

Z=impedance between the terminals

Let us calculate Z. To calculate Z, the independent generator Vi is the short-circuited, so that

Vi=0, and hence is no current in the dependent generator gm Vi. Thus, the Z is the parallel

combination of the impedance corresponding to Rl, Cd, rd and Cgd and it is given by

Z=1/Z=YL+Yds+gd+Ygd -----------------------------------------------(2)

Where YL=1/RL : Admittance corresponding to RL

Yds=jCds : Admittance corresponding to Cds

gd =1/rd : Conductance corresponding to rd

Ygd=jCgd : Admittance corresponding to Cgd

The current I in the direction from D to S with output terminals shorted is given by,

I= gm Vi+ Vi Ygd = Vi(-gm+Ygd) ----------------------(3)

101

102

103

104

UNIT-4

105

1) Explain the operation of the transformer coupled class A audio power amplifier

[APR/MAY-10,13] [ NOV/DEC-12]

Class A Power amplifier

The power amplifier is said to be class A amplifier if the Q point and the input signal

are selected such that the output signal is obtained for a full input cycle.

Transformer Coupled class A power amplifiers

In transformer coupled type, the load is coupled to the collector circuit.

The loudspeaker connected to the secondary acts as a load having impedance of

RL ohms.

The transformer used is a step down transformer with the turns ratio as n =

N2/N1.

Circuit Diagram

DC operation

1. Assumed that the winding resistances are zero ohms. Hence for d.c purposes, the

resistance is zero ohms.

2. There is no d. c voltage drop across the primary winding of the transformer.

3. The slope of the d.c load line is reciprocal of the d.c resistance in the collector circuit,

which is zero in this case.

4.Hence slope of the d.c load line is ideally infinite. This tells that the d.c load line in

the ideal condition is a vertically straight line.

5.Applying Kirchoffs voltage law to the collector circuit we get,

VCC VCE = 0

i.e., VCC = VCE drop across winding is zero.

106

This is the d.c bias voltage VCEQ for the transistor.

So,

Hence the d.c load line is a vertical straight line passing through a voltage point on the X-axis

which is VCEQ = VCC.

The intersection of d.c load line and the base current set by the circuit is the quiescent

operating point of the circuit. The corresponding collector current is ICQ.

A.C Operation

1. For the a.c analysis, it is necessary to draw an a.c load line on the output characteristics.

2. For a.c purposes, the load on the secondary is the load impedance RL ohms. And the

reflected load on the primary i.e. RL can be calculated.

3. The load line drawn with a slope of (-1/RL) and passing through the operating point i.e.

quiescent point Q is called a.c load line.

4. The output current i.e. collector current varies around its quiescent value ICQ, when a.c

input signal is applied to the amplifier.

5. The corresponding output voltage also varies sinusoidally around its quiescent value VCEQ

which is VCC in this case.

Load line for class A amplifier

A.C Output Power

The a.c power developed is on the primary side of the transformer.

While calculating this power, the primary values of voltage and current and reflected load

RL must be considered.

The a.c power delivered to the load is on the secondary side of the transformer.

VCEQ = VCC

107

While calculating load voltage, load current, load power the secondary voltage, current and

the load RL must be considered.

Let V1 m = Magnitude or Peak value of primary voltage.

V1 rms = R.M.S value of primary voltage.

I1 m = Peak value of primary current.

I1 rms = R.M.S value of primary current.

Hence the a.c power developed on the primary is given by,

Similarly the a.c power delivered to the load on secondary also can be calculated, using

secondary quantities.

Let V2 m = Magnitude or Peak value of secondary or load voltage.

V2 rms = R.M.S value of secondary or load voltage.

I2 m = Peak value of secondary or load current.

I2 rms = R.M.S value of secondary or load current.

Power delivered on primary

is same as power delivered to the

load on secondary, assuming ideal transformer.

Primary and secondary values of voltages and currents are related to each other through

the turns ratio of the transformer.

108

The slope of the a.c load line can be expressed in terms of the primary current and the

primary voltage. The slope of the a.c load line is, m

m

L V

I

R 1

1

'

1

The generalized expression for a.c power output is given by,

L

PP

acLPP

ac

PPPP

PPPP

mmac

R

VPor

RIPor

WIV

IV

IVP

8)(:

8)(

)........(..........82

22

222

But as VPP = Vmax Vmin and IPP = Imax Imin : Substitute this in equation (W) ,then we get,

Efficiency

The efficiency of an amplifier represents the amount of a.c power delivered

(or) transferred to the load, from the d.c source i.e. accepting the d.c power input. The efficiency of

an amplifier is,

Now for class A operation, we have derived the expressions for Pac and Pdc, hence equations

(1) and (2), we can write

100

8% minmaxminmax

CQCCIV

IIVV

Maximum Efficiency:

For maximum efficiency calculation, assume maximum swings of both the output voltage and the

output current.

8

minmaxminmax IIVVpac

(2)

100% dc

ac

P

P

109

From the graph we can see that the minimum voltage possible is zero and maximum voltage possible

is 2VCC, for a maximum swing.

Similarly the minimum current is zero and the maximum current possible is 2 ICQ, for a maximum

swing.

02

02

minmax

minmax

andIII

andVVV

CQ

CC

for maximum swing

%50%

1008

4%

1008

0202%

1008

% minmaxminmax

CQCC

CCCQ

CQCC

CQCC

CQCC

IV

VI

IV

IV

IV

IIVV

2. Explain the operation of class B push pull amplifier with neat diagram [APR/MAY-

10] [ NOV/DEC-11]

Class B amplifier The Power amplifier is said to be class B amplifier if the Q-point

and the input signal are selected, such that the output signal is obtained only for one half cycle for a

110

full input cycle. Class B amplifies is further classified as Push-Pull and Complementary

symmetry amplifiers.

Push-Pull Class B amplifier

When both the transistors are of same type i.e. either n-p-n (or) p-n-p then the circuit

is called Push-Pull Class B A.F power amplifier circuit.

The push-pull circuit requires two transformers, one as input transformer called

driver transformer and the other to connect the load called output transformer.

The input signal is applied to the primary of the driver transformer. Both the

transformers are centre tapped transformers.

In the circuit, both Q1 and Q2 transistors are of n-p-n type. Both the transistors are in

common emitter configuration.

The driver transformer drives the circuit. The input signal is applied to the primary of

the driver transformer.

The centre tap on the secondary of the driver transformer is grounded. The centre tap

on the primary of the output transformer is connected to the supply voltage +VCC

Circuit Diagram

PUSH-PULL CLASSB AMPLIFIER

With respect to the centre tap, for a positive half cycle of input signal, the point A

shown on the secondary of the driver transformer will be positive.

While the point B will be negative. Thus the voltages in the two halves of the

secondary of the driver transformer will be equal but with opposite polarity.

Hence the input signals applied to the base of the transistors Q1 and Q2 will be

1800 out of phase.

111

The transistor Q1 conducts for the positive half cycle of the input producing positive

half cycle across the load.

While the transistor Q2 conducts for the negative half cycle of the input producing

negative half cycle across the load.

Thus across the load, we get a full cycle for a full input cycle.

When point A is positive, the transistor Q1 gets driven into an active region while

the transistor Q2 is in cut off region.

While when point A is negative, the point B is positive, hence the transistor Q2

gets driven into an active region while the transistor Q1 is in cut off region.

D.C Operation

The d.c biasing point i.e. Q point is adjusted on the X-axis such that VCEQ = VCC

and ICEQ is zero.

Hence the co-ordinates of the Q point are (VCC,0). There is no d.c base bias voltage.

D.C. Power input:

Each transistor output is in the form of half rectified waveform. Hence if Im is the

peak value of the output current of each transistor, the d.c or average value is Im/,

due to half rectified waveform.

The two currents, drawn by the two transistors, forms the d.c supply are in the same

direction.

Hence the total d.c or average current drawn from the supply is the algebraic sum of

the individual average current drawn by each transistor.

The total d.c power input is given by,

mCCDC

dcCCDC

IVP

IVP

2

A.C Operation:

mCCDC IVP

2

mmm

dc

IIII

2

112

When the a.c signal is applied to the driver transformer, for positive half cycle Q1

conducts. The path of the current drawn by the Q1 is shown in fig (a).

For the negative half cycle Q2 conducts. The path of the current drawn by the Q2 is

shown in fig (b).

It can seen that when Q1 conducts, lower half of the primary of the output transformer

does not carry any current. Hence only N1 numbers of turns carry the current.

While when Q2 conducts, upper half of the primary does not carry any current. Hence

again only N1 number of turns carry the current. Hence the reflected load on the

primary can be written as

2

'n

RR LL (1)

Where n = N2 / N1

The step down turns ratio is 2N1:N2 but while calculating the reflected load, the ratio

n becomes N2/N1.Each each transistor shares equal load which is the reflected load

RL given by equation (1).

The slope of the a.c load line is (-1/RL) while the d.c load line is the vertical line

passing through the operating point Q on the axis.

Load Line for push-pull class B amplifier:

113

The slope of the a.c load line (magnitude of slope) can be represented in terms of Vm

and Im as,

m

mL

m

m

L

V

IR

V

I

R

'

'

1

Where Im = Peak value of the collector current.

A.C Power Output:

As Im and Vm are the peak values of the output current and the output

voltage respectively, then

2

.........2

m

rms

m

rms

IIand

VV

Hence the a.c power output is expressed as,

While using peak values it can b expressed as,

Efficiency:

The efficiency of the class B amplifier can be calculated using the basic equation.

)2..(....................1004

%

1002

2100%

CC

m

mCC

mm

DC

ac

V

V

IV

IV

P

P

Maximum Efficiency:

From the equation (2), it is clear that as the peak value of the collector voltage Vm

increases, the efficiency increases. The maximum value of Vm possible is equal to VCC.

L

mLmmmac

R

VRVIVP

'22

'

2

114

Vm = VCC for maximum .

%5.78%

1004

%

1004

%

CC

CC

CC

m

V

V

V

V

`

3. Draw the circuit of a complementary symmetry amplifier and explain its operation.

[APR/MAY-10,11,12] [NOV/DEC-06, 11, 12]

Class B amplifier:-

The Power amplifier is said to be class B amplifier if the Q-point and the input signal are

selected, such that the output signal is obtained only for one half cycle for a full input cycle. Class

B amplifies is further classified as Push-Pull and Complementary symmetry amplifiers.

Complementary Symmetry Class B amplifier:-

When the two transistors form a complementary pair i.e. one n-p-n and other

p-n-p then the circuit is called Complementary symmetry Class B A.F power amplifier circuit

Circuit Diagram:

The circuit is driven from a dual supply of CCV .The transistor Q1 is n-p-n while Q2 is of p-n-p

type.

115

In the positive half cycle of the input signal, the transistor Q1 gets driven into active region and

starts conducting.

The same signal gets applied to the base of the Q2 but as it is of complementary type, remains in

off condition, during positive half cycle. This result into positive half cycle across the load RL.

Circuit Diagram of +ve half Cycle:

During negative half cycle of the signal, the transistor Q2 being p-n-p gets biased into conduction.

While the transistor Q1 gets driven into cut off region. Hence only Q2 conducts during negative half

cycle of the input, producing negative half cycle across the load RL.

Thus for a complete cycle of input, a complete cycle of output signal is developed across the load.

Circuit Diagram of -ve half Cycle:

Advantages:-

1.As the circuit is transformer less, its weight, size and cost are less.

2.Due to common collector configuration, impedance matching is possible.

3.The frequency response improves due to transformer less class B amplifier circuit.

116

Disadvantages:-

1.The circuit needs separate two separate voltage supplies.

2.The output is distorted to cross-over distortion.

4. What is meant by cross over distortion and how it is eliminated? [APR/MAY-12]

[NOV/DEC-09]

[NOV/DEC-06; MAY-2004]

Cross over distortion

In class B mode, both transistors are biased at cut- off region because the DC bias voltage

is zero.

So input signal should exceed the barrier voltage to make the transistor conduct. Otherwise

the transistor doesnt conduct.

So there is a time interval between positive and negative alternations of the input signal

when neither transistor is conducting. The resulting distortion in the output signal is crossover

distortion.

Cross over Distortion

To eliminate the cross-over distortion some modifications are necessary.

The basic reason for the cross over distortion is the cut in voltage of the transistor junction.

To overcome this cut-in voltage, a small forward biased is applied to the transistors.

Class B with Voltage Divider Bias

117

In complementary symmetry circuit, base emitter junctions of both Q1 and Q2, are

required to provide a fixed bias.

Hence for silicon transistors a fixed bias of 0.7 + 0.7 = 1.4 V is required. This can be

achieved by using a potential divider arrangement.

But in this circuit, the fixed bias provided is fixed to say 1.4 V. While the junction cut-

in voltage changes with respect to the temperature. Hence there is still possibility of a distortion

when there is temperature change.

Class B with two diodes

:

Hence instead of R2, the two diodes can be used to provide the required fixed bias.

As the temperature changes, along with the junction characteristics get changed and maintain the

necessary biasing required to overcome the cross-over distortion when there is temperature

change.

5. Discuss the class D power amplifiers and derive its efficiency.

118

Class D amplifier or switching amplifier is an electronic amplifier where all

power devices (usually MOSFETs) are operated as binary switches. They are either fully on or

fully off. Ideally, zero time is spent transitioning between those two state.

Concept of Class D ampliifer:

119

Block Diagram of Class D amplifier:

120

Ideal Performance of class D amplifier

The transistor Q1 and Q2 acts as switches

hence when Q1 is ON, Q2 is OFF and when Q2 is

ON, Q1 is OFF. Consider Q1 is ON and Q2 OFF.

Thus voltage across Q1 is zero and equivalent circuit

is shown in fig. If input is square wave then voltage

Va is square wave at the input to the series tuned

circuit as shown in the fig.

The square wave signal Va can be expressed in a Fourier series and amplitude of the

fundamental component is given by,

CCm VV

41

Hence the fundamental component can be expressed as,

tVtVv CCm

sin4

sin11

The fundamental component of current by

11

1 4sinCC

L L

vi V t

R R

Thus average DC drain current ID is given by,

2

0

1 1 4sin

T

D CC

L

I V t d tR T

2

0

4 1 cosT

ccD

L

V tI

R T

121

4 1 cos1

2

ccD

L

V TI

R T

2

4 1 42

2

cc ccD

L L

V VI

R R

2

2

82 CCDC CC D

L

VP V I

R

And

2

2 I

2

mac RMS L LP I R R

Where 4

I ccmL

V

R

22

2 2

4 1 16

2 2

cc CCLac

L L

V VRP

R R

2

2

8 CCDC ac

L

VP P

R

The PDC is input while Pac is output power.

Non Ideal Performance of class D amplifier:

Practically BJT when ON has a drop of VCE (sat) across it

while practically FET has a resistance RON when it is ON.

Hence any replaced by ideal short circuit.

The figure shows an equivalent circuit with FET represented by RON when saturated. If the Vin is

square wave, the input to the tuned circuit Va is also square wave, but with reduced amplitude. The

output voltage assuming a narrow band filter is given by

122

0

4sinLCC

L ON

RV V t

R R

The amplitude of the output current is given by

01

4 1ccm

L L ON

V VI

R R R

The DC current in each transistor is,

2

4 1ccD

L ON

VI

R R

PDC input power=2VCCID

2

2

8 CCDC

L ON

VP

R R

Pac output power=I2rms RL

2 2 2

1

22

4

2 2

m CCac L L

L ON

I VP R R

R R

2

2

8 CCac L

L ON

VP R

R R

Thus the efficiency of non-ideal class D FET amplifier is

% 100L

L ON

R

R R

6. Explain the MOSFET power amplifiers. [NOV/DEC-09]

Power amplifier designed to switch large currents ON and OFF use MOSFET devices.

MOSFET based class-D amplifier is commonly employed. Other applications include line drivers

for digital switching circuits, switched mode voltage regulators. The advantage of using MOSFET

device for switching is the turn off time is not delayed by minority-carrier storage, as it is in a

123

BJT. Further current in a MOSFET is due to majority carriers only and they are not subjected to

thermal runaway. In addition, very large input impedance of MOSFET, makes the designed of

drivers circuits less complex.

Complementary Symmetry MOSFET amplifier with Single Power Supply:

During the positive half cycle, current flows through Q1, C1 and RL causing the left side of

C1 to charge positive. During the negative half cycle, Q2 is turned on and C1 discharge through Q2

and load.

Circuit Diagram:

This causes current to flow through the load in the opposite direction. This process is

repeatly. In this type of the circuit the capacitor must be

large enough to supply energy to the load during the

negative half cycle. These capacitors range is thousands of

microfarads

MOSFET based class D power amplifier:

In class D amplifier, transistor is used as switch

instead of current sources. When transistor is operated as

switch, the power dissipation is ideally zero and hence the

efficiency of class D amplifiers approaches 100%.

The figure shows the class D amplifier using

MOSFETs. Hear MOSFETs are switched ON and OFF, so

that they are held in a linear range for essentially zero time during each cy