ece 3450 m. a. jupina, vu, 2012 overview of digital logic technologies fpld technologies altera...

ECE 3450 M. A. Jupina, VU, 2012

Overview of Digital Logic Technologies FPLD Technologies Altera DE2 Development Board Hardware Description Languages Quartus II Software and Tutorial

Field Programmable Logic Devices (FPLDs)

Some Key Lecture Objectives

A discussion of how digital logic circuits can be implemented through various technologies (Discrete vs PLD vs ASIC vs Full Custom).

Understand how FPLD technology is implemented by briefly looking at CPLD and FPGA architectures.

Understand the advantages of FPLD technology. An overview of the Altera DE2 board and the Quartus II software. Course

projects will use the Altera FPLD boards as a platform to implement complicated digital systems. With the Quartus II software, you will use a system design approach to create your designs.

A brief (very brief) discussion of VHDL and the future of VHDL-AMS and mixed signal ICs.

References:1. Fundamentals of Digital Logic, Sections 2.9, 2.10, 3.5 – 3.7, and Appendices A-E.2. Document files at the course web site


Digital Logic Technologies

Full Custom

Standard Logic

Progammable Logic (FPLDs) ASICs

Digital Logic

TTL 74xx

CMOS 4xxx

PLDs FPGAs

Gate Arrays

Microprocessor & RAM

Standard Cell

CPLDs


A 7400-Series Chip

Dual-inline package Structure of 7404 chip

V DD

Gnd


VDD

x 1 x 2 x 3

f

7404

7408 7432

Discrete Implementation Example

1 2 2 3 f = x x + x x


General Structure of a PLA

f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n


An Exampleof a PLA

f 1

P 1

P 2

f 2

x 1 x 2 x 3

OR plane

AND plane

P 3

P 4

1 1 2 1 3 1 2 3

2 1 2 1 2 3 1 3

f x x x x x x x

f x x x x x x x



An Exampleof a PAL

f 1

P 1

P 2

f 2

x 1 x 2 x 3

AND plane

P 3

P 4

1 1 2 3 1 2 3

2 1 2 1 2 3

f x x x x x x

f x x x x x

Structure of a CPLD

PAL-likeblock

I/O

blo

ck

PAL-likeblock

I/O b

lock

PAL-likeblock

I/O

blo

ck

PAL-likeblock

I/O b

lock

Interconnection wires


A Section of a CPLD

D Q

D Q

D Q

PAL-like block (details not shown)

PAL-like block


Structure of a FPGA


Logic Block Example

A two-input lookup table

(a) Circuit for a two-input LUT

x 1

x 2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x 1 x 2

(b) f 1 x 1 x 2 x 1 x 2 + =

(c) Storage cell contents in the LUT

x 1

x 2

1

0

0

1

f 1

f 1

Out

D Q

Clock

Select

Flip-flop In1

In2

In3

LUT

Complete Logic Block


A Sea-of-Gates Gate Array


An Example of a Logic Function in a Gate Arrayf 1

x 1

x 3

x 2

1 2 3 1 3 f = x x + x x


A Simplified Floor Plan of a Standard Cells Based Design


Standard Cell Structure

VDD

VSS

n tub

p tub orsubstrate

Intra-cell wiring

pullups

pulldowns

All cells have same pitch (height), may have different widths.

VDD, VSS (ground) connections are designed to run through cells.

A feedthrough area may allow wires to be routed over the cell.


Example: Full Adder Schematic

Two Outputs: Sum and Carry

sum

carry

x1

x2

n1

n2

n3

n4


A Candidate Layout of a Full Adder

x1 x2 n1 n2 n3 n4

a

b

c s

co

Density = 5


Layout of Full Adder Cell

XOR XOR NAND NAND NAND NAND (2) (2) (2) (2) (2) (3)


Intel Pentium (IV) Microprocessor

200142 million transistors2 GHz clock


Emerging Chip Architecture

IPCORE

FPLD Circuits

Silicon Chip


Example of a System-on-a-Chip (SOC) Architecture

System-on-a-Programmable Chip (SOPC) NOW EMERGING!


Digital Logic Technology Tradeoff

PLDs

ASICs

Full CustomVLSI Design

Speed,Density,Complexity,MarketVolumeneeded forProduct

Engineering Cost, Time to Develop Product

CPLDsFPGAs


Comparison of Digital Technologies


FPLD Advantages1. Re-configurable: The IC can be configured or “wired” to perform a particular

task at a given instance in time and then reconfigured or “rewired” to perform another task a moment later. For example, the IC could be used as a low pass FIR digital filter one moment then reconfigured as a band pass FIR filter the next moment.

2. Rapid Prototyping

3. FPGA to ASIC Design (Example: Altera Stratix II to HardCopy II)

http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp?f=hc2hp&k=m1

FPLD

ROM

ROM

ROM

ROM


http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp?f=hc2hp&k=m1

• Complexity of Logic Element

– How many inputs/outputs for the logic element?

– Does the basic logic element contain a FF? What type?

• Interconnect

– How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of these?

– Can I have on-chip tri-state busses?

– How routable is the design? If 95% of the logic elements are used, can I route the design?

More routing means more “route-ability,” but less room for logic elements

Issues in FPLD Technologies


• Macro elements

– Are there SRAM blocks? Is the SRAM dual ported?

– Is there fast adder support (i.e. fast carry chains?)

– Is there fast logic support (i.e. cascade chains)

– What other types of macro blocks are available (fast decoders? register files? )

• Clock support

– How many global clocks can I have?

– Are there any on-chip Phase Locked Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication?

Issues in FPLD Technologies Continued


• What type of I/O support exists?

– TTL, CMOS are a given

– Support for mixed 5V, 3.3V I/Os?

• 3.3 v internal, but 5V tolerant inputs?

– Support for new low voltage signaling standards?

• GTL (Gunning Transceiver Logic) - used on Pentium II

• HSTL - High Speed Transceiver Logic

• SSTL - Stub Series-Terminate Logic

• USB - Universal Serial Bus (differential signaling)

• AGP - Advanced Graphics Port

– Maximum number of I/O? Package types?

Ball Grid Array (BGA) for high density I/O

Issues in FPLD Technologies Continued

(bottom view)


Examples of FPLDs and Advanced High Pin Count Package Types

PLCC PQFP Ceramic PGA


• Altera Max7000/Max7000A

– EEPROM based, very fast (tp = 7.5 ns)

– Basically a PLD architecture with programmable interconnect.

– Max 7000A family is 3.3 V

• Altera Flex10K/10KE

– LEs (Logic elements) have 4-input LUTS (look-up tables) and 1 FF

– Fast Carry Chain between LE’s and Cascade chain for logic operations

– Large blocks of SRAM available as well

Altera FPLD Family Summaries


MAX 7000 Macrocell

(36 signals from PIA)

(16 inputs)

Output can befed back to input for state machine implementation


MAX 7000 LAB and PIA


MAX 7000 CPLD Architecture


FLEX 10K LE


FLEX 10K LAB and Interconnects


8-Bit Parallel Adder Example


Product Term of Eight Variables Example


FLEX 10K FPGA Architecture


The Altera DE2 Development Board


In-System Programming of the Altera Development Board


Connections Between the Pushbuttons, the LEDs, and the Altera FPGA

Figure 1.6 FPGA I/O connections to Pushbuttons (PBx) and LED: Right of center, active LOW LED

output (i.e., UP1 and UP2 boards) or on far right active HIGH LED output (i.e., DE1, DE2, and UP3

boards). Note that a depressed pushbutton input will be LOW.


9V DC PowerSupply

Connector

27Mhz Oscillator24-bit Audio CODEC

TV Decoder(NTSC/PAL)

PowerON/OFFSwitch USB

Host/SlaveController

Altera USB BlasterController Chipset

Altera EPCS 16Configuration Device

RUN/PROGSwitch forJTAG/AS

Modes

LCD 16x2 Module

7-SEG Display Module

18 Red LEDs

18 Toggle Switches

1MB FlashMemory

(upgradable to4MB)

PS/2 Port

XSGA10-bit DAC

Ethernet 10/100MController

SD Card Connector

IrDATransceiver8 Green LEDs

SMAExtClk

4 Push-button Switches

90nmCyclone IIFPGA with35K LEs

RS-232Port

Ethernet10/100M Port

XSGAVideo Port

VideoIn

USBHost

LineIn

MicOut

MicInUSB

Device

USBBlaster

Port

50Mhz Oscillator

8MB SDRAM

512KB SRAM

88888888

Figure 1.16 Altera DE2 board showing the Pushbutton and LED locations used in design (enclosed

in dashed ellipses seen in bottom right).


Examples of Dedicated Pin-Outs on the DE2 Cyclone II Chip

Table 1.2 Hardwired I/O connections on the various FPGA boards in the design example.

I/O Device DE1 Pin DE2 Pin UP3 Pin UP2 & 1 Pin

PB1 R21 (Key1) N23 (Key1) 62 (SW7) 28 (FLEX PB1)

PB2 T22 (Key2) P23 (Key2) 48 (SW4) 29 (FLEX PB2)

LED R20(LEDR0) AE23(LEDR0) 56 (D3) 14 (7Seg Dec. pt.)


Logic Synthesis: convert a description of a digital system in a Hardware Description Language (HDL) to an implementation technology.

library ieee;use ieee.std_logic_1164.all;

entity majority is port ( A, B, C : in std_logic; Y: out std_logic );end majority;

ARCHITECTURE a of majority is

begin

Y <= (A and B) or (A and C) or (B and C);end a;

HDL description Gates

Synthesis

Logic Synthesis


• VHDL is a language used for simulation and synthesis of digital logic.

• A VHDL description of a digital system can be transformed into a gate level implementation. This process is know as synthesis.

VHDL for Combinational Logic


• VHDL has a reputation as a complex language (it is!)• We will use a small subset of the language for our

purposes• Some VHDL constructs:

– Signal Assignment: A <= B;– Comparisons = (equal), > (greater than), < (less

than), etc.– Boolean operations AND, OR, NOT, XOR– Sequential statements (CASE, IF, FOR)– Concurrent statements (when-else)

VHDL Statements


• Every VHDL model is composed of an entity and at least one architecture .

• Entity describes the interface to the model (inputs, outputs)

• Architecture describes the behavior of the model

• Can have multiple architectures for one entity (we will only use one in this class).

VHDL Combinational Template


entity model_name is port ( list of inputs and outputs ); end model_name; architecture arch_name of model_name is begin concurrent statement 1 concurrent statement 2 ... concurrent statement N;

end arch_name;

All of the text not in italics are VHDL keywords. VHDL is NOT case sensitive. (ENTITY is same as entity is same as EnTiTy).

A VHDL Template for Combinational Logic


library ieee;use ieee.std_logic_1164.all;

entity example is port ( A, B, C : in std_logic; Y: out std_logic );end example;

-- this is the architecture declaration, uses only -- one concurrent statement.

ARCHITECTURE a of example is

begin

Y <= (A and B) or (A and C) or (B and C);end a;

Description Implementation

A VHDL Example of an XOR Gate


Analog and Mixed Signal VHDL (VHDL-AMS)

• The IEEE 1076.1 language (VHDL-AMS) is a superset of the IEEE Std 1076-1993 (VHDL) that provides capabilities for describing and simulating analog and mixed-signal systems.

• VHDL-AMS was developed to provide the industry with a high-level design language to master future challenges in both mixed digital and analog system design as well as multi-physics applications.

• Currently, VHDL-AMS provides simulation only. Future software could provide synthesis. For example, field-programmable analog arrays (FPAA) are being developed. A FPAA containing many (~20) analog function blocks could be configured as DC level shifters, rectifiers, amplifiers, filters, oscillators, comparators, equalizers, etc.


FPAA Reconfiguration Example

While FPAA technology is very young, and still expensive, it could someday be useful for creating communications products that would work on any standard.

For instance, a cell phone with a re-programmable analog-to-digital converter would search the entire communications band for a signal, then grab the necessary program from memory to make itself into a code-division multiple access (CDMA), time-division multiple access (TDMA), or global system for mobile communications (GSM) phone. Such a phone could be used in Japan, Europe, or the US without modification.


VHDL-AMS Code Example-- VHDL-AMS model of an Analog Schmitt Trigger -- Description -- This Schmitt trigger uses a signal to model a simple hysteresis -- loop. When the input voltage exceeds the high threshold, the internal -- state switches to 5 Volts and when the input drops below the low threshold, -- the state switches to 0 Volts. -- The output is an ideal voltage source which contributes to the output -- terminal OutTerminal. -- LIBRARY DISCIPLINES;LIBRARY IEEE;

USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM.ALL;USE IEEE.MATH_REAL.ALL;

entity AnalogSchmitt is end entity AnalogSchmitt;

architecture Hysteresis of AnalogSchmitt is TERMINAL n1,n2 : ELECTRICAL;


VHDL-AMS Example Continued-- declare a signal to memorize the hysteresis state: SIGNAL State : REAL := 0.0; -- initial state is low QUANTITY vin ACROSS iin THROUGH n1;

-- declare a through branch for the output voltage source quantity vout across iout through n2;

begin -- the architecture consists of two architecture statements: -- a conditional concurrent signal assignment to implement the hysteresis -- a simultaneous statement to implement the equation for the output source vin == 5.0 * sin(2.0 * math_pi*0.5E3*NOW);

-- hysteresis: break State => 0.0 when Vin'above(1.0); -- trigger event when Vin > 1.0 break State => 5.0 when not Vin'above(2.4); -- trigger event when Vin < 2.4

-- output voltage source equation: vout == State'Ramp(1.0e-9,1.0e-9); -- the use of ramp assures that when a discontinuity -- in State arises, it is announced to the simulator end architecture Hysteresis;


Altera Quartus II Software


Required Installation of Quartus II on Laptops Go to the Altera folder on the K:\ Drive. Download

the executable file 91_quartus_free to your laptop’s hard drive. Install the Quartus II software.

After Installation, run the Quartus II software. Go to the menu Tools, License Setup, and in the box for License File put the following [email protected] so that your laptop can find the license on the ECE server.


Design Process for Schematic or VHDL Entry


Create/Edit Schematic/VHDL

Compilerrepeat until no errors

Create Simulation Waveforms

SimulatorRun simulation until functionally correct

Timing Analysis?Modify design until timing specs are met

Program Device

Design Implementation Methodology


Creating a New Quartus II Project


Setting the FPGA Device Type

The Cyclone II Chip resides on the DE2 Board.

Figure 1.9 Setting the FPGA Device Type. Settings shown are for the DE1 board.

DE2

Cyclone II

EP2C35F672C6


Creating the Top-Level Project Schematic Design File


Selecting a New Symbol with the Symbol Tool


Active Low OR-Gate Schematic Example with I/O Pins Connected


Assigning Pins with the Assignment Editor


Active Low OR-Gate Timing Simulation with Time Delays


VHDL Entity Declaration Text


VHDL OR-Gate Model (with Syntax Error)


VHDL Compilation with a Syntax Error


Timing Analyzer Showing Input to Output Timing Delays


Floorplan View Showing Internal FPGA Placement of OR-

Gate in LE and I/O Pins


ORgate Design Symbol

orgate

inst

PB1PB1

PB2PB2

LEDLED


Implementation of a Simple Processor

Data

IEA IEB IECClock

RA RB RC IEX RX

Multiplexer

SY

SDATA

SA

SC SB

ALU

IEY RY

StateMachine

IEA IEB IEC

SC

SDATA

SA

SB

Done

IEX IEY

AddSub SY

Bus

AddSub

Start


Altera Implementation of Simple Processor


An Example Design Illustrating the Mapping of Multi-Bit Connections


An Example with a LPM Device


Lpm_counter0 MegaWizard Edit Window


ece 3450 m. a. jupina, vu, 2012 overview of digital logic technologies fpld technologies altera...

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