ece 352 winter 2007 bipolar digital pt. 4 1 voltage transfer characteristic for ttl *summary of...

Bipolar Digital Pt. 4 1ECE 352 Winter 2007

Voltage Transfer Characteristic for TTL

* Summary of transfer characteristic When the input is low,

The current iR goes out the E of Q1

So Q2 and Q3 get no base current and are off

So the output is high When the input increases,

Some of iR gets directed into the B of Q2, so Q2 gets some base current and comes on in active mode

C current of Q2 increases, so IR drop across R1 increases and output voltage drops (B to C)

As Q2 comes on, it provides base current to Q3 and Q3 come on in active mode (C).

When the input increases further, More of iR gets directed into the C of Q1, so

Q2 gets more base current and moves into the saturation mode (C to D)

Q2 provides more base current to Q3 and then Q3 moves into saturation mode (D).

Further increases in the input direct all of iR into the C of Q1, so Q2 gets even more base current and moves deeper into the saturation mode (D to E). Similarly, Q3 moves deeper into saturation.

vi

+_

vi

voA B

0

VOH =3.7 V

VCC = 5 V

0.5V 1.2V 1.4V 3.7 VVIL VIH

C2.7 V

DVOL=0.1 V

III

III

EIV

iR

R3 =0.13 K

Q2 comes on

Q3 comes on, Q2 heads towards saturation

Q3 reaches saturation, Q2 already in saturationQ1 comes out of saturation

Q1 in saturation, Q2 and Q3 off


Voltage Transfer Characteristic for TTL* Noise Margins

Noise Margin for low state NML = VIL -VOL

VOL = low output voltage for typical high input voltage = 0.1 V

VIL= maximum input voltage recognized as a low input = 0.5 V

NML = VIL-VOL =0.5 V - 0.1 V = 0.4 V

Noise Margin for high state NMH = VOH -VIH

VOH = high output voltage for typical low input voltage = 3.7 V

VIH= minimum input voltage recognized as a high input = 1.4 V

NMH = VOH -VIH = 3.7 V - 1.4V = 2.3 V

Noise margins are very unequal for this technology.

vi

+_

vi

voA B

0

VOH =3.7 V

VCC = 5 V

0.5V 1.2V 1.4V 3.7 VVIL VIH

C2.7 V

DVOL=0.1 V

III

III

E

IV

iR

NMHNML

vo


Comparison of Simplified TTL and TTL

* Noise Margin (Low state) NML = VOL - VIL = 0.6V - 0.1 V = 0.5 V

* Noise Margin (High state) NMH = VOH - VIH = 5 V - 0.7 V = 4.3 V

vo

VCC = 5V

VCC = 5V

R=4K

vi

vo

0.6 V 0.7V 5 V

VCC = 5VBA

C0.2V0.1V

I II

D

III

RC =1.6K

+

vi

voA B

0

C2.7 V

DVOL=0.1 V

III

III

E

IV

NMHNML

3.7 V

VOL=0.1 V

0.5V 1.2V 1.4V 3.7 VVIL VIH

* Noise Margin (Low state) NML = VOL - VIL = 0.5V - 0.1 V = 0.4 V

* Noise Margin (High state) NMH = VOH - VIH = 3.7 V – 1.4 V = 2.3 V

NMLNMH


Voltage Transfer Characteristic for TTL* What is the function of Q4?

Q4 is weakly on but producing little current when the output is low.

This helps to minimize power dissipation since Q3 is on and in saturation so ready to conduct current.

Q4 is weakly on when the output is high.

This is because the following gate has a reverse biased E junction for Q1 and so draws almost no current.

The reason Q4 is included in the circuit is to provide a large current to ensure a fast transition time when the output is going from low to high so tPLH is small.

At all other times we want Q4 off (or only weakly on) to minimize power dissipation.

A simple resistor in place of Q4 gives a very long rise time ~ 100’s nsec, as we saw for the RTL inverter, so the use of Q4 and the diode D is an improvement.

vi

+_

vi

voA B

0

VOH =3.7 V

VCC = 5 V

0.5V 1.2V 1.4V 3.7 VVIL VIH

C2.7 V

DVOL=0.1 V

III

III

EIV

iR

vo


Transistor - Transistor Logic (TTL)

+vo

+

_sat

* What is the ability (fan-out) of the TTL logic to drive simultaneously a number of subsequent inverters?

* Fan-out = NMax = maximum number of subsequent inverters that can be simultaneously driven (connected to the output).

* For the output high, i.e. vo = 3.7 V, the output is connected to a reverse biased E junction for Q1 for each subsequent inverter, so current load is very small.

* However, for output low, i.e. vo = 0.1 V E junction of each Q1 forward biased, so

So this adds to the collector current of Q3 so iC3 = N iE1 = N (1.0 mA)

Fan-out limit = maximum value of N In saturation, iC3 < β iB3

In active, iC3 = β iB3

So limit is when Q3 comes out of saturation into active mode and iC3 = β iB3.

VCC = 5 V

np

mAK

VVV

R

VVVi satCEBECCE 0.1

4

1.07.05,311

iE1 =1 mAiC3

VCE3

+

_

240.1

24

24)4.2(10

for maximum then the,10For

4.2

1

3max

33

3

3

mA

mA

i

iN

mAmAii

isi

mAi

E

MaxC

BMaxC

C

B

Recall, we found when the output was low

R3 =0.13 K

Fan – Out Capability

Fan-out limt

iRi

= 1 mA


TTL Propagation Delay

* Output going high Input goes low Transistors Q2 and Q3 turn off (cutoff) due to low input to gate. Large charging current flows through Q4 to charge up C. Q4 called pull-up transistor Charging time is small ~ 1 nsec tPLH is the time it takes the output to rise from V OL

= VCE,sat = 0.1 V to 1/2(VOH + VOL) = ½(3.7+0.1) V = 1.9 V

Cvo+

iCap

t

vo

VOH=3.7V

VCE,sat

= 0.1 VGoesoff

Goeson

Goesoff

iB4

iC4

iE4

iR

Goes low Goes

hightPLH

1.9V

Output going high



* Charging current for capacitor is emitter current of Q4.

At outset, vo= VCE,sat = 0.1 V, so iB4 and VCE4 are initially large

Charging current iCap ≈ iE4 is large since for = 10

As vo rises, iB4 decreases, so iE4 = iCap

decreases, but Q4 stays in active mode. At vo = 1.9V

So iE4 = iC has decreased to

So capacitor charging current is not constant and calculation of tPLH is more difficult.

Cvo

Goes high

P

R

S

iB4iC4

iE4

t

VOH=3.7V

tPLH

VOH=0.1V

iCap mAK

V

K

VV

K

vVVVi

vVViKV

oB

DBEB

1.26.1

5.3

6.1

1.06.3

6.1

7.07.05

6.15

4

044

mAmAiii BECap 23)1.2(11)1( 44

mAK

V

K

VVVVi

vVViKV

B

DBEB

1.16.1

7.1

6.1

9.17.07.05

6.15

4

044

mAmAiii BEC 12)1.1(11)1( 44

1.9V

Output going high

vo

iC4

vCE4



* Approximating the charging current for capacitor as a constant (average value),

* We can calculate the propagation delay tPLH using

Cvo

Goes high

P

R

S

iB4iC4

iE4

t

VOH=3.7V

VOH=0.2V

iCap

mAmAmAii ECap 182/)2312(4

44

4

OL

44

4

8.11.09.1

1.09.1

9.1 to0.1V V from rise output tofor time

1.0

thencurrent, chargingconstant a Assuming

EEPLH

PLHE

oPLH

EEOLo

Eo

Cap

i

VC

i

VVCt

tC

iVV

Vvt

tC

iVt

C

iVtv

idt

dvCi

sec0.118

8.110

8.1

get we10For

4

nmA

VpF

i

VCt

pFC

EPLH

tPLH

vo

iC4

vCE4

Output going high

So Q4 provides a large charging current to reduce the rise time for the output going

high.



* Output going low Input goes high Transistors Q2 and Q3 turn on (first in active then saturation) as

iR is redirected from the input into the base of Q2

Q4 is turned off as VB4 = VCC – iR1 R1 decreases since iR1≈ iC2. Large discharge current flows through Q3

Q3 called pull-down transistor Discharge time is small ~ 1 nsec tPHL is time it takes the output to fall from VOH = 3.7 V to 1/2(VOH +

VOL) = ½(3.7+0.1) V = 1.9 V

Cvo+

iCap

t

vo

VOH = 3.7V

Goesoff

Goeson

Goeson

iC3iB3

iB2

Goes high

Goes low

tPHL

1.9V

Output going low

iR

iR1

VCE,sat

= 0.1 V



vo

+iCap

t

voVCC=5V

P

RS

iC3

What current to use for the transistor?

off

on

onGoes high

iE4=0

VOH = 3.7V

CCPHL

PHLC

oPHL

CCOHo

Co

Cap

i

VC

i

VVCt

tC

iVV

Vvt

tC

iVt

C

iVtv

idt

dvCi

8.19.17.3

7.39.1

9.1 to3.7V V from fall output tofor time

7.3

thencurrent, dischargeconstant a Assuming

OH

tPHL

1.9V

iB3

sec75.024

8.110

8.1

get we10for so

24)4.2(10

,10and activein intially for 4.2

33

33

nmA

VpF

i

VCt

pFC

mAmAii

QmAi

CPHL

BC

B

Output going low

iB2

iR

iC3

vCE3

VCE,sat

= 0.1 V


Power Dissipation for Transistor - Transistor Logic (TTL)

vi =3.7V

+

_

iR

iR1

sat

sat

* For input high and output low. Q2 and Q3 are in SATURATION.

Since Q2 is in saturation mode, iC2 < β iB2 but VCE2 = 0.2 V and

Q4 is weakly on, iC4 ≈ 0.

Power dissipation

io

mAK

VV

R

VVi

andVVV

BCCR

B

65.04

4.25

4.2)8.0(3

1

1

1

VCC = 5 V

low

np

VVVV BEBEBC 8.0321

VVVVVV CEBEC 0.12.08.0232

mAK

VV

R

VVi CCCR 5.2

6.1

15

1

21

R3 =0.13 K

iC4=0

mW

mAmAV

iiVP RRCCL

8.15

)5.265.0(5

)( 1

VB1 VC2


Power Dissipation for Transistor - Transistor Logic (TTL)

+

_

iR

iR1=0

off

off

* For input low and output high. Q2 and Q3 are off, iC2 ≈ 0, iC3 ≈ 0. Q4 is weakly on, iC4 ≈ 0. iR1 ≈ 0. Q1 is on so VBE1 = 0.7 V

Power dissipation

Average Power Dissipation

Power Delay Product

io≈ 0

mAK

VV

R

VVi

VVVVVV

BCCR

satCEBEB

0.14

9.05

9.07.02.0

1

1

,11

VCC = 5 V

Low =0.2V

np

R3 =0.13 K

iC4=0

mWmAViVP RCCH 0.5)0.1(5)( high

mWPPP HL 4.10)58.15(2/1)(2/1

pJn

mWPtDP P 92

sec)75.00.1()4.10(

VB1


TTL vs. Simplified TTL

* Logic levels and noise margins Noise Margin for Low State

NML = VIL – VO = 0.6 V - 0.1 V = 0.5V

Noise Margin for High State NMH = VOH - VIH = 5 V - 0.7 V = 4.3 V

Unequal noise margins for high and low states.

* Propagation delays Output going low Output going high Propagation delay

* Power – Delay Product

sec16 ntPLH sec55.0 ntPHL

pJmWnPtDP P 1023.12sec3.8

sec3.8 ntP

* Logic levels and noise margins Noise Margin for Low State

NML = VIL – VO = 0.5 V - 0.1 V = 0.4 V Noise Margin for High State

NMH = VOH - VIH = 3.7 V – 1.4 V = 2.3 V Unequal noise margins for high and low states.

* Propagation delays Output going low Output going high Propagation delay

* Power – Delay Product

sec1 ntPLH sec75.0 ntPHL

pJmWnPtDP P 94.10sec9.0

sec9.0 ntP

vivo vi

vo


TTL Summary* Advantages:

Fast switching times, ~ 1 nsec. Low power-delay product (~ 10 pJ) Good fan-out capability Adequate noise margins

* Disadvantages: Static power dissipation, higher

than CMOS Complexity – four transistors Time delay due to saturating

transistors. Small noise margin for low state,

e.g. 0.4 V.


Comparison of Digital Logic Families

* J. Millman and A. Grabel, Microelectronics, McGraw Hill, p. 261 (1987).

vi

vo


TTL Gates


Schottky TTL Gates

* Schottky diode clamp prevents transistors from going deep into saturation.

* Reduces transistor switching time.* Reduces propagation delay, e.g. from

~ few nsec to < 1 nsec.* Power-delay product is not reduced

due to lower resistances used. * Low power version of Schottky TTL

has DP ~ 4 pJ.



Power delay product = a constant


Emitter-Coupled Logic (ECL)

* Sub nsec propagation delay (fastest of bipolar technologies).

* 40 mW/gate power dissipation (high).

* Power delay product = 30 pJ.* Noise margins nearly equal, ~ 0.15 V* High fan-out capability.


BiCMOS

Basic Inverter Advanced Inverter Two input NAND Gate

ece 352 winter 2007 bipolar digital pt. 4 1 voltage transfer characteristic for ttl *summary of...

Documents