ECE 353Introduction to Microprocessor Systems

Michael G. Morrow, P.E.

Final Exam Review

Final Exam InfoHeld on Wednesday, May 16th, at 12:25pm in room 2255EH.Exam is 2 hours Two 3x5 cards Calculators are permitted for numeric

calculations. ~35% on Module 7

serial communications, analog signals ~65% cumulative over course

timing, I/O devices, interrupts, etc. Emphasis will be on conceptual

comprehension

Review - Timing Problem #1

Assume we have the system shown here.The SRAM requires that the address must be valid for at least 40ns before /CS is asserted on a write.Assume the following - ADuC7026 with 40MHz external clock (T = 25ns) tDECODERmin = 5ns, tDECODERmax = 15ns tLATCHmin = 3ns, tLATCHmax = 8ns

Draw only the waveforms of interest on the handout, and write the inequality. write cycle - write parameters - write control

Is the device compatible? If the device was not compatible, what are our options?

Review - Timing Problem #2

Assume we have the system shown here.What is the worst-case SRAM data setup time (tWDS) requirement that we can support while keeping the total write cycle time to 150ns or less? (Assume all other timing has been met.)Assume the following - ADuC7026 with 40MHz external clock (T = 25ns) tDECODERmin = 5ns, tDECODERmax = 15ns tLATCHmin = 3ns, tLATCHmax = 8ns

Draw only the waveforms of interest on the handout, and write the inequality. write cycle - write parameters - write control

Review - Timing Problem #3Assume we have the system shown here.The SRAM requires that the address be stable for at least 45ns after the /WE pin is negated. Assume that there is no delay between consecutive writes (i.e. /MSx remains asserted), and a one clock delay if a read follows the write.Assume the following -

ADuC7026 with 40MHz external clock (T = 25ns) tDECODERmin = 5ns, tDECODERmax = 15ns tLATCHmin = 3ns, tLATCHmax = 8ns

Draw only the waveforms of interest on the handout, and write the inequality.

read cycle - read parameters - read control write cycle - write parameters - write control consecutive write cycles

Is the device compatible? If the device is not compatible, what are our options?

ReviewWhat is an address boundary?In regards to decoding, why do we care about boundaries?What is the difference between memory-mapped I/O and isolated I/O? What are the main signal groups you would expect to find on a parallel system bus?

ReviewWhy does the assembler need IMPORT/EXPORT directives? What effect do they have?What addressing mode does the instruction LDR R0, label imply?How is the instruction LDR R0, label encoded? What limits are there on label?Why can’t the ADR pseudo-instruction work across AREA boundaries?

Review SessionIn a processor with vectored interrupts, a timer interrupt is typically cleared automatically. In the ADuC7026, we had to do it in software. Why is this?If you were designing transmitter and receiver logic for a serial port, how different would it be for synchronous communication versus asynchronous communication? Consider the transmitter. Consider the receiver.

ReviewCreate a look-up table to convert the values 0-9 to a pointer to the respective ASCIIZ equivalent strings (i.e. 4 converts to the address of a string “four”)Write a code fragment to access the LUT.What are the limitations on the LUT size?What are the limitations on the size of the LUT elements?When is it advantageous to use an LUT?

ReviewWhat is a jump table? How is it used?What are the advantages of using a stack frame?Can register passing schemes be reentrant?Why do many compilers use a combination of register passing and stack frames?What is the difference between unpacked and packed BCD?

ReviewWhat safeguards are necessary to safely implement battery-backed NV-SRAM?What is the primary function of a reset circuit?Why do RAMs typically implement two-level decoding?How are the memory device signals (address, data, /CS, /WE, /OE) managed when creating memory banks with greater depth and width than a single device?

ReviewWhat signals does the ADuC7026 use to support 8-bit and 16-bit access to 512kB of external memory space? Why does the ADuC7026 use a multiplexed AD bus? Why isn’t address bit A0 used in a 16-bit memory space? What is the logic used to generate /BHE and /BLE?Can we connect a 4-bit device by itself to the ADuC7026 bus? Any hazards? How to mitigate?

ReviewAt how many different addresses will a single physical location exist if a device is partially decoded?If 0x12345 is stored as a 32-bit word at address 0x1000, show how it is stored in a little-endian system. Is either endian better than the other?How does a watchdog timer work?What type of rotary encoder would be best for a car stereo volume control?What is a level-sensitive IRQ line?

ReviewAn ISR services a communications receiver. The interrupt occurs when a single byte of data is available at address 0x70000000. The ISR will call a subroutine scan to get the incoming data and looks for a specified string. If detected, it returns R0<>0, otherwise returns R0=0.Write the scan subroutine. Do not worry about context save/restore. Use a terminating 0 on the target string to set the comparison length. Assume characters only appear once in the string (use “ATZ” for this example).

ReviewThat’s all, folks!

Basic Read Cycle

Basic Write Cycle

Read Cycle Parameters

Write Cycle Parameters

Read Cycle Controls

Write Cycle Controls

Microprocessor/Memory System

Consecutive Write Cycles

Synchronous Communications

Back frame

Asynchronous Communications -RS232 Framing

Back

What do you need to know in order to figure out what the data is?