ECE 353Introduction to Microprocessor Systems

Michael J. Schulte

Week 7

TopicsClock and reset generation.Bus timing.Bus signal demultiplexing.System bufferingDetermining suitability of logic family interconnections.

System Diagram

80C188EB Package

Clock and ResetClock Generation Internal Oscillator External Oscillator Processor ClockReset Cold-start vs. warm-start RC reset circuit Microprocessor Supervisors

MAX807

Bus CyclesBasic Read Cycle Sequence at Bus Level DiagramBasic Write Cycle Sequence at Bus Level DiagramStates and PhasesBus Cycle State DiagramTypes of Bus Cycles S2:0 indicate the type of bus cycle in

progress.

Bus Cycles80C188EB Bus Cycle Timing Read Cycle Write CycleExercise: What type(s) of bus cycles are run? What address and data during each?001A BA 1000 mov dx, 1000h001D C7 07 1234 mov [bx], 1234h0021 8A 07 mov al, [bx]0023 EE out dx, al0024 ED in ax, dx

DemultiplexingMultiplexed Signal Timing Bus signal phasesDemultiplexing Strategies Remote Demultiplexing Local DemultiplexingImplementation Devices Connections Timing

Read Write

Fully-Buffered SystemAdvantages and DisadvantagesSignal Buffering Address bus Data bus

Transceivers Control signals

Control bus Contention issues

Terminology Local bus Buffered bus Partial buffering

Logic Family CompatibilityLogic family characteristics Definitions Logic families

DC noise margins Driver characteristics Receiver characteristics

Compatibility Voltage Current Exercises Capacitive loading TTL to CMOS

Wrapping UpReading for next week Textbook chapters 10.7-10.10, 11

80C188EB Clock Generator

MAX807

Basic Read Cycle

Basic Write Cycle

Bus Cycle State Diagram

Bus Cycle Types

Read Cycle

Write Cycle

States & Phases

001A BA 1000 mov dx, 1000h

001D C7 07 1234 mov [bx], 1234h

0021 8A 07 mov al, [bx]

0023 EE out dx, al

0024 ED in ax, dx

Logic Compatibility Exercises

For the following logic families, determine compatibility, noise margins, and fan-out. 74ALS driving 74AC 74AC driving 74ALS

VOHmin VIHmin VOLmax VILmax IOHmax IIHmax IOLmax IILmax

74ALS

2.7V 2.0V 0.5V 0.8V -400uA +20uA +8.0mA

-200uA

74AC 4.9V3.76V

0.7*VCC 0.1V0.7V

0.3*VCC -50uA-24mA

+1uA +50uA+24mA

-1uA

Note: For 74AC, top line is with CMOS load, bottom line is with TTL load.

TinyLogicTM and Little Logic