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ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

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Page 1: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

ECE 3561 - Lecture 1 1

The MSP430xxxx

Department of Electrical and Computer EngineeringThe Ohio State University

ECE 2560

Page 2: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

ECE 3561 - Lecture 1 2

Today

The MSP430 MicrocontrollerWhat is a microcontroller

The Physical Chip/ProcessorMemory structureAddressing Modes

Page 3: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

The MSP430 Microcontroller

What is a microcontroller?A microprocessor with memory and I/O port

support directly on chip. It also includes controllers for interfaces such a JTAG, SPIO, A-to-D conversion on board.

With the support on chip, microcontrollers are very important in design and implementation of embedded systems.

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Page 4: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

The MSP430

A von-Neumann style architecture Key features

Ultralow-power architecture 0.1 uA RAM rentention 0.8 uA real-time clock mode 250 uA/MIPS active

High-performance A-to-D conversion 12-bit or 10-bit ADC, 12-bit dual-DAC 200 ksps

16-bit RISC processor features Large Register file Compact code design 27 core instructions 7 addressing modes

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Page 5: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

The MSP430

Block Diagram of internal structure – high level

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Page 6: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

MSP430

Memory structure – logical16-bit addressable

64K bytes (64KB)Amount of Flash/ROM

and RAM vary by device

Last 16 words of Flash/ROM used for the Interrupt Vector Table

I/O is memory mapped

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Page 7: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Memory data organization

Bytes can be at even or odd addresses

Words are only at even addressesThe low byte of a word

is at the even address.The high byte of a word

is at the odd address

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Page 8: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Memory dump

Big endian and little endian (the 430) Little endian is more logical but… (pg 27 of text) If memory is dumped by the debugger Addresses increase from low to high across a line Display is low-order-byte high-order-byte so $1234 is displayed $34 $12 bytes look reversed but consistent with their address Can be avoided by getting the dump in words versus bytes.

(Will see this later in examples) (Code composer supports this)

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Page 9: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

The MSP430 CPU

Incorporates features to support modern programming techniques (Don’t need go to’s)

The features Calculated branching Table processing 27 RISC instructions 7 addressing modes All instructions use all the addressing modes Full register access Single cycle register operations (RISC) Direct memory-to-memory transfers Constant generator provides most used values

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Page 10: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

The MSP430 data path

There are 16 registers Contents are 16-bits User has access to all registers 4 registers are special purpose

Note bus structure MDB – Memory Data Bus MAB – Memory Address Bus Also have 2 internal bussed to

deliver 2 operand to ALU Diagram is called the datapath of

the processor See Users Guide

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Page 11: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

General purpose registers

R4 thru R15Registers are indistinguishableCan be used as

Data RegistersAddress Registers Index values

Can be accessed with byte or word instructions

There is Register-Byte operation and Byte-Register operation – covered later

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Page 12: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Addressing Modes

MSP430 addressing modes Addressing mode – the way in which the

operand(s) of an instruction are accessed, i.e., the effective addresses are calculated.

7 modes supported Register Mode – (Rn) – operands are in registers Immediate Mode – #N – The operand is part of the

instruction Instructions have format OPCODE #OPERAND

Absolute Mode – &ADDR – The address of the operand is given by the word following the opcode

Instructions have format OPCODE &ADDRESS

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Page 13: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Addressing Modes (2)

Remainder of addressing mode Indexed Mode – X(Rn) – (Rn+X) points to (is the

address of) the operand. The value X is the next word in the instruction stream after the OPCODE.

Symbolic Mode – ADDR – (PC+X) points to the operand. X is the next word.

Indirect Register Mode - @Rn – Rn is used as a pointer to the operand.

Indirect Autoincrement - @Rn+ - Rn is used as a pointer to the operand. After access Rn is incremented by 1 for .B instructions and by 2 for .W instructions

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Page 14: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Register Mode Addressing

Note gives action if only a byte

Form is MOV.B R1,R2

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Page 15: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Immediate Mode addressing

Operand is part of instruction

Destination can be a register or a memory location.

If a register instruction is only 2 words

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Page 16: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Absolute Mode Addressing

One of operands can be a register

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Absolute Mode Addressing (2)

Effect

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Page 18: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Indexed Mode Addressing

Summary

ECE 3561 - Lecture 1 18

Page 19: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Indexed Mode Addressing (2)

Action

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Page 20: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Symbolic Mode Addressing

Summary

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Page 21: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Symbolic Mode Addressing (2)

Action

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Page 22: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Indirect Register Mode

Summary

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Page 23: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Indirect Register Mode (2)

Action

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Page 24: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Indirect Autoincrement Mode

Summary

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Page 25: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

Indirect Autoincrement Mode (2)

Action

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Page 26: ECE 3561 - Lecture 1 1 The MSP430xxxx Department of Electrical and Computer Engineering The Ohio State University ECE 2560

ECE 3561 - Lecture 1 26

Assignment

The MSP 430 Users Guide has been added to the course webpage.

The information of this lecture can be found there (section 3.3).

Quiz next week – (again)Some 430 questions