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Copyright © by Jose E. SchuttAine , All Rights Reserved ECE 451 1 ECE 451 Signal Integrity Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois [email protected]

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Page 1: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 1

ECE 451Signal Integrity

Jose E. Schutt-AineElectrical & Computer Engineering

University of [email protected]

Page 2: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 2

TransmissionChannel

TransmissionChannel

TransmissionChannel

Ideal

Common

Noisy

Signal Integrity

Page 3: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 3

• Attenuation & Loss (skin effect, on-chip loss)• Crosstalk (interconnect proximity, coupling)• Dispersion (frequency dependence of parameters)• Reflection (unmatched loads, reactive loads, ISI)• Distortion (nonlinear loads)• Interference & Radiation (EMI/EMC)• Rise time degradation• Clock skew (different electrical path lengths)

Signal Integrity

Page 4: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 4

The Interconnect BottleneckThe Interconnect Bottleneck

TechnologyGeneration

MOSFET IntrinsicSwitching Delay

ResponseTime

1.0 um

0.01 um

~ 10 ps

~ 1 ps

~ 1 ps

~ 100 ps

Page 5: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 5

ChipChip--Level Interconnect DelayLevel Interconnect DelayLine

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Vol

ts

0 0.4 0.8 1.2 1.6 2Time (ns)

Far End Response

BoardVLSISubmicronDeep Submicron

-0.1

0.175

0.45

0.725

1

0 0.4

Vol

ts

0.8 1.2 1.6 2Time (ns)

Near End Response

BoardVLSISubmicronDeep Submicron

Pulse Characteristics: rise time: 100 ps fall time: 100 ps pulse width: 4ns

Line Characteristics length : 3 mm near end termination: 50 far end termination 65

LogicthresholdLogic

threshold

Page 6: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 6

Signal Integrity

Crosstalk Dispersion Attenuation

Reflection Distortion Loss

Delta I Noise Ground Bounce Radiation

Sense Line

Drive Line

Drive Line

Interconnect BottleneckInterconnect Bottleneck

Page 7: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 7

Reflection in Transmission Lines

1.

2.

3.

Page 8: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 8

Metallic Conductors

Length

Area

Re sist an ce : R

Package level:W=3 milsR=0.0045 /mm

R = Le ng th Are a

Submicron level:W=0.25 micronsR=422 /mm

Page 9: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 9

Metal Conductivity -1 m 10-7)

Silver 6.1Copper 5.8Gold 3.5Aluminum 1.8Tungsten 1.8Brass 1.5Solder 0.7Lead 0.5Mercury 0.1

Metallic Conductors

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 10

RF SOURCE

Loss in Transmission Lines

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Low Frequency High Frequency Very High Frequency

Skin Effect in Transmission Lines

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 12

.

Magnitude of current density

y

w

t

e

D

V

J = Joe- y /d e

- jy / d

d

Skin Effect in Microstrip

r

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 13

The electric field in a material medium propagates as

z

Eoez Eoeze jz

where j. We also have

= (1+j) .

Skin EffectSkin Effect

Wint

s

s

Hint

CURRENT AREAS

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 14

Current density varies as

J Joey / e jy /

Note that the phase of the current density varies as a function of y. The total

current is given by:

/ /

0 1y jy o

oJ wI J we e dy

j

oo o o

JE J E

The voltage measured over a section of the conductor of length L is:

oo

J DV E D

Skin effect and internal inductance

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 15

The “skin effect” impedance is therefore

(1 ) (1 )oskin

o

J DV j DZ j fI J w w

where 1

is the bulk resistivity of the conductor

Zskin Rskin jXskin

with

skin skinDR X fw

Skin effect and internal inductance

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 16

Vz

= (R+ jL)I = ZI

Iz

= (G+ jC)V = YV

Lossy Transmission LineL

z

C

I

V

+

-

G

R

Telegraphers Equation

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 17

z

R, L, G, C,

Lossy Transmission Line

forward wave

backward wave

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 18

Coupled Lines and Crosstalk

r

w s

h

Cs

V1

V2

I1

I2

Cs

Cm Lm

Page 19: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 19

50 line 1

line 2

50

line 1

line 2

50 line 1

line 2

line 1

line 2

Crosstalk noise depends on termination

Page 20: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 20

50 line 1

line 2

50

line 1

line 2

line 1

line 2

tr = 1 ns tr = 7 ns

Crosstalk depends on signal rise time

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 21

tr = 1 ns tr = 7 ns

Crosstalk depends on signal rise time

50 line 1

line 2

line 1

line 2

line 1

line 2

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 22

-0.2

0

0.2

0.4

0.6

0.8

1

Vol

ts

0 5 10 15 20 25 30

Time (ns)

Drive Line at Near End

35 40

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Vol

ts

0 5 10 15 20 25 30

Time (ns)

Sense Line at Near End

35 40

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 23

ALS04 ALS240Drive Line 1

Drive Line 2

z=0 z=l

Drive Line 3

Sense Line 4

Drive Line 5

Drive Line 6

Drive Line 7

ALS04

ALS04

ALS04

ALS04

ALS04

ALS240

ALS240

ALS240

ALS240

ALS240

7-Line Coupled-Microstrip System

Ls = 312 nH/m; Cs = 100 pF/m;

Lm = 85 nH/m; Cm = 12 pF/m.

Page 24: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 24

20010000

1

2

3

4

5Drive line 3 at Near End

Time (ns)2001000

-1

0

1

2

3

4

5Drive Line 3 at Far End

Time (ns)

Drive Line 3

Page 25: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 25

2001000-1

0

1

2Sense Line at Near End

Time (ns)2001000

-1

0

1

2Sense Line at Far End

Time (ns)

Sense Line

Page 26: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 26

Multiconductor Simulation

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451 27

• Signal launched on a transmission line can be affected by previous signals as result of reflections

• ISI can be a major concern especially if the signal delay is smaller than twice the time of flight

• ISI can have devastating effects

• Noise must be allowed to settled before next signal is sent

Intersymbol Interference (ISI)

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Volts

Time

Waveform beginning transition from low to highwith unsettled noise on the bus

Different starting point due to ISI

Receiver switching threshold

Timing differencedue to ISI

Ideal waveform beginning transistionfrom low to high with no noise on the bus

Intersymbol Interference

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• Minimize reflections on the bus by avoiding impedance discontinuities

• Minimize stub lengths and large parasitics from package sockets or connectors

• Keep interconnects as short as possible (minimize delay)

• Minimize crosstalk effects

Minimizing ISI

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Copyright © by Jose E. Schutt‐Aine , All Rights ReservedECE 451

• Timing uncertainties in digital transmission systems• Utmost importance because timing uncertainties cause bit errors• There are different types of jitter

Jitter DefinitionJitter DefinitionJitter is difference in time of when somethingwas ideally to occur and when it actually did occur.

Some devices specify the amount of marginal jitter and totaljitter that it can take to operate correctly. If the cable addsmore jitter than the receiver’s allowed marginal jitter and total jitter the signal will not be received correctly. In this case the jitter is measured as in the below diagram

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• Jitter is a signal timing deviation referenced to a recovered clock from the recovered bit stream

• Measured in Unit Intervals and captured visually with eye diagrams

• Two types of jitter– Deterministic (non Gaussian)– Random

• The total jitter (TJ) is the sum of the random (RJ) and deterministic jitter(DJ)

Jitter CharacteristicsJitter Characteristics

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Types of JitterTypes of Jitter

•Deterministic Jitter (DDJ)Data‐Dependent Jitter (DDJ)Periodic Jitter (PJ)Bounded Uncorrelated Jitter (BUJ)

• Random Jitter (RJ)Gaussian Jitter f Higher‐Order Jitter 

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Bandwidth Limitations Cause intersymbol interference (ISI) ISI occurs if time required by signal to completely charge is longer

than bit interval Amount of ISI is function of channel and data content of signal

Jitter EffectsJitter Effects

Oscillator Phase Noise Present in reference clocks or high-speed clocks In PLL based clocks, phase noise can be amplified

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Jitter StatisticsJitter StatisticsMost common way to look at jitter is in statistical domain

Because one can observe jitter histograms directly on oscilloscopes

No instruments to measure jitter time waveform or frequency spectrum directly

Jitter Histograms and Probability Density Functions (PDF)Built directly from time waveforms Frequency information is lostPeak‐to‐peak value depends on observation time

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Total Jitter Time WaveformTotal Jitter Time Waveform

The total jitter waveform is the sum of individual components

TJ(t) = PJ(t) + RJ(t)

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Jitter StatisticsJitter Statistics

TJ(x) = PJ(x) * RJ(x)

The total jitter PDF is the convolution of individual components

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An eye diagram is a time-folded representation of a signal that carries digital information

Eye DiagramEye Diagram

Page 38: ECE 451 Signal Integrity - University Of Illinoisemlab.illinois.edu/ece451/appnotes/signal_integrity.pdfFar End Response Board VLSI Submicron Deep Submicron-0.1 0.175 0.45 0.725 1

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Eye Diagram ConstructionEye Diagram Construction

Eye diagram construction in real-time oscilloscope is based on hardware clock recovery and trigger circuitry

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Eye Diagram ConstructionEye Diagram Construction

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1. Capture of the Waveform Record

2. Determine the Edge Times

Eye Diagram ConstructionEye Diagram Construction

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Eye Diagram ConstructionEye Diagram Construction

3. Determine the Bit Labels

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4. Clock Recovery

Eye Diagram ConstructionEye Diagram Construction

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Eye Diagram ConstructionEye Diagram Construction

5. Slice Overlay

6. Display

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Eye Diagram MeasurementsEye Diagram Measurements

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Reference LevelsReference Levels

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Eye HeightEye HeightEye Height is the measuremnt of the eye height in volts

3 3PTop PTop PBase PBaseEye Height

PTop

PBasePBasePTop

: mean value of eye top

: standard deviation of eye top

: mean value of eye base

: standard deviation of eye base

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Eye WidthEye WidthEye Width is the measuremnt of the eye width in seconds

2 2 1 13 3TCross TCross TCross TCrossEyeWidth

1Crossing Percent 100%PCross PBase

PTop PBase

Crossing percent measurement is the eye crossing point expressed as a percentage of the eye height

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Eye Diagram SpecificationsEye Diagram Specifications

PCI Express 2.0 eye diagram specification for full and deemphasized signals

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Margin TestingMargin Testing

Eye diagram with low margin

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Pseudorandomsequencegenerator

Transmitter Receiver

Scope

Trig Vert

Clk

Data

Fiber

Eye Pattern AnalysisEye Pattern Analysis

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Typical Eye Diagrams

Eye DiagramEye Diagram

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Eye Diagram ‐ ADS Simulation 

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Eye Diagram ‐ ADS SimulationIdeal Matched Line 

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Eye Diagram ‐ ADS Simulation5 GHz Data Transmission 

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Eye Diagram ‐ ADS Simulation5 GHz Data Transmission 

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Eye Diagram ‐ ADS Simulation10 GHz Data Transmission 

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Eye Diagram ‐ ADS Simulation 

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• The Bit-error rate (BER) quantifies the likelihood of a bit being interpreted at the receiver incorrectly due to jitter- or amplitude-induced degradation on the received signal

• No higher than a 10-16 BER is tolerable no more than 1 error out of 1016 bits.

• BER can be measured directly or quantified with statistical calculations

• Deterministic jitter(DJ) can be easily measured via S-parameters obtained in the frequency domain

Bit‐Error Rate