ece 4510/5530 microcontroller applications chapter...

ECE 4510/5530Microcontroller Applications

Chapter 1

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

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Chapter 1 Overview• Basic Computer Concepts• Introduction to Microprocessor• Applications of Microprocessors• Introduction to Microcontroller• Applications of Microcontroller• Microprocessor vs Microcontroller• Processor, Memory, I/O ports and Peripheral modules and

Software

Modern Computers

• They are everywhere and in just about everything.– Ubiquitous computing– Cloud computing

• We are all users …– Some of us are knowledgeable users– Fewer understand basic “computer architecture”– Fewer yet are programmers– And a very few are designers, architecting and building the next

generation.

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Microcontroller vs. Microprocessor

• From wikipedia: http://en.wikipedia.org/wiki/Microcontroller

• Volume– About 55% of all CPUs sold in the world are 8-bit microcontrollers

and microprocessors. According to Semico, over four billion 8-bit microcontrollers were sold in 2006.[http://www.semico.com]

– A typical home in a developed country is likely to have only four general-purpose microprocessors but around three dozen microcontrollers. A typical mid-range automobile has as many as 30 or more microcontrollers. They can also be found in many electrical device such as washing machines, microwave ovens, and telephones.

ECE 2510 4This is old news … there are probably more!

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Embedded Computers in Industry

• The goal of general-purpose computers is to accommodate variety of the programs selected by user and execute them quickly.– To meet this goal, scientist/engineers have been developing

powerful computing units, sophisticated memories, complex input outputs and efficient buses.

• In 1970s automobile executive companies saw benefits of the computers in their cars. To make their cars reliable , safe and fuel efficient. – These applications do not need general purpose computers and

demanded embedded computers.

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Computers in Industry

• The goal of general-purpose computers is to accommodate variety of the programs selected by user and execute them quickly.– To meet this goal, scientist/engineers have been developing

powerful computing units, sophisticated memories, complex input outputs and efficient buses.

• In 1970s automobile executive companies saw benefits of the computers in their cars. To make their cars reliable , safe and fuel efficient. – These and many more applications do not need general purpose

computers and demanded embedded computers.

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Embedded Processors

• The embedded processors contains all necessary parts including memory and I/O ports within a single chip. These computers run at much slower memory clock and have a smaller memory size.

• Embedded computers can also be found in washing machine, microwave oven, camcorder, video cassette recorder, camera, cellular phone, and many other appliances. A family of embedded computers is based on the 68HC12 microcontroller.

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• Cell phone: making the phone call, accepting incoming call, accessing Internet, displaying

• Home security system: sensing external temperature, smoke, humidity, and intruders; taking appropriate actions according to the detected events

• Automobile: monitoring speed, gas level, temperature, distance, direction, and so on; controlling display, full injection, air bag deployment, cruising, and so on; giving warnings

• Network router: responsible for message routing, congestion and traffic control, and so on

Other Examples of Embedded System

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Computers and embedded controllers

• All general-purpose computers or microcontrollers contain four hardware modules:1. Central processing unit (CPU)2. Memory3. Input/output (I/O) devices4. Buses

• CPU controls order of instruction execution, controls the access to the memory and I/O devices, performs arithmetic and logical operations, and handles interrupt services.

• The CPU contains an arithmetic and logical unit (ALU), a control unit, internal registers (for temporary storage)

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The Computing Problem

HardwareArchitcture

OperatingSystem

ApplicationSoftware

System or ApplicationRequirements

Algorithmand DataStructures

High-LevelLanguages

Mapping

Binding(Compile,

Link, Load)

Programming

PerformanceEvaluationK. Hwang, Advanced Computer Architecture:

Parallelism, Scalability, Programmability, McGraw Hill, 1993. ISBM: 0-07-031622-8

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Six layers for a computer system development

Applications

Programming Environment

Languages Supported

Communication Model

Addressing Space

Hardware Architecture

MachineDependent

MachineIndependent

K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw Hill, 1993. ISBM: 0-07-031622-8

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C o ntro l U nit

D atapath

Arithm e ticLo gic U nit

Re gis te rs

P ro c e sso r

Co m m o n B us (addre ss , data, & c o ntro l)

M e m o ry

P ro gramSto rage

D ataSto rage

O utputU nits

InputU nits

Figure 1 .1 Co m pute r O rganizatio n

The CPU

• The CPU contains:– arithmetic and logical unit

(ALU)– control unit– internal registers (for

temporary storage)– Timer related components– Internal and external

connections (buses).

The Processor

• Registers– Contain digital values– Local data– Data memory addresses

• Control Unit– Handles executing the program– Program counter (address of current instruction)– Instruction register (describes what is to be done)– Handle program flow (called branching when not linear)

• Arithmetic Logic Unit– Arithmetic and logic operations on register or memory values

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CPU Processing Rate

• Speed of a CPU is based on:– The clock rate (speed in Hertz)– Format of an instruction (CPI: cycles per instruction)– Parallel nature of instruction execution (CPI <1)– Access time to its memory and I/O devices (Not likely, too slow)

• A 3.2 GHz machine gives information about its clock speed which is a good indication of the machine speed but …it is equally important to consider other factors to measure overall performance of a computer: e.g. memory speed, I/O speed, how the software program was written, etc.

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Memory

• There are two types of information stored in memory: – Instructions, specifying types of operations a computer executes.

• Such as: activities like accessing I/O, adding two numbers or logical operations

– Data, the actual numerical values necessary to carry out instructions.

• In adding two numbers the addition operation is an instruction and actual numbers being added are data.

• Von Neumann memory architecture (1945): stores both instruction and data in a single memory. M68HC12 has this basic structure.

• Harvard memory architecture: stores instruction and data in separate data memories.

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• Registers are present in the CPU• Cache is a type of memory

designed to reduce memory latency by reorganizing the memory.– Small memory component with fast

access time is placed closer to CPU

• 2nd level cache is larger than first layer cache and has faster access time compare to main memory.

• Main memory contains all data and programs.

Cache

2nd level cache

Main memory

Registers

Memory Hierarchy

CPU

PCs and large

computers

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Memory Types

• Different types of memory are– RAM (Random Access Memory)

• Allows processor to read from and write into any location on the memory chip

• RAM is volatile and cannot retain data without power– ROM (Read Only Memory)

• ROM is non volatile memory• ROM data can only be read. Does not allow to perform write

operations on its memory locations– PROM (Programmable Read Only Memory)

• Can be programmed using a PROM programmer or burner• Once programmed its contents cannot be changed.

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Memory Types (Cont.)

• EPROM (Erasable Programmable Read Only Memory)– Read only memory that can be erased by exposing it to strong ultra violet

rays– Requires to erase the contents of a location before writing a new value to it

• EEPROM (Electrically Erasable Programmable ROM)– Non volatile memory that can be erased by electrical signals– Requires to erase the contents of a location before writing a new value to it– Allows each individual location to be erased and programmed

• Flash Memory– Developed to overcome the drawbacks of EPROM and EEPROM– Can be erased and programmed without a dedicated programmer– Can be erased and programmed electrically– Does not provide the facility of erasing a single location but facilitates

erasure of a block of memory or entire chip

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Buses and Peripheral Devices

• Buses are physical connections or pathways among the CPU, memory and Peripheral (Inout/Output) devices. There are three types of buses:1. The address buses, is used to identify the address location where data and

instructions reside in memory .2. The data buses is used to carry actual information between CPU, memory

location and I/O devices.3. The control buses, is for sending and receiving control command such as:

CPU, memory, and I/O devices.

• The purpose of input devices is transferring outside information into the computer, i.e. keyboard, mouse, microphone scanner.

• The function of output devices is allowing the computer to inform its internal states and data to the outside world. Such as: monitor, speaker, and printer.

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Computer system

• A computer system is shown above. It consists of a CPU or central processing, memory containing the program and data, and I/O interface with associated input and output devices, and three buses connecting the elements of the system together.

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Computers, Microprocessors, Microcomputers, Microcontrollers

• Microprocessors are CPU package in a single chip such as Intel Pentium family chip, AMD K series, Athlon.– A computer that uses microprocessor as its CPU is called

microcomputer, such as PC.– Microprocessors require external memory and cannot directly

interface with I/O devices, peripheral interface ICs are needed.

• Microcontroller is a package of the CPU, the memory, the I/O ports and buses in a single chip.– Contains everything needed to be a stand-alone microcomputer.– Typically found as an embedded computer application used to

control a subsystem or device.

Inside an HC12 Microcontroller

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Simple Processor Diagram

• Registers Interactions

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Important Peripherals

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Computer Software

• Computer programs are known as software.• A program is a sequence of instructions.• There are at least three levels of software:

1. Kernel: is a program responsible for making the computer hardware perform the instructions that a programmer wrote.

2. Operating software: is responsible for memory management, exception services, and program execution control, such as: MacOS, Windows 95, 98, 2000, XP, Linux, UNIX …

3. Application program: such as: word processor, spreadsheets, email, text editor …

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Computer Software

• Microprocessor/Microcontroller Instructions/Languages– Machine, Assembly, and High-Level

• Machine instructions:– A sequence of binary digits which can be executed by the

processor• 0001 1000 0000 0110: [A] + [B] ═> A aba• 0100 0011: [A] + 1 ═> A inca• 1000 0110 0000 0110: 6 ═> A ldaa #06

– Hard to understand, enter, debug, and maintain for human being– A readable equivalent of what is performed is shown first– A mnemonic for the machine instruction is shown second.

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Assembly Language

• Defined by assembly language instructions– An assembly instruction is a mnemonic representation of a

machine instruction• Mnemonic What it does (RTL) • aba ; [A] + [B] ═> A• deca ; [A] - 1 ═> A

– Assembly programs must be translated into machine instructions before it can be executed -- translated by an assembler

– There are two kinds of assemblers: native assembler and cross assembler.

– Programmers need to work on the program logic at a very low level and cannot achieve high productivity.

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Assembly Language Example

Loop1:ldx #Array1 ; Loads index register X with start address of Array1ldy #Array2 ; Loads index register Y with start address of Array2ldab #$0A ; Loads B accumulator with value 10 for counter

Assembly Language Instructions Elements:Label: a defined location in the code used by compiler/assemblerOpcode: descriptor of the operation to be performedSource and Destination: source and destination of operands

(from where, to where)Where the next instruction comes from

(usually the next instruction, increment PC)

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line

1:

2:

3:

4:

5:

addr.

2000

2003

2006

2009

machine code

B6 1000

BB 1001

BB 1002

7A 1100

source code

ldaa $1000

adda $1001

adda $1002

staa $1100

Machine/Assembly Code Example

• The example shows:– The address where the machine code is to be stored in memory– The machine code in hex– The assembly code or source code with an assembler directive

• The assembler directive tells the assembler at what address to start storing the machine code

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High-level Language

• Syntax of a high-level language is “similar to English” (?!)• A translator is required to translate the program written in

a high-level language -- done by a compiler.– There are two types of compilers: native compiler and cross

compiler.

• High-level languages allow the user to work on the program logic at higher level and achieve higher productivity.

• Source code– A program written in assembly or high-level language

• Object code– The output of an assembler or compiler

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line

1:

2:

3:

4:

5:

addr.

2000

2003

2006

2009

machine code

B6 1000

BB 1001

BB 1002

7A 1100

source code

ldaa $1000

adda $1001

adda $1002

staa $1100

Machine/Assembly Code Example

• The example shows:– The address where the machine code is to be stored in memory– The machine code in hex– The assembly code or source code with an assembler directive

• The assembler directive tells the assembler at what address to start storing the machine code

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Microcontroller Used for This Class

• MC9S12DP512 16-bit Microcontroller manufactured by Motorola/Freescale

• Includes:– HCS12 CPU Core

(speed 24 MHz)– On-Chip Debug Interface– 512K Flash, 14K RAM, 4K EEPROM– 91 I/O Lines, ATD Module, Timer

Module, PWM, SPI, SCI, IIC and CAN modules and PLL module

– Widely used in the automobile industry

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How Widely Used?

According to the U.S. Bureau of the Census, the resident population of the United States, projected to 05/11/11 is 311,331,964.

Therefore, approximately 1 microcontroller for every 3 people in the US every year!

http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=982874

Application Brochure

ECE 2510 34http://cache.freescale.com/files/microcontrollers/doc/brochure/BR1871.pdf?fpsp=1&WT_TYPE=Brochures&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation

Finding This Stuff:• Freescale• 16-bit

Microcontroller• S12 and S12X• S12D

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7 00 7A B

15 0D

8-bit accumulator A and Bor16-bit double accumulator D

15 0X

15 0Y

Index register X

Index register Y

15 0SP Stack pointer

15 0PC Program counter

S X H I N Z V C Condition code registerCarryOverflowZeroNegativeI Interrupt maskHalf-Carry (from bit 3)X Interrupt MaskStop Disable

Figure 1.2 HCS12 CPU registers.

HCS12 CPU Registers

• Data Registers– Two 8-bit, [A] and [B] OR– One 16-bit, [D]

• Memory index registers– Two general purpose, [X] and [Y]– One stack pointer, [SP]

• Program Counter– Instruction address, [PC]

• Condition Code Register– Bits describing completed CPU

operation or instruction results– [C] or [CCR]

Simple Processor Diagram

• Registers Interactions

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Accumulator Based Machines

• All arithmetic or logic functions must go through the accumulator.– Opcode (in the instruction register) relate the operation– The destination is often explicit … the accumulator.– Load and store operations are use often.– The accumulator sets the majority of condition code register bits.

• Index and Stack Pointer Registers– These will be used often for addressing.– There is expected to be a fixed stack and it will be used a lot.

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Condition Code Register

• Condition Code Register (CCR) (8-bit register)– Used to keep track of the program execution status– Control the execution of conditional instructions– Enable the interrupt handling

S X H I N Z V C

Stop disable

Interrupt Mask

Half-Carry

(from bit 3)

Interrupt Mask

Negative

Zero

Overflow

Carry

Most important for arithmetic

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Condition Code Register (1 of 2)

• Carry – Flag is set when and addition/subtraction generates a borrow/carry

in/out of the highest bit position– Applies to unsigned integers

• Overflow – Flag is set when addition of two positive numbers results in a

negative number and vice-versa. i.e. whenever the carry from the most significant bit and the second most significant bit differs

– Applies to signed integers

• Zero – Flag is set when a particular operation leads to a result of zero

• Negative – Flag is set whenever the most significant bit of the result of an operation is

1, i.e. result is negative

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Condition Code Register (2 of 2)

• Interrupt Mask– When set , all maskable interrupts are disabled (detailed explanation

provided during lecture on interrupts)

• Half Carry – Flag is set whenever there is a carry from the lower four bits to the upper

four bits

• X Interrupt Mask – Set during the system reset (detailed explanation provided during lecture

on interrupts)

• Stop – Clearing this bit keeps the processor in standby mode (detailed

explanation provided during lecture on interrupts)

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ContentsAddress

Figure 1.5 The components of a memory location

Memory Addressing

• Memory consists of a sequence of directly addressable locations.– A location is referred to as an information unit.– A memory location can be used to store data, instruction, and the status of

peripheral devices.– A memory location has two components: an address and its contents.

• Addresses in our microcontroller.– For our processor, a 16-bit address. – Each address reads one byte (8-bits), not a 16-bit word .– Physical address range, 0 to 65,535.

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Human Readable Addressing

Leading characters are used to describe a number system– Decimal: 1023– Binary: %0000 0011 1111 1111– Hex: $03FF (also common 0x03FF)– Octal: @001777

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CPU

Address bus lines

Data bus lines

Memory

Figure 1.6 Transferring data between CPU and memory

Transferring Data

• Data transfers between the CPU and the memory are done over the common buses: address bus and data bus.

• Notations: m[addr] represents the contents of a memory location, [reg] or reg refers to the contents of a register. – For example, m[$20] refers to the contents of memory location at

$20.– [A] or A refers to the contents of accumulator A.

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Addressing Modes

• A HCS12 instruction consists of one or two bytes of opcode and zero to five bytes of operand addressing information.– Opcode bytes specify the operation to be performed by the CPU. – For us, the first byte of a two-byte opcode is always $18.

• Addressing modes specify the operand to be operated on.• The addressing mode may specify a value, a register, or a

memory location to be used as an operand.

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Addressing Mode Summary

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Addressing Modes

• Inherent• Immediate• Direct• Extended (or Extended Direct)• Relative (or typically PC Relative)• Indexed

– Indexed with constant offset– Indexed with a data register (accumulator) offset– Indexed with auto pre-/post-increment/decrement of index register

• Indexed-Indirect– Indexed-Indirect with a constant and index register– Indexed-Indirect with a D register and index register

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Inherent Mode

• Instructions that use this mode do not use extra bytes to specify operands because the instructions either do not need operands or all operands are CPU registers.– Examples

• nop ;no operation• inx ;increment register X• deca ;decrement register A

– Operands are implied by the opcode.

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Immediate Mode (use #)

• Operands for instructions that use immediate mode are included in the instruction.– Example

• ldaa #$55 ; Load register A with the value $55, A ← $55• ldx #$1000 ; Load register X with the value $1000, X ← $1000• ldx #Array1 ; Loads index register X with start address of Array1• ldy #Array2 ; Loads index register Y with start address of Array2• ldab #$0A ; Loads B accumulator with value 10

– The CPU does not access a memory address or register for operands.

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Direct Mode

• This mode can only specify memory locations in the range of 0 – 255 (one byte address or two hex digits).– Example

• ldaa $20 ;load register A with memory location $20; A ← ($0020)

• ldab $40 ;load register B with memory location $40; B ← ($0040)

– This mode uses only one byte to specify the operand address.

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Extended (Direct) Mode

• In this mode, the full 16-bit address is provided in the instruction (four hex digits).– For example,

• ldaa $4000 ; load register A with memory location $4000; A ← ($4000)

• ldx $FE60 ; load register X with memory location $FE60; A ← ($FE60)

• lds $3C00 ‘ load the stack pointer to the default address

– This mode uses two bytes to specify the operand address

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Relative Mode (1 of 2)

• Used only by branch instructions that change the PC– Short and long conditional branch instructions use the relative

mode. That’s way it’s also called PC-Relative addressing

• A short branch instructions consists of an 8-bit opcode and a signed 8-bit offset. – The short relative mode can specify a range of -128 ~ +127.

• A long branch instruction consists of an 8-bit opcode and a signed 16-bit offset. – The range of the long relative mode is from -32768 ~ +32767.

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Relative Mode (2 of 2)

• For example,minus:

……bmi minus ; branch if minus

; if N=1, PC ← (PC) + 2 + Rel; else PC ← (PC) + 2

…

A programmer uses a label to specify the branch target and the assembler will figure out the actual branch offset (distance) from the instruction that follows the branch instruction.

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Indexed Mode Overview

• This mode uses the sum of an index register (X, Y, or SP) and an offset to specify the address of an operand.

– The offset can be a 5-bit, 9-bit, or 16-bit signed value.– The offset can be the value in accumulator A, B, or D. – The PC may also be used as the index register for offset addressing, but it

is not recommended.• If offset is not needed, “auto” incrementing or decrementing of the

index register can be performed.– Automatic pre- or post-increment or pre- or post-decrement of the index

registers by -1 to -8 or +1 to +8 are options.• Indexed-Indirect addressing is unique as it generates the address of the

address– Indirect addressing with 16-bit offset or accumulator D as the offset is

supported. • A summary of indexed addressing modes is given in Table 1.3.

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Table 1.3 Summary of indexed operations

Postbytecode (xb)

source codesyntax

Commentsrr: 00 = X, 01 = Y, 10 = SP, 11 = PC

rr0nnnnn

111rr0zs

111rr011

rr1pnnnn

111rr1aa

111rr111

rn,r-n,rn,r-n,r

[n,r]

n,-rn,+rn,r-n,r+

A,rB,rD,r

[D,r]

5-bit constant offset n = -16 to +15r can be X, Y, SP, or PC

Constant offset (9- or 16-bit signed)z: 0 = 9-bit with sign in LSB of postbyte (s) -256< n < 255 1 = 16-bit 0 < n < 65535if z = s = 1, 16-bit offset indexed-indirect (see below)r can be X, Y, SP, or PC16-bit offset indexed-indirect 0 < n < 65536rr can be X, Y, SP, or PCAuto pre-decrement/increment or auto post-decrement/increment ;p = pre-(0) or post-(1), n = -8 to -1 or +1 to +8r can be X, Y, or SP (PC not a valid choice)

+8 = 0111...+1 = 0000-1 = 1111....-8 = 1000

Accumulator offset (unsigned 8-bit 0r 16-bit)aa: 00 = A

01 = B10 = D (16-bit)11 = see accumulator D offset indexed-indirect

r can be X, Y, SP, or PCAccumulator D offset indexed-indirectr can be X, Y, SP, or PC

Indexed Addressing Modes

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Indexed Addressing (1 of 3)

• 5-bit Constant Offset Indexed Addressing (IDX)– The base index register can be X, Y, SP, or PC.– The range of the offset is from -16 to +15.– Examples

• ldaa 0,X ; load A with memory location (X + 0)• stab -8,X ; store B at memory location (X - 8)

• 9-bit Constant Offset Indexed Addressing (IDX1)– The base index register can be X, Y, SP, or PC.– The range of the offset is from -256 to +255.– Examples

• ldaa $FF,X ; load A with memory location (X + 255)• ldab -20,Y ; load B with memory location (Y - 20)

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• 16-bit Constant Offset Indexed Addressing (IDX2)– The base index register can be X, Y, SP, or PC.– This mode allows access any location in the 64-KB range.– Examples

• ldaa 2000,X ; load A with memory location (X + 2000)• staa $4000,Y ; store A at memory location (Y + $4000)

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• 16-bit Constant Indirect Indexed Addressing ( [D,IDX] OR [IDX2] )– A 16-bit offset is added to the base index register to form the

address of a memory location that contains a pointer to the memory location affected by the instruction.

– The square brackets distinguish this addressing mode from the 16-bit constant offset indexing.

– Example,• ldaa [10,X] ; load A with memory location m[m[X + 10]]• staa [D,Y] ; store A at memory location m[m[Y + D]]

• Generate the address containing the address desired.• Useful for using a table of pointers … and the pointers can change in

time (using jump tables)

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Auto Pre/Post-Decrement/Increment Indexed Addressing

• The index register can be incremented or decremented by an integer value either before or after indexing taking place.– The base index register can be X, Y, or SP.– The value to be incremented or decremented is in the ranges -8

thru -1 or 1 thru 8.

• The index register retains the changed value after indexing.– Examples

• staa 1,-Y ; store A at memory location (Y-1), Y ← Y-1• staa 1,Y- ; store A at memory location (Y), Y ← Y-1• ldx 2,+Y ; load X with memory location (Y+2), Y ← Y+2• ldx 2,Y+ ; load X with memory location (Y), Y ← Y+2

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Accumulator Offset Indexed Addressing

• The effective address of the operand is the sum of the accumulator and the base index register.– The base register can be X, Y, SP, or PC.– The accumulator can be the 8-bit A or B or the 16-bit accumulator

D.– Example

• ldaa B,X ; load A with memory location (X + B)• stab A,Y ; store B at memory location (Y + A),

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Examplejmp [D,PC] ; load PC with (PC + D)

go1 dc.w target1

go2 dc.w target2

go3 dc.w target3

…

target1 …

.

target2 …

.

target3 …

Accumulator D Indirect Indexed Addressing

• The value in D is added to the value in the base index register to form the address of the memory location that contains the address to the memory location affected by the instruction.

• The square brackets distinguish this addressing mode from accumulator D offset indexing.

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HCS12 Instruction Types

• LOAD and STORE– LOAD copies the contents of a memory location or places an

immediate value into an accumulator or a CPU register.– STORE save the contents of a CPU register into a memory

location.

• TRANSFER and EXCHANGE– TRANSFER moves the contents of one register into another– EXCHANGE swaps the contents of one register with another

• MOVE– MOVE moves source bytes or words to defined destinations

• sources may be immediate values, index registers addressed memory, or memory locations

• destinations may be index registers addressed memory or memory locations

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HCS12 Instruction Types (cont)

• ADD and SUBTRACT– ADD register value with addressed memory.– SUBTRACT addressed memory from a register value

• BCD operations– perform binary coded decimal adjustments and additions

• INC and DEC– INC increments memory locations or registers– DEC decrements memory locations or registers

• COMPARE and TEST– Operations to set the condition code registers

• BOOLEAN LOGIC FUNCTIONS– AND, OR, and exclusive OR data registers with immediate values

or memory locations

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• CLEAR, COMPLEMENT and NEGATE• MULTIPLY and DIVIDE• BIT LEVEL TEST, SET and CLEAR• SHIFT and ROTATE

– SHIFT register values right or left with zero fill or sign extend– ROTATE register values circularly within the register

• BRANCH INSTRUCTIONS– change program flow based on condition code values– Includes looping primitives

• JUMP and SUBROUTINE– control flow commands

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• INTERRUPT • INDEX MANIPULATION• STACK OPERATIONS• CONDITION CODE MANIPULATION• STOP and WAIT

• See section 5 of the “S12CPUV2.PDF” Reference Manual– Reference Manual in HW Solution Web Site

• See Section 6 for an instruction glossary (one or more pages per instruction)

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Include or Header Files

• mc9s12dp256.h– The C header file fore the specific processor to be included

whenever compiling C code

• mc9s12dp256.s– An assembly language source code file with all common peripheral

register names equated to their correct locations.– If and when specific internal CPU addresses locations are required,

they can be found in this file. Either cut and paste what you need or include the entire file.

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Load and Store Instructions

Transfer and Exchange Instructions

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Mnemonic Function Operation

TAB Transfer A to B (A) B

TAP Transfer A to CCR (A) CCR

TBA Transfer B to A (B) A

TFR Transfer register to register (A, B, CCR, D, X, Y, or SP) A, B, CCR, D, X, Y, or SP

TPA Transfer CCR to A (CCR) A

TSX Transfer SP to X (SP) X

TSY Transfer SP to Y (SP) Y

TXS Transfer X to SP (X) SP

TYS Transfer Y to SP (Y) SP


EXG Exchange register to register (A, B, CCR, D, X, Y, or SP) A, B, CCR, D, X, Y, or SP)

XGDX Exchange D with X (D) (X)

XGDY Exchange D with Y (D) (Y)


SEX Sign extend 8-Bit operand (A, B, or CCR) D, X, Y, or SP

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Move Instructions

Move Instructions


MOVB Move byte (8-bit) (M1) (M2)

MOVW Move word (16-bit) (M1:M1+1) (M2:M2+1)

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Add and Subtract Instructions

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Instruction Tables

• Table information from the manual/textbook

• http://homepages.wmich.edu/~bazuinb/ECE4510/AddressingModeTable.pdf

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Instruction Tables

• Instruction Table and Timing– See Appendix A of the “S12CPUV2.PDF” Reference Manual

Processor Cycles Needed

or CPI

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Instruction Execution Cycle

• Instruction Execution Cycle– One or more read cycles to fetch instruction opcode bytes and

addressing information– One or more read cycles to fetch the memory operand(s) (optional)– Perform the operation specified by the opcode– One or more write cycles to write back the result to either a

register or a memory location (optional)

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Instruction Queue

• Instruction Queue– The HCS12 executes one instruction at a time and many

instructions take several clock cycles to complete.– When the CPU is performing the operation, it does not need to

access memory. • The HCS12 prefetches instructions when the CPU is not accessing

memory to speedup the instruction execution process.• There are two 16-bit queue stages and one 16-bit buffer. Unless

buffering is required, program information is first queued in stage 1, and then advanced to stage 2 for execution.

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