ece 526 lab10

December 5, 2012 [ECE 526L VERILOG LAB]

FALL 2012

ECE 526L – VERILOG HDL/SYNTHESIS LAB

Experiment 10: The VeriRISC CPU

Instructor: Dr. Ronald Mehler

SUBMITTED BY

Sameer PanditStudent ID: 104249481

CECS, CSUN | EXPERIMENT #10: VeriRISC CPU . 1


ContentsTable of Figures...........................................................................................................................................2

Objective :...................................................................................................................................................3

Discussion :..................................................................................................................................................3

Code fo Sequence Controller :.....................................................................................................................4

Code for Clock generator:............................................................................................................................6

Code for 8-bit register:................................................................................................................................7

Code for AASD:............................................................................................................................................8

Code for Program Counter :........................................................................................................................9

Code for ALU:............................................................................................................................................10

Code for CPU :...........................................................................................................................................12

Test Plan :..................................................................................................................................................13

Waveforms :..............................................................................................................................................16

RTL Schematic :..........................................................................................................................................18

Simulation Results:....................................................................................................................................19

Table of FiguresFigure 1: VeriRISC CPU.................................................................................................................................3Figure 2: CPU instructions.........................................................................................................................11Figure 3 : Output Waveform 1...................................................................................................................16Figure 4 : Waveform 2(further zoomed)....................................................................................................16Figure 5 : Zoomed out waveform..............................................................................................................17Figure 6 : rtl schematic..............................................................................................................................18



Objective:The objective of this laboratory is to design a VeriRISC CPU.

Discussion:

In this lab, we were asked to design a VeriRISC CPU. We were to instantiate some of the modules we have done in our previous labs to form this CPU. We were asked to include the following modules:

1. Scalable MUX (Lab #5),2. 8-bit Register (Lab #3),3. 5-bit Counter (Lab #4),4. 32x8 RAM (Lab #7),5. 8-bit ALU (Lab #8),6. Sequence Controller and Clock Generator (Lab #9)

The following is the structure of my VeriRISC CPU. The block diagram was given in the manual:

Figure 1: VeriRISC CPU

I had to make few changes to my previous lab modules to make them compatible for VeriRISC CPU.



OPERATION and CODES:

The specifications for VeriRISC CPU unit was given in the lab manual:

A sequence controller steps the CPU through fetch instruction/fetch operand cycle. The sequence requires 8 master clock cycles. I made many changes to my previous code of Lab 9. The Ph1, Ph2 and fetch are given from clock_gen. The opcode is set based on these 3 inputs.

Code for Sequence Controller:

/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename: control.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/

`timescale 1ns/1ns

module control(load_acc,mem_rd,mem_wr,inc_pc,load_pc,load_ir,halt,opcode,fetch,zero,clk,ph1,ph2,reset);

output load_acc, mem_rd, mem_wr, inc_pc, load_pc, load_ir, halt;input [2:0] opcode;input fetch, zero, ph1, ph2, clk, reset;

reg [2:0] temp;reg [6:0] ctrl;reg load_acc, mem_rd, mem_wr, inc_pc, load_pc, load_ir, halt;

always@(ph1 or ph2 or fetch)begin

temp = {ph1,ph2,fetch};end

always@(posedge clk or negedge reset)begin

if (reset==1'b0)begin

load_acc <= 1'b0;mem_rd <= 1'b0;mem_wr <= 1'b0;inc_pc <= 1'b0;load_pc <= 1'b0;load_ir <= 1'b0;halt <= 1'b0;

end



case(temp)4'b???: ctrl <= 7'b0;4'b011: ctrl <= 7'b0;4'b111: ctrl <= 7'b0100000; 4'b001: ctrl <= 7'b0100010;4'b101: ctrl <= 7'b0100010;4'b010:

beginif (opcode==3'b000)

ctrl <= 7'b0001001;else

ctrl <= 7'b0001000;end

4'b110:begin

if (opcode==3'b010|opcode==3'b011|opcode==3'b100|opcode==3'b101)

ctrl <= 7'b0100000;else

ctrl <= 7'b0;end

4'b000:begin

if (opcode==3'b001 & zero==1'b1)ctrl <= 7'b0001000;

else if (opcode==3'b010|opcode==3'b011|opcode==3'b100|opcode==3'b101)

ctrl <= 7'b1100000;else if (opcode==3'b111)

ctrl <= 7'b0000100;else

ctrl <= 7'b0;end

4'b100:begin

if (opcode==3'b111)ctrl <= 7'b0000100;

else if (opcode==3'b110)ctrl <= 7'b0010000;

else if (opcode==3'b001 & zero==1'b1)ctrl <= 7'b0001000;

else if (opcode==3'b010|opcode==3'b011|opcode==3'b100|opcode==3'b101)

ctrl <= 7'b1100000;else

ctrl <= 7'b0;end

default: ctrl <= 7'b0;endcase

endalways@(ctrl)

{load_acc,mem_rd,mem_wr,inc_pc,load_pc,load_ir,halt} = ctrl;endmodule



Ph1, Ph2 and fetch are generated from clock_gen module which was used in lab 9. Ph1 has to be used as enable to all the other components to make them synchronous.

Also halt from the sequence controller is given as an input to the clk_gen. Interrupt is also assigned as an input to the clk_gen. It is use full when halt signal becomes 1. When halt becomes 1, the CPU comes to a halt. It waits for the interrupt to become 1 to resume the normal operation. The interrupt input is not shown in the block diagram. The following is the code for that:

Code for Clock generator:/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename: clk_gen.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/

`timescale 1 ns / 1 ns

module clk_gen(ph1, ph2, fetch, clk, reset, enable, interrupt);

output reg ph1, ph2, fetch;input clk, reset, enable, interrupt;

reg temp_interrupt;

// reg [3:0] cnt=0;

always@(posedge interrupt)temp_interrupt <= 1'b1;

always@(posedge enable) beginif(!enable)

temp_interrupt <= 1'b1;else

temp_interrupt <= 1'b0;end

always@(posedge clk or negedge reset) beginif(!reset) begin

ph1 <= 1'b0;ph2 <= 1'b0;fetch <= 1'b0;

end

else if(temp_interrupt) begin



ph1 <= ~ph1;if(ph1 == 1'b1)

ph2 <= ~ph2;else

ph2 <= ph2;if(ph1 == 1'b1 && ph2 == 1'b0)

fetch <= ~fetch;else

fetch <= fetch;end

else beginph1 <= ph1;ph2 <= ph2;fetch <= fetch;

endend

endmodule

The whole design must be synchronous to the master clock. No derived signals must be used as a clock.

We were supposed to use a register in this design. We were asked to use register from Lab 3 here, which was modelled structurally. But as the design has to be synchronous with the clock, I made changes to it so that it functions behaviorally. I also got rid of the delays in that. The following is the code which I have modified :

Code for 8-bit register:/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename: register_8bit.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/

`timescale 1ns/1ns

module register_8bit (out,clk, data,ena,load_ir,rst);

input [7:0]data; //8 bit data input input ena,load_ir,clk,rst; //input port declaration output reg [7:0]out; //output port declaration

always@(posedge clk or negedge rst) begin if (!rst) out <= 8'b0; else if(ena) begin



if (load_ir) out <= data;

elseout <= out;

end else

out <= out; endendmodule

The system needs to use Asynchronous Assert, Synchronous De-assert reset in the whole design. Hence I used the AASD module, to which I gave my external reset. The AASD reset output was given in the place of reset for the whole design. The following is the code for AASD :

Code for AASD:/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename: aasd.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/

`timescale 1 ns / 1 ns

module aasd(AASD, clk, reset);

output reg AASD;input clk, reset;

reg R;

always @(posedge clk or negedge reset) beginif(!reset) begin

R <= 1'b0;AASD <= 1'b0;

endelse begin

R <= reset;AASD <= R;

endend

endmodule



A program counter points to the next location in memory from which the CPU will fetch instructions or data. The inputs for the program counter are load_pc and inc_pc from sequence controller. Reset is nothing but AASD reset. The output pc_adr is sent to a mux, which is intern used as address to RAM. The following is the code for program counter, which was taken from 5th lab :

Code for Program Counter :/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename: counter.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/

`timescale 1 ns/ 1 ns

module counter(cnt, rst, clk, load, inc_pc, enable, data);output [4:0] cnt; // counter outputinput [4:0] data; // data to be loaded on cnt when load is enabledinput rst, clk, load, enable, inc_pc;

reg [4:0] cnt;

always@(posedge clk, negedge rst) beginif(!rst)

cnt <= 5'b0;else if(enable) begin

if(load)cnt <= data;

else if(inc_pc)cnt <= cnt+1;

elsecnt <= cnt;

endelse

cnt <= cnt;end

endmodule



ALU receives operands from both accumulator and from memory. Based on the opcode it receives from the instruction register, the functionality of the ALU runs as mentioned in lab 8. The carry flag of ALU c_in is always set to 0. The following is the code for the ALU :

Code for ALU:/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename: alu.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/`timescale 1ns/1ns

module alu(alu_out,CF,OF,SF,ZF,PF,opcode,accum,data,c_in);input [2:0] opcode;input [7:0] accum, data;input c_in;output [7:0] alu_out;output CF, OF, SF, ZF, PF;

reg [7:0] alu_out;reg CF, OF, SF, ZF, PF;

always@(opcode,accum,data,c_in)begin

case(opcode)3'b010: begin {CF, alu_out} <= accum + data + c_in;

OF <= (accum & data) & alu_out;SF <= |alu_out[7];PF <= âlu_out;

end3'b011: begin

alu_out <= accum & data;SF <= alu_out[7];PF <= âlu_out;

end3'b100: begin

alu_out <= accum ^ data;SF <= alu_out[7];PF <= âlu_out;

end3'b101: begin



alu_out <= data;SF <= alu_out[7];PF <= ^alu_out;

enddefault:

beginalu_out <= accum;

SF <= alu_out[7];PF <= ^alu_out;

CF <= 0; OF <= 0; end

endcaseend

always@(accum)begin

if (accum==0) ZF <= 1;else ZF <= 0;

endendmodule

I have included a register for the accumulator. The register is nothing but the 8-bit register which I have instantiated for the instruction register. The same register has been instantiated twice in my design.

There is also a tristate data bus as shown in the design. I used the following code in my main cpu code for the tri-state buffer :

assign data = (mem_wr) ? alu_out : 8'hz;

CPU can process the following instructions:

Figure 2: CPU instructions



Now finally I have included all these instantiations into my top module, which is my cpu. The following is the code for CPU :

Code for CPU :/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename : alu.v Created by Sameer Pandit, 12/03/2012 ****** ***************************************************************************************/`timescale 1 ns / 1 ns

module cpu(interrupt, clk, reset, CF, OF, SF, PF);input clk, interrupt, reset;output CF, OF, SF, PF;wire CF, OF, SF, PF;tri [7:0] data;wire [7:0] accum, ir;wire [7:0] alu_out;wire [4:0] adr;wire [4:0] pc_adr;

wire RST_sync;wire mem_wr, mem_rd, load_ir, load_pc, inc_pc, load_acc;wire ZF, ph1, ph2, fetch, halt;

aasd aasd1(RST_sync, clk, reset); // AASD register_8bit ir_reg(ir, clk, data, ph1, load_ir, RST_sync); //Instruction Register register_8bit accumulator(accum, clk, alu_out, ph1, load_acc, RST_sync); // Accumulator Register

counter prog_cnt(pc_adr, RST_sync, clk, load_pc, inc_pc, ph1, ir[4:0]); //Program Counter

mux mux1(adr, fetch, ir[4:0], pc_adr); //Mux

ram ram1(adr, data, mem_rd, mem_wr); //RAM

alu alu1 (alu_out,CF,OF,SF,ZF,PF,ir[7:5],accum,data,1'b0); //ALU

assign data = (mem_wr) ? alu_out : 8'hz; //Tri-state buffer

control control1(load_acc, mem_rd, mem_wr, inc_pc, load_pc, load_ir, halt,ir[7:5], fetch, ZF, clk, ph1, ph2, RST_sync); // Controller

clk_gen clk_gen1(ph1, ph2, fetch, clk, RST_sync, halt, interrupt); //Clock_gen



endmodule

Test Plan : We were asked to create a testbench, where the data to be written is taken from a text file. The

data is taken from the text file by using $readmemh. I followed similar approach to write the test bench as I have done for the RAM code in Lab 7.The following is the text file which I have used :

Then I wrote the code for my test bench. The following is the code for my test bench :

/*************************************************************************************** ****** EE 526 L Experiment #10 Sameer Pandit, Fall, 2012 ****** ****** Experiment #10: VeriRISC CPU ****** ******************************************************************************************* Filename : tb_cpu.v Created by Sameer Pandit, 12/03/2012 ****** ***

************************************************************************************/`timescale 1ns/1ns

module tb_cpu();

reg clk, interrupt, rst;wire CF, OF, SF, PF;

integer i;

cpu UUT(interrupt, clk, rst, CF, OF, SF, PF);

initial beginclk = 1'b0;forever #10 clk = ~clk;

end

initial beginrst = 1'b0;#10 rst = 1'b1;



end

initial begin$readmemh("cpu_data.txt", UUT.mem1.memory);for (i=0; i<32; i=i+1)

$display("Data at Memory[%0h] = %b", i, UUT.mem1.memory[i]);end

initial begin $monitor ("%d accumulator = %b ; data = %b ; ALU output = %b ; CF = %b ; OF = %b ; SF=%b ; PF = %b; ZF = %b ", $time, UUT.accum, UUT.data, UUT.alu_out, CF, OF, SF, PF, UUT.ZF); end

initial begininterrupt = 1'b0;#1 interrupt = 1'b1;#1000 interrupt = 1'b0;#3000 interrupt = 1'b1;

#1000 $stop;#10 $finish;

end

endmodule

After simulating and displaying the results, I observed the following :The data is being written into the memory :



The memories at 17, 18, 19, 1d shows 'x' because, I have not assigned any values to those memory addresses.

It fetches the instruction from RAM memory : It fetches the data operand from RAM memory, then performs mathematical operations and stores

the results back into the RAM memory. I have also displayed the flags which are set because of the mathematical operations :

The following are the output waveforms :



Waveforms :

Figure 3 : Output Waveform 1

From the above waveform, we can clearly see that the data is being read.

We can also see the ir values. First 5 bits are that of Instruction address and the last 3 are that of opcode. Here we can show that the instruction is being fetched from the RAM memory.

We can also notice the flags that have been set in the process.

The next waveform is further zoomed to show the signals more clearly:

Figure 4 : Waveform 2(further zoomed)



The next one is the zoomed out operation of the complete operation. Here we can observe the values of accumulator as well:

Figure 5 : Zoomed out waveform

The following is the RTL schematic:



RTL Schematic:

Figure 6 : RTL schematic

The signals and names are not visible properly because of the size of the CPU.



Simulation Results:The following is the log file of my simulation:

ncverilog: 08.20-p001: (c) Copyright 1995-2008 Cadence Design Systems, Inc.TOOL: ncverilog 08.20-p001: Started on Dec 06, 2012 at 08:05:19 PSTncverilog

-s+gui+access+rwctb_cpu.vcpu.vaasd.vacc_reg.valu.vclock.vcontrol.vcounter.vreg_register.vs_mux.vmem.v

Recompiling... reason: file './tb_cpu.v' is newer than expected.expected: Thu Dec 6 08:01:48 2012actual: Thu Dec 6 08:05:14 2012

file: tb_cpu.vmodule worklib.tb_cpu:v

errors: 0, warnings: 0file: cpu.vfile: aasd.vfile: acc_reg.vfile: alu.vfile: clock.vfile: control.vfile: counter.vfile: reg_register.vfile: s_mux.vfile: mem.v

Caching library 'worklib' ....... DoneElaborating the design hierarchy:Building instance overlay tables: .................... DoneGenerating native compiled code:

worklib.tb_cpu:v <0x56b4ddb1>streams: 9, words: 7332

Loading native compiled code: .................... DoneBuilding instance specific data structures.Design hierarchy summary:

Instances Unique



Modules: 11 11Resolved nets: 0 1Registers: 30 30Scalar wires: 20 -Vectored wires: 12 -Always blocks: 14 14Initial blocks: 5 5Cont. assignments: 3 3Pseudo assignments: 6 6Simulation timescale: 1ns

Writing initial simulation snapshot: worklib.tb_cpu:v

-------------------------------------Relinquished control to SimVision...ncsim> ncsim> source /opt/cadence/IUS82/tools/inca/files/ncsimrcncsim> runData at Memory[0] = 11111110Data at Memory[1] = 00000000Data at Memory[2] = 00000000Data at Memory[3] = 10111010Data at Memory[4] = 00100000Data at Memory[5] = 00000000Data at Memory[6] = 10111011Data at Memory[7] = 00100000Data at Memory[8] = 11101010Data at Memory[9] = 00000000Data at Memory[a] = 11011100Data at Memory[b] = 10111100Data at Memory[c] = 00100000Data at Memory[d] = 00000000Data at Memory[e] = 10011011Data at Memory[f] = 00100000Data at Memory[10] = 11110100Data at Memory[11] = 00000000Data at Memory[12] = 10011011Data at Memory[13] = 00100000Data at Memory[14] = 00000000Data at Memory[15] = 00000000Data at Memory[16] = 11100000Data at Memory[17] = xxxxxxxxData at Memory[18] = xxxxxxxxData at Memory[19] = xxxxxxxxData at Memory[1a] = 00000000Data at Memory[1b] = 11111111Data at Memory[1c] = 10101010Data at Memory[1d] = xxxxxxxxData at Memory[1e] = 11100011



Data at Memory[1f] = 00000000 0 opcode = 000; accumu = 00; data = xx; alu_out = 00; CF = 0; OF = 0; SF=x; PF = x; ZF = 1 110 opcode = 000; accumu = 00; data = fe; alu_out = 00; CF = 0; OF = 0; SF=0; PF = 0; ZF = 1 150 opcode = 111; accumu = 00; data = e3; alu_out = 00; CF = 0; OF = 0; SF=0; PF = 0; ZF = 1 310 opcode = 111; accumu = 00; data = ba; alu_out = 00; CF = 0; OF = 0; SF=0; PF = 0; ZF = 1 470 opcode = 101; accumu = 00; data = 00; alu_out = 00; CF = 0; OF = 0; SF=1; PF = 1; ZF = 1 550 opcode = 101; accumu = 00; data = 20; alu_out = 20; CF = 0; OF = 0; SF=0; PF = 0; ZF = 1 630 opcode = 001; accumu = 00; data = fe; alu_out = 00; CF = 0; OF = 0; SF=0; PF = 0; ZF = 1 750 opcode = 001; accumu = 00; data = bb; alu_out = 00; CF = 0; OF = 0; SF=0; PF = 0; ZF = 1 790 opcode = 101; accumu = 00; data = ff; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 1 870 opcode = 101; accumu = ff; data = 20; alu_out = 20; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 950 opcode = 001; accumu = ff; data = fe; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1070 opcode = 001; accumu = ff; data = ea; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1110 opcode = 111; accumu = ff; data = dc; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1270 opcode = 110; accumu = ff; data = aa; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1350 opcode = 110; accumu = ff; data = ff; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1370 opcode = 110; accumu = ff; data = aa; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1390 opcode = 110; accumu = ff; data = bc; alu_out = ff; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1430 opcode = 101; accumu = ff; data = aa; alu_out = aa; CF = 0; OF = 0; SF=1; PF = 1; ZF = 0 1510 opcode = 101; accumu = aa; data = 20; alu_out = 20; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1590 opcode = 001; accumu = aa; data = fe; alu_out = aa; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1710 opcode = 001; accumu = aa; data = 00; alu_out = aa; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 1750 opcode = 000; accumu = aa; data = fe; alu_out = aa; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 4090 opcode = 000; accumu = aa; data = 9b; alu_out = aa; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 4130 opcode = 100; accumu = aa; data = ff; alu_out = 55; CF = 0; OF = 0; SF=0; PF = 1; ZF = 0 4210 opcode = 100; accumu = 55; data = 20; alu_out = 75; CF = 0; OF = 0; SF=1; PF = 0; ZF = 0 4290 opcode = 001; accumu = 55; data = fe; alu_out = 55; CF = 0; OF = 0; SF=0; PF = 0; ZF = 0 4410 opcode = 001; accumu = 55; data = f4; alu_out = 55; CF = 0; OF = 0; SF=0; PF = 0; ZF = 0 4450 opcode = 111; accumu = 55; data = 00; alu_out = 55; CF = 0; OF = 0; SF=0; PF = 0; ZF = 0 4610 opcode = 000; accumu = 55; data = fe; alu_out = 55; CF = 0; OF = 0; SF=0; PF = 0; ZF = 0Simulation stopped via $stop(1) at time 5001 NS + 0ncsim>


I hereby declare that this lab report is entirely my own work. I have not copied either code or text from anyone, nor have I allowed or will I allow anyone to copy my work.

Name (printed) ____SAMEER PANDIT____

Name (signed) _______________________ Date ___12/06/2012___

ece 526 lab10

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