ece 550d - all facultypeople.ee.duke.edu/~jab/ece550/slides/08-datapath.pdf · ece 550d...

ECE 550DFundamentals of Computer Systems and Engineering

Fall 2017

Datapaths

Prof. John BoardDuke University

Slides are derived from work byProfs. Tyler Bletch and Andrew Hilton (Duke) and Amir Roth (Penn)

2

Last time

• What did we do last time?• MIPS Assembly

• Practice translating C to assembly together• Using functions

• Calling conventions• jal (call)• jr (return)

3

Now confluence of MIPS + digital logic

• Start of semester: Digital Logic• Building blocks of digital design

• Most recently: MIPS assembly, ISA• Lowest level software

• Now: where they meet…• Datapaths: hardware implementation of processors• By the way: homework 4 = build a datapath

• With some components from the TAs…

4

Necessary ingredient: the ALU

• ALU: Arithmetic/Logic Unit

• Performs any supported math or logic operation on two inputs

• Which operation is chosen by a third input

ALU

A

B

op

out

5

Add/Subtract With Overflow Detection

Full AdderFull AdderFull AdderFull Adder

S0S1Sn- 2Sn- 1

Overflow

a0a1 b0b1an- 2bn- 2an- 1bn- 1

Add/Sub

6

Add/sub

Cin

Cout

Add/sub F

20

1

2

3a

bQ

A F Q0 0 a + b1 0 a - b- 1 NOT b- 2 a OR b- 3 a AND b

ALU Slice

7

The ALU

ALU SliceALU SliceALU SliceALU SliceALU control

a0b0a1b1an-2bn-2an-1bn-1

Q0Q1Qn-2Qn-1

Overflow Is non-zero?

ALU

A

B

op

out

8

Datapath for MIPS ISA

• Consider only the following instructionsadd $1,$2,$3addi $1,2,$3lw $1,4($3)sw $1,4($3)beq $1,$2,PC_relative_targetj absolute_target

• Why only these?• Most other instructions are the same from datapath viewpoint• The one’s that aren’t are left for you to figure out

9

InstructionFetch

InstructionDecode

OperandFetch

Execute

ResultStore

NextInstruction

Remember The von Neumann Model?

• Instruction Fetch: Read instruction bits from memory

• Decode:Figure out what those bits mean

• Operand Fetch:Read registers (+ mem to get sources)

• Execute:Do the actual operation (e.g., add the #s)

• Result Store:Write result to register or memory

• Next Instruction:Figure out mem addr of next insn, repeat

10

Start With Fetch

• Same for all instructions (don’t know insn yet)• PC and instruction memory• A +4 incrementer computes default next instruction PC

• Details of Insn Mem: later…• For now: just assume a bunch of DFFs

PC

InsnMem

+4

11

First Instruction: add

• Add register file and ALU

PC

InsnMem

RegisterFile

R-type

s1 s2 d

+4

Decoding: Very easy in MIPS

Op(6) Rs(5) Rt(5) Rd(5) Sh(5) Func(6)

12

First Instruction: add

• Add register file and ALU

PC

InsnMem

RegisterFile

R-type

s1 s2 d

+4

Decoding: Very easy in MIPS

Op(6) Rs(5) Rt(5) Rd(5) Sh(5) Func(6)

AND, OR, other r-type identical, just change func code! Same datapath

13

Second Instruction: addi

• Destination register can now be either Rd or Rt• Add sign extension unit and mux into second ALU input

PC

InsnMem

RegisterFile

SX

Op(6) Rs(5) Rt(5)I-type Immed(16)

s1 s2 d

+4

14

Third Instruction: lw

• Add data memory, address is ALU output• Add register write data mux to select memory output or ALU output

PC

InsnMem

RegisterFile

SX


s1 s2 d

DataMemd

+4

a

15

Fourth Instruction: sw

• Add path from second input register to data memory data input

PC

InsnMem

RegisterFile

SX


s1 s2 d

DataMem

a

d

+4

16

Fifth Instruction: beq

• Add left shift unit and adder to compute PC-relative branch target• Add PC input mux to select PC+4 or branch target

• Note: shift by fixed amount very simple

PC

InsnMem

RegisterFile

SX


s1 s2 d

DataMem

a

d

+4

<<2

z

17

Sixth Instruction: j

• Add shifter to compute left shift of 26-bit immediate• Add additional PC input mux for jump target

PC

InsnMem

RegisterFile

SX

Op(6)J-type Immed(26)

s1 s2 d

DataMem

a

d

+4

<<2

<<2

18

More Instructions…

• Figure out datapath modifications for • jal (J-type)• jr (R-type)

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

19

Jal

• For jal, need to get PC+4 to RF write mux• (and constant 31 to destination register ID – probably another

mux)

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

20

JR

• For JR need to get RF read value to next PC mux• (and constant 31 to source register ID, again probably another

mux)

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

21

Good practice: Try other insns

• Pick other MIPS instructions, contemplate how to add them

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

22

d

“Continuous Read” Datapath Timing

• Works because writes (PC, RegFile, DMem) are independent• And because no read logically follows any write (until next complete

instruction)• ONE LONG CLOCK CYCLE!

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

+4

Read IMem Read Registers Read DMEM Write DMEMWrite Registers

Write PC

23

d

What Is Control?

• 8 signals control flow of data through this datapath• (well, ALUop is more than one bit..)• MUX selectors, or register/memory write enable signals• A real datapath might have 300-500 control signals

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

+4

<<2

<<2

Rwe

ALUinB

DMwe

JP

ALUop

BR

Rwd

Rdst

24

Example: Control for add

• Control for an instruction: • Values of all control signals to correctly execute it

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

BR=0

JP=0

Rwd=0

DMwe=0ALUop=0

ALUinB=0Rdst=1

Rwe=1

25

Example: Control for sw

• Difference between sw and add is 5 signals• 3 if you don’t count the X (don’t care) signals

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

Rwe=0

ALUinB=1

DMwe=1

JP=0

ALUop=0

BR=0

Rwd=X

Rdst=X

26

d

Example: Control for beq

• Difference between sw and beq is only 4 signals

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

+4

<<2

<<2

Rwe=0

ALUinB=0

DMwe=0

JP=0

ALUop=1

BR=1

Rwd=X

Rdst=X

27

Let’s figure out LW

• How would these control signals be set for LW?

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

Rwe

ALUinB

DMwe

JP

ALUop

BR

Rwd

Rdst

28

Example: Control for LW

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

<<2

<<2

BR=0

JP=0

Rwd=1

DMwe=0ALUop=0

ALUinB=1Rdst=0

Rwe=1

29

d

How Is Control Implemented?

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

+4

<<2

<<2

Rwe

ALUinB

DMwe

JP

ALUop

BR

Rwd

Rdst

Control?

30

Implementing Control

• Each insn has a unique set of control signals• Most are function of opcode• Some may be encoded in the instruction itself

• E.g., the ALUop signal is some portion of the MIPS Func field+ Simplifies controller implementation

• Requires careful ISA design

31

Control Implementation: ROM

• ROM (read only memory): think rows of bits• Bits in data words are control signals• Lines indexed by opcode• Example: ROM control for 6-insn MIPS datapath• X is “don’t care” (electrically must be 0 or 1 but doesn’t matter)

BR JP ALUinB ALUop DMwe Rwe Rdst Rwd

add 0 0 0 0 0 1 0 0addi 0 0 1 0 0 1 1 0

lw 0 0 1 0 0 1 1 1sw 0 0 1 0 1 0 X X

beq 1 0 0 1 0 0 X Xj 0 1 0 0 0 0 X X

opcode

32

Control Implementation: Random Logic

• Real machines have 100+ insns 300+ control signals• 30,000+ control bits (~4KB)• Not huge, but hard to make faster than datapath (important!)

• Alternative: random logic (random = ‘non-repeating’)• More or less what I did for protocomputer• Exploits the observation: many signals have few 1s or few 0s• Example: random logic control for 6-insn MIPS datapath

ALUinB

opco

de

addaddilwswbeqj

BR JP DMwe Rwd Rdst ALUopRwe

Yes, “random logic” is a very dumb and

misleading name for this concept. Sorry.

33

Datapath and Control Timing

• Will usually need an IR (instruction register) buffering current instruction, as in protocomputer, but here can get by with Imem output

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4

Control ROM/random logic

Read IMem Read Registers(Read Control ROM)

Read DMEM Write DMEMWrite Registers

Write PC

34

Single-Cycle Datapath Performance

• This machine will work, and it will be simple, but it will be slow

• Goes against make common case fast (MCCF) principle+ Low Cycles Per Instruction (CPI): 1– Long clock period: to accommodate slowest insn

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4


35

Interlude: Performance

• Previous slide alludes to something new: Performance• Don’t just want it to work…• But want it to go fast!

• Three components to performance:Number of instructions

x Cycles per instruction (CPI)x Clock Period (1 / Clock frequency)

Instructions Cycles Seconds Seconds—————— x ————— x ————— = ——————Program Instruction Cycle Program

36

Interlude: Performance

• Three components to performance:Number of instructions <- Compiler’s Job

x Cycles per instruction (CPI)x Clock Period (1 / Clock frequency)

Instructions Cycles Seconds Seconds—————— x ————— x ————— = ——————Program Instruction Cycle Program

• Insns/Program: determined by compiler + ISA• Generally assume fixed program when doing micro-architecture

37

Micro-architectural factors

• Micro-architecture: • The details of how the ISA is implemented• Affects CPI and Clock frequency

• Often will look at fixed program, and consider MIPS• Million Instructions Per Second• MIPS = IPC * Frequency (in MHz)• IPC = Instruction Per Cycle (1 / CPI)• Gives “Bigger is better” number

Instructions Cycles Instructions————— x ————— = ——————Cycle Second Second(IPC) (Frequency) (Throughput)

The use of “MIPS” to mean “Millions of

Instructions Per Second” has nothing to do with the CPU architecture also called “MIPS”,

which actually stands for “Microprocessor without

Interlocked Pipeline Stages”.

This fact that a major CPU architecture shares a

name with an important metric for performance is incredibly confusing and dumb, and I apologize.

I blame the cocaine-fueled CPU architects of the

1980s.

38

“Best” IPC

• For now, best we can do: IPC = 1 (CPI = 1)• Do 1 instruction every cycle

• Later:• Real processors can do multiple instructions at once!• Potentially: IPC > 1! (CPI < 1!)• Best possible IPC depends on design

39

Performance vs ….

• 1990s: Performance at all cost• Actually more “clock frequency” at all cost…

• Now: Care about other things• Energy (electric bill, battery life)• Power (cooling, also affects energy)• Area (chip cost)• Reliability (tolerance of transient faults: e.g., charge particle strikes) • …

• Important metric these days “Performance / Watt”• Throughput divided by power consumption• Why? What device in particular?

40

Performance Modeling and Analysis

• Speaking of performance• Making a processor takes time (years) and money (millions)• Want to know it will perform well before you finish

• If its wrong, doing it all over is painful…• Performance can be simulated in software

• Estimate what IPC will be• Guide design• Patterson and Hennessy’s other more advanced textbook:

“Computer Architecture: A Quantitative Approach"

41

Single-Cycle Datapath Performance

• Goes against make common case fast (MCCF) principle+ Low Cycles Per Instruction (CPI): 1– Long clock period: to accommodate slowest insn

PC

InsnMem

RegisterFile

SX

s1 s2 d

DataMem

a

d

+4


42

Alternative: Multi-Cycle Datapath

• Multi-cycle datapath: attacks high clock period• Cut datapath into multiple stages (5 here), isolate using FFs• FSM control “walks” insns thru stages (by staging control signals)• Not every instruction needs every stage+ Instructions can bypass stages and exit early

PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

s3

s3

s3 s4

s5

s5s5

43

Multi-cycle Datapath FSM

• First state: Get a New Instruction• Output signals to fetch (e.g., read enable IMEM)• Next State: Always Decode

NextInsn

DecodeInsn

44


• Second State: Decode• Output signals to decode instruction (RdEn RegFile)• Go to Next Insn if NOP• Otherwise Execute

NextInsn

DecodeInsn

ExecuteInsn

NOP

45


• Execute State• Execute Insn (varies by insn type)• Next State: Also depends on insn type

• Branches: Next Insn

NextInsn

DecodeInsn

ExecuteInsnBranch

NOP

46



• ALU op: write register - we call this Writeback (to register file)

NextInsn

DecodeInsn

ExecuteInsnBranch

Writeback

ALU

NOP

47



• Load: Read Memory

NextInsn

DecodeInsn

ExecuteInsnBranch

Writeback

ALU

Read DMEM

Load

NOP

48



• Store: Write Memory

NextInsn

DecodeInsn

ExecuteInsnBranch

Writeback

ALU

Read DMEM

LoadWriteDMEM

Store

NOP

49


• Read DMEM State• Control signals enable DMEM Read• Next state is writeback (what we read from memory needs to go to

a register)

NextInsn

DecodeInsn

ExecuteInsnBranch

Writeback

ALU

Read DMEM

LoadWriteDMEM

Store

NOP

50


• Writeback state• Control signals enable regfile write• Next state: Next Insn

NextInsn

DecodeInsn

ExecuteInsnBranch

Writeback

ALU

Read DMEM

LoadWriteDMEM

Store

NOP

51


• Write DMEM state• Control signals enable memory write• Next state: Next Insn

NextInsn

DecodeInsn

ExecuteInsnBranch

Writeback

ALU

Read DMEM

LoadWriteDMEM

Store

NOP

52

Multi-Cycle Datapath Example: Add

PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

• Example: Add• Cycle 1: Read IMEM

53


PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

• Example: Add• Cycle 1: Read IMEM• Cycle 2: Decode + Read RF

54


PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

• Example: Add• Cycle 1: Read IMEM• Cycle 2: Decode + Read RF• Cycle 3: ALU

55


• Example: Add• Cycle 1: Read IMEM• Cycle 2: Decode + Read RF• Cycle 3: ALU• Cycle 4: Writeback + Increment PC

PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

56

Multi-Cycle Datapath Performance

• Opposite performance split of single-cycle datapath+ Short clock period– High CPI

PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

57

Multi-cycle Data-path CPI

• CPI depends on instructions• Branches / Jumps: 3 cycles• ALU: 4 cycles• Stores: 4 cycles• Loads: 5 cycles

• Overall CPI is weighted average

• Example: • 20% loads, 15% stores, 20% branches, 45% ALU

58





CPI= 0.20 * 5 +

59





CPI= 0.20 * 5 + 0.15 * 4 +

60





CPI= 0.20 * 5 + 0.15 * 4 + 0.20 * 3 + 0.45 * 4 = 4.0

61

Multi-cycle Datapath Performance

• Single-cycle• Clock period = 50ns, CPI = 1• Performace = 50 ns/insn

• Multi-cycle• Clock period = 10ns • CPI = (0.2*3+0.2*5+0.6*4) = 4• Performance = 40 ns/insn

• But wait…

62

Multi-Cycle Datapath Performance

• Did not just cut up existing logic into 5 pieces• Also added logic (flip flops)

• So clock period not 1/5 of single cycle, but slightly longer

PC

InsnMem

RegisterFile

SX

s1 s2 dDataMem

a

d

+4

<<2

IR DO

B

A

63

Multi-cycle Datapath Performance

• Single-cycle• Clock period = 50ns, CPI = 1• Performace = 50 ns/insn

• Multi-cycle• Clock period = 12ns• CPI = (0.2*3+0.2*5+0.6*4) = 4• Performance = 48 ns/insn

• Better, but not as exciting…• Can we do better still? • Have our cake (low CPI) and eat it too (high clock frequency)?

64

Clock Period and CPI

• Single-cycle datapath+ Low CPI: 1– Long clock period: to accommodate slowest insn

• Multi-cycle datapath+ Short clock period– High CPI

• Can we have both low CPI and short clock period?– No good way to make a single insn go faster+ Insn latency doesn’t matter anyway … insn throughput matters• Key: exploit inter-insn parallelism

insn0.fetch, dec, execinsn1.fetch, dec, exec

insn0.decinsn0.fetchinsn1.decinsn1.fetch

insn0.execinsn1.exec

65

Pipelining

• Pipelining: important performance technique• Improves insn throughput rather than insn latency• Exploits parallelism at insn-stage level to do so• Begin with multi-cycle design

• When insn advances from stage 1 to 2, next insn enters stage 1

• Individual insns take same number of stages+ But insns enter and leave at a much faster rate• Physically breaks “atomic” VN loop ... but must maintain illusion

• Revisit at end of semester (hopefully)

insn0.decinsn0.fetchinsn1.decinsn1.fetch

insn0.execinsn1.exec

insn0.decinsn0.fetchinsn1.decinsn1.fetchinsn0.exec

insn1.exec

66

Summary

• Datapaths:• Single Cycle

• What do we need?• Control• How control is implemented

• Multi-cycle• Faster clock (yay!)• Worse CPI (boooo)

• Performance:• IPC• Performance / Watt• CPU Performance Equation

• Pipelining• Teaser for later!

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