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ECE103 Digital Logic Design L T P C3 0 2 4

Version No.: 1.10Prerequisite: ECE101 Electron Devices and CircuitsObjectives:

Establish a strong understanding of the principles of Digital Design.Provide Understanding of number systems and Boolean algebra.Represent logical functions in Canonical form and standard forms.Develop the Knowledge of combinational and sequential circuits design.Enable the student to design and implement their circuitsExpected Outcome:1. An ability to understand the basic number systems used in digital design2. An ability to understand the basic principles of Boolean algebra3. An ability to design and analyze combinational logic and sequential logic digital circuits4. Develop state diagrams and algorithmic state machine charts methods of minimization of

next state transition tables, and strategies for state assignment.

5. An ability to design and analyze finite state machines.6. An ability to design and implement Combinational and Sequential circuits using PLAs.Unit I Number systems and Boolean algebra 3 hoursBrief review of Digital systems, Binary numbers, Number base conversions, Representation ofNegative Numbers, Complements, Binary arithmetic, Binary Codes for Decimal Numbers.Basic Definitions, Axiomatic Definition of Boolean Algebra, Basic Theorems and Properties ofBoolean Algebra, Boolean Functions, Canonical and Standard Forms, Digital Logic Gates andtiming concepts.Unit II Gate-Level Minimization 4 hours

The Map Method - K-map 4 variable, Product of Sums Simplification, NAND and NORImplementation, Other Two-Level Implementations. Review of , RTL, DTL, TTL, ECL, CMOS

families.Unit III VerilogHDL Coding Style 8 hoursLexical Conventions - Ports and ModulesOperators - Gate Level Modeling - System Tasks &Compiler Directives - Test Bench - Data Flow Modeling - Behavioral level Modeling -Tasks &Functions.Unit IV Design and Modeling of Combinational Logic Circuits using

Verilog15 hours

Analysis Procedure, Design Procedure, Binary Adder-Subtractor, Parallel Adder, Carry lookAhead Adder, Binary Multiplier, Code Converters-Binary to Gray, Gray to Binary, BCD toExcess-3 Code Conversion and vice versa, BCD to 7-segment code converter, MagnitudeComparator-4 bit, Decoders, Encoders, Multiplexers, De-multiplexer, Parity generator and

checker.Modeling of above combinational circuits using Verilog.Unit V Sequential Logic 15 hoursLatches, Flip-Flops-SR, D, JK & T, realization of FFs, synchronous and asynchronous sequentialcircuits-State table and state diagrams, State reduction, Shift Registers-SISO, SIPO, PISO,PIPO,Design of counters-Modulo-n, Johnson, Ring, Up/Down, Design of Serial Adder, SerialMultiplier, FSM, Mealy and Moore state machines - State minimizationSequence detection.Modeling of above sequential circuits using Verilog.

Textbooks1. M. Morris Mano, "Digital Design", 4thEdition, Prentice Hall of India Pvt. Ltd., 2012.2. Samir Palnitkar,Verilog HDL: A Guide to Digital Design and Synthesis Prentice Hall,

Second Edition, 2009.

Proceedings of the 29th Academic Council [26.4.2013] 326

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Reference Books1. Charles H. Roth, Jr., "Fundamentals of Logic Design", 6 thEdition, Brooks/Cole, 2009.2. Thomas L. Floyd & R P Jain, Digital Fundamentals, PHI, 10thEdition, 2009.3. Ronald J Tocci & Neal S. Widmer, Digital Systems, Principles and Applications,

10thedition, Pearson education, 2009.

4. Ronald J. Tocci & Neal S. Widmer, Digital Systems, Principles and Frank Vahid, DigitalDesign, John Wiley and Sons, 2007.

Mode of Evaluation: CAT- I & II, Quizzes, Assignments/ other tests, Term EndExamination.

ECE103 Digital Logic Design Lab

Prerequisite: ECE101 Electron Devices and Circuits

List of Experiments:1. Verification of logic gates2. Design of HA, FA, HS, FS.3. MUX and De-MX (SOP, POS-Minimization)4. Encoder and Decoder5. Parity Generator and checker6. Code Converters.7. Verification of Flip Flops.

Software experiments ( Altera Quartus-II and Model Sim)

8. Modeling of HA, FA, HS, FS, MUX ,De-MUX, Encoder, Decoder and FF9. Shift Registers and their types.10.

Counters and their typed.

11.Design of Sequential Circuit.12.Sequence Detector.

Proceedings of the 29th Academic Council [26.4.2013] 327