ece122_lab1 tanner tutorial
TRANSCRIPT
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ECE122 – Digital Electronics & Design
Tanner Tools Tutorial
Ritu Bajpai
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Objective of the lab
To develop an understanding of design and simulation of digital logic circuits.
To get a basic understanding of layout of electronic circuits.
We will use Tanner tools for design and simulation.
This lab introduces us to Tanner tools.
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Introduction to Tanner tools
Tanner tool- simulation tool for the class
Upgraded from last year Some slides may look different as you
will see on your computer Slides will be updated to correspond
with the new version of Tanner as we advance into the semester
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Tanner tools consists of the followingL-Edit: Layout editing
LVS: Layout vs. Schematic
S-Edit: Schematic Entry
T-Spice: Simulation
W-Edit: Waveform formatting
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This is S-Edit
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For creating new design go
File->New->New design
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Enter design name and the folder name where you want to save your work.
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Recommendations
Make a new folder in your name and always save all your work there.
Use same system each time so that you don’t have to transfer your old files to another system if needed.
Create a backup of your work if needed as the lab computers are formatted from time to time.
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Now go to Cell->New View
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Hit OK to start with new cell schematic design
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Levels of design in S-Edit The highest level in the S-Edit design
hierarchy is the design file. Files contain modules, which can contain primitive objects or reference to other modules.
A module can further have pages. S-Edit has 2 viewing modes, Schematic
mode and Symbol mode. We can switch between 2 modes using the tabs in the tool bar or using a question mark (?).
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Select tool Draw wire
Cap Node
Label Node
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For more help with S-Edit go to
Help->Tutorial
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Library file path
C:\Documents and Settings\Student\My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_200nm\Generic_200nm.tanner
Click here to add libraries
Browse the library file from the path above and hit OK
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Now we will instance first element NMOS from the library Devices and hit done.
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Some useful tips To move an object: Use center wheel of
the mouse. For zoom in and zoom out use + and –
respectively from the key board. To view/edit object properties, select
object and use CTRL+E. Do not use space in your design
names. Do not use special characters in port
names.
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Introduction to MOSFET A MOSFET can be
• PMOS
• NMOS A MOSFET is a four terminal device.
Four terminals are:• Gate
• Drain
• Source
• Bulk A MOSFET is symmetrical device
unlike a BJT which means either terminal can be drain or source unless connected in a circuit.
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Introduction to MOSFET
For a PMOS source is always connected to highest voltage in the circuit.
For an NMOS source is always connected to lowest voltage in a circuit.
The bulk is always shorted to the source for both devices.
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Introduction to MOSFET The bulk terminal is identified by an
arrow. We can distinguish PMOS symbol from
NMOS symbol as follows:• PMOS bulk has arrow coming out .
• NMOS bulk has arrow going in. (Tip: remember ‘in’ sounds like N.)
• PMOS gate has a bubble attached to it. There can be different symbols for
PMOS and NMOS for example the bulk may not be shown but the above points hold good for the MOSFETS we will be using from SCMOS library in S-Edit.
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Schematic design of an inverter
Today we will design an inverter schematic in S-Edit.
In this class we will design CMOS based logic circuits.
Thus an inverter consists of a PMOS and an NMOS connected in series with PMOS source connected to Vdd and NMOS source connected to Gnd.
Input is applied at the gates. Output is collected from the drains
which are connected together.
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Vdd from library Misc
Gnd from library Misc
PMOS from library Devices
Input portOutput port
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Now we are ready to create a symbol for the schematic design
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Draw the symbol of the module which clearly represents the function if possible.
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Create a new design file just as you did for inverter now to make the schematic for the inverter test bench.
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Add libraries and make sure you also add inverter as a library so that you can instance it.
Voltage sources from spice elements
library
Print voltage probe from spice commands
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Voltage source properties can be modifies from here
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Now we will set up the simulation settingsClick to pop up the set up window
Browse the library file
My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_200nm_Tech\Generic_200nm.lib TT
Select Transient/Fourier analysis
Hit OK and click the green play button on the top left
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Types of analysis
DC Operating Point Analysis. DC Transfer Analysis. Transient Analysis. AC Analysis. Transient Analysis, Powerup Mode. Noise Analysis.
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Types of analysis
DC operating point analysis: It finds the circuit’s steady-state condition, obtained (in principle) after the input voltages have been applied for an infinite amount of time.
DC Transfer Analysis: It is used to study the voltage or current at one set of points in a circuit as a function of the voltage or current at another set of points. This is done by sweeping the source variables over specified ranges, and recording the output.
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Types of Analysis Transient Analysis: It provides
information on how circuit elements vary with time.
AC Analysis: It characterizes the circuit’s behavior dependence on small signal input frequency.
Transient Analysis power up mode: Some circuits do not have a DC steady state so it is difficult to specify there initial state. This is done using power up option of the .tran command. It sets entire circuit to zero for time equal to 0.
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Propagation Delay Propagation Delay is the amount of time
it takes a change of input to appear as a change on the output.
Propagation Delay is measured from the 50% point on the input signal to the 50% point on the output.
Input
Output
tpHL
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Transition time
High-low and low high transition times at the output of a gate are defined as tHL and tLH between the 10% and 90% points.
tLH
10%90%
tHL
10%90%
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Gate Delay
The load capacitance severely affects the gate delay.
Inv1
Inv2
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Simulating NAND gate
Next we will make a NAND gate using p and n MOSFET and test its performance.
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Note parameters W=2.50u and L=0.25u
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NAND GATE
TEST BENCH FOR THE NAND GATE
NAND GATE
TEST BENCH FOR NAND GATE
NAND GATE
TEST BENCH FOR NAND GATE
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tpHL
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Record the propagation delay
Record tpHL and tpLH for the NAND gate.
Record the waveform for the same.
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Lab Reports
Strictly adhere to the lab report format and other instructions on the website
No late submissions without prior permission