--------------------

ECE2020 Final Exam Summer 2013 GTL July 31 2013 Name

Show your work for any possible partial credit 100 possi ble points 12 exam pages plus a figure

High Level Language I

I Assembly Language

Instruction Set

Memory Data Path Contro ller

Storage Functional

Units Building Blocks

State

Machinfs

Gate

Switches and Wires

J) (6 Points) Three incomplete circuits are shown below Complete each circuit by adding the needed switching network so the output is pLdled high or low for all combinations of inputs (ie no floats or sI101ts) Complete each circuit (pull down pull up or both) and write the expression if one is Dot given Assume both inputs and complements are available

E

F

H ~

fI _

~ -I

L -

Outl = _ c_A_( _D_+_f----)__ Out2 = _ E_ Cr_+-_F_ _+_ h_ P_ Out3 = D (A + B + C ) E

--------------------------

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functio na l State

_Units Machines Building Blocks

Gate

Switches and Wires

2) (5 points) Implement the following expression using only NOR gates and inverters Then determine the

number of switches required Use proper mixed logic notation Do not modify the expression Do not

assume compliments of inputs are available

Out = (A B + C) D + E) F

A

~S

c

~0 ts

Chl r

F

2

Number of switches

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Units

State

Machines Build BIodcs

Gate

Switches and Wires

3) (5 points) Using only the devices below implement a two-to-one mux on the diagram below (The

block diagram of a 2 to 1 mux is show above just as an FYI only)

InO

In

Select

3

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Stor Functional

llnitlt

State

Machines Building Blocks

Gate

Switches a nd Wires

In Oot

Latch

En

elkl

4) (5 points) Using a two-to-one mux implement a transparent latch using basic gates (NAND NOR

AND OR NOT pass) Enable here is an active high write enable (The block diagram of a transparent

latch is show above just as an FYI only)

Try to minimize transistors

Input Output

Enable

4

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storaae Functional

Units

State

Machines Building Blocks

Gate

Switches a nd Wires

5) (8 points) Consider the register implementation below

Assume the following signals are applied to the register above Draw the signal at point A (output of the

first latch) the signal at point OUT (output of second latch) Assume A and OUT start at logic unknown

values

I

Clkl

Clk2

WE I ILJJ LSLJ IN

I I

A 7V U L in I

OUT

I I

5

High Level Language

Assembly Language

I nstruction Set

Memory Data Path Controller

Storage Functional Un

State

Machi~s Building Blocks

Gate

Switches a nd Wires

6) a)(5 points) Complete the truth table below to the left for a full adder as shown below on the right

x Y C in Sum CarrYouI

() 0 C 0 0 x cin

0

() 0 I D 0 0

sum 0 0 I y cout l 0 0 C

0 0

I I 0 0

b) (10 Points) Using four of the full adder blocks shown above to the right show how four of them would

be used to implement a four bit adder that would be able to addsubtract two four bit numbers Your

inputs are X3 X2 Xl XO Y3 Y2 YI YO addsub S3 S2 S I SO You may use any additional logic

gate types you want Draw your hardware diagram below

c7-0 shy X -SU M Sb11)

1 ( u Ishy

)L c Su m

~ gt

1 c~ vt-

Colshy)lt)2shy ou SL

ttlshy c ~r

cshyYX l ~Ufl S3~3 iV 4l r

1k11tub C Oli t

6

--------------------------

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functio na l State

_Units Machines Building Blocks

Gate

Switches and Wires

2) (5 points) Implement the following expression using only NOR gates and inverters Then determine the

number of switches required Use proper mixed logic notation Do not modify the expression Do not

assume compliments of inputs are available

Out = (A B + C) D + E) F

A

~S

c

~0 ts

Chl r

F

2

Number of switches

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Units

State

Machines Build BIodcs

Gate

Switches and Wires

3) (5 points) Using only the devices below implement a two-to-one mux on the diagram below (The

block diagram of a 2 to 1 mux is show above just as an FYI only)

InO

In

Select

3

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Stor Functional

llnitlt

State

Machines Building Blocks

Gate

Switches a nd Wires

In Oot

Latch

En

elkl

4) (5 points) Using a two-to-one mux implement a transparent latch using basic gates (NAND NOR

AND OR NOT pass) Enable here is an active high write enable (The block diagram of a transparent

latch is show above just as an FYI only)

Try to minimize transistors

Input Output

Enable

4

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storaae Functional

Units

State

Machines Building Blocks

Gate

Switches a nd Wires

5) (8 points) Consider the register implementation below

Assume the following signals are applied to the register above Draw the signal at point A (output of the

first latch) the signal at point OUT (output of second latch) Assume A and OUT start at logic unknown

values

I

Clkl

Clk2

WE I ILJJ LSLJ IN

I I

A 7V U L in I

OUT

I I

5

High Level Language

Assembly Language

I nstruction Set

Memory Data Path Controller

Storage Functional Un

State

Machi~s Building Blocks

Gate

Switches a nd Wires

6) a)(5 points) Complete the truth table below to the left for a full adder as shown below on the right

x Y C in Sum CarrYouI

() 0 C 0 0 x cin

0

() 0 I D 0 0

sum 0 0 I y cout l 0 0 C

0 0

I I 0 0

b) (10 Points) Using four of the full adder blocks shown above to the right show how four of them would

be used to implement a four bit adder that would be able to addsubtract two four bit numbers Your

inputs are X3 X2 Xl XO Y3 Y2 YI YO addsub S3 S2 S I SO You may use any additional logic

gate types you want Draw your hardware diagram below

c7-0 shy X -SU M Sb11)

1 ( u Ishy

)L c Su m

~ gt

1 c~ vt-

Colshy)lt)2shy ou SL

ttlshy c ~r

cshyYX l ~Ufl S3~3 iV 4l r

1k11tub C Oli t

6

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Units

State

Machines Build BIodcs

Gate

Switches and Wires

3) (5 points) Using only the devices below implement a two-to-one mux on the diagram below (The

block diagram of a 2 to 1 mux is show above just as an FYI only)

InO

In

Select

3

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Stor Functional

llnitlt

State

Machines Building Blocks

Gate

Switches a nd Wires

In Oot

Latch

En

elkl

4) (5 points) Using a two-to-one mux implement a transparent latch using basic gates (NAND NOR

AND OR NOT pass) Enable here is an active high write enable (The block diagram of a transparent

latch is show above just as an FYI only)

Try to minimize transistors

Input Output

Enable

4

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storaae Functional

Units

State

Machines Building Blocks

Gate

Switches a nd Wires

5) (8 points) Consider the register implementation below

Assume the following signals are applied to the register above Draw the signal at point A (output of the

first latch) the signal at point OUT (output of second latch) Assume A and OUT start at logic unknown

values

I

Clkl

Clk2

WE I ILJJ LSLJ IN

I I

A 7V U L in I

OUT

I I

5

High Level Language

Assembly Language

I nstruction Set

Memory Data Path Controller

Storage Functional Un

State

Machi~s Building Blocks

Gate

Switches a nd Wires

6) a)(5 points) Complete the truth table below to the left for a full adder as shown below on the right

x Y C in Sum CarrYouI

() 0 C 0 0 x cin

0

() 0 I D 0 0

sum 0 0 I y cout l 0 0 C

0 0

I I 0 0

b) (10 Points) Using four of the full adder blocks shown above to the right show how four of them would

be used to implement a four bit adder that would be able to addsubtract two four bit numbers Your

inputs are X3 X2 Xl XO Y3 Y2 YI YO addsub S3 S2 S I SO You may use any additional logic

gate types you want Draw your hardware diagram below

c7-0 shy X -SU M Sb11)

1 ( u Ishy

)L c Su m

~ gt

1 c~ vt-

Colshy)lt)2shy ou SL

ttlshy c ~r

cshyYX l ~Ufl S3~3 iV 4l r

1k11tub C Oli t

6

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Stor Functional

llnitlt

State

Machines Building Blocks

Gate

Switches a nd Wires

In Oot

Latch

En

elkl

4) (5 points) Using a two-to-one mux implement a transparent latch using basic gates (NAND NOR

AND OR NOT pass) Enable here is an active high write enable (The block diagram of a transparent

latch is show above just as an FYI only)

Try to minimize transistors

Input Output

Enable

4

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storaae Functional

Units

State

Machines Building Blocks

Gate

Switches a nd Wires

5) (8 points) Consider the register implementation below

Assume the following signals are applied to the register above Draw the signal at point A (output of the

first latch) the signal at point OUT (output of second latch) Assume A and OUT start at logic unknown

values

I

Clkl

Clk2

WE I ILJJ LSLJ IN

I I

A 7V U L in I

OUT

I I

5

High Level Language

Assembly Language

I nstruction Set

Memory Data Path Controller

Storage Functional Un

State

Machi~s Building Blocks

Gate

Switches a nd Wires

6) a)(5 points) Complete the truth table below to the left for a full adder as shown below on the right

x Y C in Sum CarrYouI

() 0 C 0 0 x cin

0

() 0 I D 0 0

sum 0 0 I y cout l 0 0 C

0 0

I I 0 0

b) (10 Points) Using four of the full adder blocks shown above to the right show how four of them would

be used to implement a four bit adder that would be able to addsubtract two four bit numbers Your

inputs are X3 X2 Xl XO Y3 Y2 YI YO addsub S3 S2 S I SO You may use any additional logic

gate types you want Draw your hardware diagram below

c7-0 shy X -SU M Sb11)

1 ( u Ishy

)L c Su m

~ gt

1 c~ vt-

Colshy)lt)2shy ou SL

ttlshy c ~r

cshyYX l ~Ufl S3~3 iV 4l r

1k11tub C Oli t

6

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storaae Functional

Units

State

Machines Building Blocks

Gate

Switches a nd Wires

5) (8 points) Consider the register implementation below

Assume the following signals are applied to the register above Draw the signal at point A (output of the

first latch) the signal at point OUT (output of second latch) Assume A and OUT start at logic unknown

values

I

Clkl

Clk2

WE I ILJJ LSLJ IN

I I

A 7V U L in I

OUT

I I

5

High Level Language

Assembly Language

I nstruction Set

Memory Data Path Controller

Storage Functional Un

State

Machi~s Building Blocks

Gate

Switches a nd Wires

6) a)(5 points) Complete the truth table below to the left for a full adder as shown below on the right

x Y C in Sum CarrYouI

() 0 C 0 0 x cin

0

() 0 I D 0 0

sum 0 0 I y cout l 0 0 C

0 0

I I 0 0

b) (10 Points) Using four of the full adder blocks shown above to the right show how four of them would

be used to implement a four bit adder that would be able to addsubtract two four bit numbers Your

inputs are X3 X2 Xl XO Y3 Y2 YI YO addsub S3 S2 S I SO You may use any additional logic

gate types you want Draw your hardware diagram below

c7-0 shy X -SU M Sb11)

1 ( u Ishy

)L c Su m

~ gt

1 c~ vt-

Colshy)lt)2shy ou SL

ttlshy c ~r

cshyYX l ~Ufl S3~3 iV 4l r

1k11tub C Oli t

6

High Level Language

Assembly Language

I nstruction Set

Memory Data Path Controller

Storage Functional Un

State

Machi~s Building Blocks

Gate

Switches a nd Wires

6) a)(5 points) Complete the truth table below to the left for a full adder as shown below on the right

x Y C in Sum CarrYouI

() 0 C 0 0 x cin

0

() 0 I D 0 0

sum 0 0 I y cout l 0 0 C

0 0

I I 0 0

b) (10 Points) Using four of the full adder blocks shown above to the right show how four of them would

be used to implement a four bit adder that would be able to addsubtract two four bit numbers Your

inputs are X3 X2 Xl XO Y3 Y2 YI YO addsub S3 S2 S I SO You may use any additional logic

gate types you want Draw your hardware diagram below

c7-0 shy X -SU M Sb11)

1 ( u Ishy

)L c Su m

~ gt

1 c~ vt-

Colshy)lt)2shy ou SL

ttlshy c ~r

cshyYX l ~Ufl S3~3 iV 4l r

1k11tub C Oli t

6

7) ( 10 points total) State machine problem straight from the practice problems

Strik State fvlachiuo

ouw de-i lI iu H lta- hall J 1 middot l llHU d A ul jJlltJhleIU lrl I t plnn tlad Jf l ik aw l [ jIL qtnk OLlurS I Iwu t ill lm l P in ~ a l (114 Illlll 111 d tu lt U Idl 11 dll lJlItt j UI ) - II 1 I iLl iI

ljo(d pilei If it lI art lJ eUJl t h l PC stril~ durlug w i lar l1Irtl al r Il~J tmiddot j W( U 11 r Vitll lt

lieu l lll hmt I L it tl lt hrlH I lllt Llw lliltl dOI- I I t lilw l in 1JU l l lflLl1r will an VUlltl ] il ~ like ul lril rbi IHII Ll t iU I - lIt) -ITiklmiddot Tlto fUll t alt 19n oHoI Thl T llle din n lJlud ~ vljJllU t ll-I I ult--

Iw llull llJpu luJh-a e- lwi 11 I a ~tfikfI J ot fl fllll l 01 urrcc dl11l11g tIIuJ d ck eyrie T he gt tikl am] fuul iUPUl liLUrJ 1 (J1(IU tumlum lvo ) 1( JUlJlLIl (r IIi- b to d n t C[lle

mill (

P aJt A I [io h lH I (l ingraJI Hl1O lapiN It -lilt ailll for [lib Jirlgrlllll Th~ ItJp ut are ~1I Lkf It ll nd _ talC bi t I ltluI Sa TIl IU lPU ill next Ernle igti[ laud J 0 uII I nuL

~ I So strlk~ f (JIll N51 ASo uut n tJ 4l 1)

0 0 C

I) I ) IJ 1 0 I 0

n ) 1 n C t 0

V 1 1~ Il 0 I C

0 1 0 I I 0 0

11 1 ] I)

I 0 0

1 ) n n I ~ Q

1 IJ U 1 I 0 C

] IJ 1 n 0 0 I

7

art B DLtftJl i III Ll r -iml) lili l1 logical r xpl l I 11 fur S I S S ilia] (lui llSiJJ~ ytJm tte Lal ti l il IHI t mapl l f bt 1~ lL[IlUllgb lUIlP- bel IV idlmif rbe prlmc iln pI ill bull iUII) e Jl C L1 l1 11111t

I -- ----------~~~--~~~__----~~~--------~~~=_------------- Y (I ____ 5~middot st i ItA p ~ + S -Sa fovl + gt1 -50 S-trIt~- --=-l----=-=-________________________------_______________

S S-t rt ~ IJIj t - ________-________=-___________________________________________

art IUlplt-mclJ[ L1lt- lIH I rllllddll( I lu eJ p l tOi l flout IU) [ n (tit lIV( ) lcgill tH~ l fllJ

iton fUl a otl4 hit r(~ l-l rdL Y II do not lw t how th e imp l JU li t ri II l f iI r ~i It l LN (lOr 10 ir woul hf impl ifir d

)

5cht 51ItSSo

of

SO SmiddotU-PA

~~

L

out

~~ 0 0 0 0 strike

~- 0 ~ 10 I

0 )l ilt IC

0 () C -v- ~ ~~ --

fuUI foul foul fool frot fOUl S ~ $tr~~ +- Stl -t0l -t- S~ S-t~

~

I I

1 f

8

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Unit

State

Machines Building Blocks

Gate

Switches and Wires

8) (6 points) SIMM Memory System

Using SIMMs that are 8 million addresses by 8 bit words

Part A Suppose that these SIMMS are used to build a 16 million address memory system with 8 bit

words Using however many of these SIMMs you need draw this memory system In the drawing you

make below add as many SIMM chips as you need and then be sure you label the memory system inputs

Addr RIW and Mem Sel and the systems outputs DO Dl D2 etc Also label bus widths and inputs and

outputs of any required decoders Put a star on the chip(s) containing the memory location addressed

by an address containing a one followed all zeros (all of the address bits are input as a zero except tbe most significant bit which is a one) 9 VI =) e Z 10 - 2 3 2h 2 2 3

mSo

~~ Addr DO

i-shy RW CS 07 I-

e

1()~ l-J )b

I-shy

1shy tVugt lt s D1

9

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Ilnitlt

State

~chines Building Blocks

Gate

Switches and Wires

9) Using the attached single cycle datapath we have discussed extensively in class (see last page of exam

for part of it) implement the microcode for the following instructions (see instruction examples also on

last page)

a) (5 points) addi $3 $225

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

I rl

-w

msel description

1 1shy X 3 I l~ I 0 0 y))X 0 ~I 0 D )( 13 =21-s

b) (5 points) sw$1($2)

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

rI

-w

msel description

1 2 t ~ 0 0 X () X 0 XI (j 1 0 I C) I ~~0i1 [~ 2l t I

c) (5 points) Thinking about the putting it all together system block diagram Which bit fields in the part

(a) microcode you wrote above would be stored in a Read Only Memory controller For those fields not

stored in the Read Only memory controller where would they come from

Ftgt12- l)1)l NO )IE

tu TA1 Nep I N -~ pCTvpoLoFshy

10rd-L OTJIYl- SI6-NIIL~ (rwe) ill ~ 4lA gt 0+-() ltIAO O~ ~ o(fI aY~ I ~OT~II-I

- - -- - - - - - -- - - -- - - - - - - -- - - --

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

lInits

State

Mchinps Building Blocks

Gate

Switches and Wires

10) ( 5 points) Instruction Fonnat For the third instruction type we discussed the Immediate Instruction

Fonnat show the actual 32 bits for the instruction

addi $10 $84

assuming the opcode for addi is 00] 000

tTNtllCO pI V-VE 4shy~Opt-vI) f -X

~ l 0 0 0 6 000 0 D60 00 00 o oot) 0 I 00D o 0 - - ---

11

9) Assembly language progranuning

Consider the following MIPS program fragment The attached last exam page lists the instruction set and

explains them with examples

addl~ss labtl insh11CtiOll 1000 st art a ddi $1 $ 0 300

1004 lw $2 ($1)

1008 l oop a d d i $1 $ 1 4

1012 lw $4 ($1)

1016 sI t $ 3 $2 $ 4

1020 b eq $ 3 $Oskip l

1 024 add $2 $0$ 4

1 028 s k i p1 s lti $ 3 $ 1 324

1032 b ne $ 3 $0 loop

10 36 a d d $5 $0 $ 2

Assume memory holds the following starting at address 300

Part a) (5 points) How many words of data are read in by the program fragment

- INCIViIVCTotal number of data words read T

Part b) (5 points) How many times is the add instruction at address 1024 executed

Number of times 4shy

Part c) (5 points) What are the values in the following registers at the end of the program fragment

$1= S z+-shy$2 = 1() $3 = 0

$4 = 10

$5 = 0

Part d) (5 points) What does this program fragment do

IJ 12

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

13

art B DLtftJl i III Ll r -iml) lili l1 logical r xpl l I 11 fur S I S S ilia] (lui llSiJJ~ ytJm tte Lal ti l il IHI t mapl l f bt 1~ lL[IlUllgb lUIlP- bel IV idlmif rbe prlmc iln pI ill bull iUII) e Jl C L1 l1 11111t

I -- ----------~~~--~~~__----~~~--------~~~=_------------- Y (I ____ 5~middot st i ItA p ~ + S -Sa fovl + gt1 -50 S-trIt~- --=-l----=-=-________________________------_______________

S S-t rt ~ IJIj t - ________-________=-___________________________________________

art IUlplt-mclJ[ L1lt- lIH I rllllddll( I lu eJ p l tOi l flout IU) [ n (tit lIV( ) lcgill tH~ l fllJ

iton fUl a otl4 hit r(~ l-l rdL Y II do not lw t how th e imp l JU li t ri II l f iI r ~i It l LN (lOr 10 ir woul hf impl ifir d

)

5cht 51ItSSo

of

SO SmiddotU-PA

~~

L

out

~~ 0 0 0 0 strike

~- 0 ~ 10 I

0 )l ilt IC

0 () C -v- ~ ~~ --

fuUI foul foul fool frot fOUl S ~ $tr~~ +- Stl -t0l -t- S~ S-t~

~

I I

1 f

8

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Unit

State

Machines Building Blocks

Gate

Switches and Wires

8) (6 points) SIMM Memory System

Using SIMMs that are 8 million addresses by 8 bit words

Part A Suppose that these SIMMS are used to build a 16 million address memory system with 8 bit

words Using however many of these SIMMs you need draw this memory system In the drawing you

make below add as many SIMM chips as you need and then be sure you label the memory system inputs

Addr RIW and Mem Sel and the systems outputs DO Dl D2 etc Also label bus widths and inputs and

outputs of any required decoders Put a star on the chip(s) containing the memory location addressed

by an address containing a one followed all zeros (all of the address bits are input as a zero except tbe most significant bit which is a one) 9 VI =) e Z 10 - 2 3 2h 2 2 3

mSo

~~ Addr DO

i-shy RW CS 07 I-

e

1()~ l-J )b

I-shy

1shy tVugt lt s D1

9

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Ilnitlt

State

~chines Building Blocks

Gate

Switches and Wires

9) Using the attached single cycle datapath we have discussed extensively in class (see last page of exam

for part of it) implement the microcode for the following instructions (see instruction examples also on

last page)

a) (5 points) addi $3 $225

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

I rl

-w

msel description

1 1shy X 3 I l~ I 0 0 y))X 0 ~I 0 D )( 13 =21-s

b) (5 points) sw$1($2)

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

rI

-w

msel description

1 2 t ~ 0 0 X () X 0 XI (j 1 0 I C) I ~~0i1 [~ 2l t I

c) (5 points) Thinking about the putting it all together system block diagram Which bit fields in the part

(a) microcode you wrote above would be stored in a Read Only Memory controller For those fields not

stored in the Read Only memory controller where would they come from

Ftgt12- l)1)l NO )IE

tu TA1 Nep I N -~ pCTvpoLoFshy

10rd-L OTJIYl- SI6-NIIL~ (rwe) ill ~ 4lA gt 0+-() ltIAO O~ ~ o(fI aY~ I ~OT~II-I

- - -- - - - - - -- - - -- - - - - - - -- - - --

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

lInits

State

Mchinps Building Blocks

Gate

Switches and Wires

10) ( 5 points) Instruction Fonnat For the third instruction type we discussed the Immediate Instruction

Fonnat show the actual 32 bits for the instruction

addi $10 $84

assuming the opcode for addi is 00] 000

tTNtllCO pI V-VE 4shy~Opt-vI) f -X

~ l 0 0 0 6 000 0 D60 00 00 o oot) 0 I 00D o 0 - - ---

11

9) Assembly language progranuning

Consider the following MIPS program fragment The attached last exam page lists the instruction set and

explains them with examples

addl~ss labtl insh11CtiOll 1000 st art a ddi $1 $ 0 300

1004 lw $2 ($1)

1008 l oop a d d i $1 $ 1 4

1012 lw $4 ($1)

1016 sI t $ 3 $2 $ 4

1020 b eq $ 3 $Oskip l

1 024 add $2 $0$ 4

1 028 s k i p1 s lti $ 3 $ 1 324

1032 b ne $ 3 $0 loop

10 36 a d d $5 $0 $ 2

Assume memory holds the following starting at address 300

Part a) (5 points) How many words of data are read in by the program fragment

- INCIViIVCTotal number of data words read T

Part b) (5 points) How many times is the add instruction at address 1024 executed

Number of times 4shy

Part c) (5 points) What are the values in the following registers at the end of the program fragment

$1= S z+-shy$2 = 1() $3 = 0

$4 = 10

$5 = 0

Part d) (5 points) What does this program fragment do

IJ 12

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

13

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Unit

State

Machines Building Blocks

Gate

Switches and Wires

8) (6 points) SIMM Memory System

Using SIMMs that are 8 million addresses by 8 bit words

Part A Suppose that these SIMMS are used to build a 16 million address memory system with 8 bit

words Using however many of these SIMMs you need draw this memory system In the drawing you

make below add as many SIMM chips as you need and then be sure you label the memory system inputs

Addr RIW and Mem Sel and the systems outputs DO Dl D2 etc Also label bus widths and inputs and

outputs of any required decoders Put a star on the chip(s) containing the memory location addressed

by an address containing a one followed all zeros (all of the address bits are input as a zero except tbe most significant bit which is a one) 9 VI =) e Z 10 - 2 3 2h 2 2 3

mSo

~~ Addr DO

i-shy RW CS 07 I-

e

1()~ l-J )b

I-shy

1shy tVugt lt s D1

9

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Ilnitlt

State

~chines Building Blocks

Gate

Switches and Wires

9) Using the attached single cycle datapath we have discussed extensively in class (see last page of exam

for part of it) implement the microcode for the following instructions (see instruction examples also on

last page)

a) (5 points) addi $3 $225

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

I rl

-w

msel description

1 1shy X 3 I l~ I 0 0 y))X 0 ~I 0 D )( 13 =21-s

b) (5 points) sw$1($2)

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

rI

-w

msel description

1 2 t ~ 0 0 X () X 0 XI (j 1 0 I C) I ~~0i1 [~ 2l t I

c) (5 points) Thinking about the putting it all together system block diagram Which bit fields in the part

(a) microcode you wrote above would be stored in a Read Only Memory controller For those fields not

stored in the Read Only memory controller where would they come from

Ftgt12- l)1)l NO )IE

tu TA1 Nep I N -~ pCTvpoLoFshy

10rd-L OTJIYl- SI6-NIIL~ (rwe) ill ~ 4lA gt 0+-() ltIAO O~ ~ o(fI aY~ I ~OT~II-I

- - -- - - - - - -- - - -- - - - - - - -- - - --

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

lInits

State

Mchinps Building Blocks

Gate

Switches and Wires

10) ( 5 points) Instruction Fonnat For the third instruction type we discussed the Immediate Instruction

Fonnat show the actual 32 bits for the instruction

addi $10 $84

assuming the opcode for addi is 00] 000

tTNtllCO pI V-VE 4shy~Opt-vI) f -X

~ l 0 0 0 6 000 0 D60 00 00 o oot) 0 I 00D o 0 - - ---

11

9) Assembly language progranuning

Consider the following MIPS program fragment The attached last exam page lists the instruction set and

explains them with examples

addl~ss labtl insh11CtiOll 1000 st art a ddi $1 $ 0 300

1004 lw $2 ($1)

1008 l oop a d d i $1 $ 1 4

1012 lw $4 ($1)

1016 sI t $ 3 $2 $ 4

1020 b eq $ 3 $Oskip l

1 024 add $2 $0$ 4

1 028 s k i p1 s lti $ 3 $ 1 324

1032 b ne $ 3 $0 loop

10 36 a d d $5 $0 $ 2

Assume memory holds the following starting at address 300

Part a) (5 points) How many words of data are read in by the program fragment

- INCIViIVCTotal number of data words read T

Part b) (5 points) How many times is the add instruction at address 1024 executed

Number of times 4shy

Part c) (5 points) What are the values in the following registers at the end of the program fragment

$1= S z+-shy$2 = 1() $3 = 0

$4 = 10

$5 = 0

Part d) (5 points) What does this program fragment do

IJ 12

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

13

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

Ilnitlt

State

~chines Building Blocks

Gate

Switches and Wires

9) Using the attached single cycle datapath we have discussed extensively in class (see last page of exam

for part of it) implement the microcode for the following instructions (see instruction examples also on

last page)

a) (5 points) addi $3 $225

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

I rl

-w

msel description

1 1shy X 3 I l~ I 0 0 y))X 0 ~I 0 D )( 13 =21-s

b) (5 points) sw$1($2)

X Y Z rw e

1m

en

1m va au

en

-a

Is lu

en

If su

en

st Id

en

st

en

rI

-w

msel description

1 2 t ~ 0 0 X () X 0 XI (j 1 0 I C) I ~~0i1 [~ 2l t I

c) (5 points) Thinking about the putting it all together system block diagram Which bit fields in the part

(a) microcode you wrote above would be stored in a Read Only Memory controller For those fields not

stored in the Read Only memory controller where would they come from

Ftgt12- l)1)l NO )IE

tu TA1 Nep I N -~ pCTvpoLoFshy

10rd-L OTJIYl- SI6-NIIL~ (rwe) ill ~ 4lA gt 0+-() ltIAO O~ ~ o(fI aY~ I ~OT~II-I

- - -- - - - - - -- - - -- - - - - - - -- - - --

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

lInits

State

Mchinps Building Blocks

Gate

Switches and Wires

10) ( 5 points) Instruction Fonnat For the third instruction type we discussed the Immediate Instruction

Fonnat show the actual 32 bits for the instruction

addi $10 $84

assuming the opcode for addi is 00] 000

tTNtllCO pI V-VE 4shy~Opt-vI) f -X

~ l 0 0 0 6 000 0 D60 00 00 o oot) 0 I 00D o 0 - - ---

11

9) Assembly language progranuning

Consider the following MIPS program fragment The attached last exam page lists the instruction set and

explains them with examples

addl~ss labtl insh11CtiOll 1000 st art a ddi $1 $ 0 300

1004 lw $2 ($1)

1008 l oop a d d i $1 $ 1 4

1012 lw $4 ($1)

1016 sI t $ 3 $2 $ 4

1020 b eq $ 3 $Oskip l

1 024 add $2 $0$ 4

1 028 s k i p1 s lti $ 3 $ 1 324

1032 b ne $ 3 $0 loop

10 36 a d d $5 $0 $ 2

Assume memory holds the following starting at address 300

Part a) (5 points) How many words of data are read in by the program fragment

- INCIViIVCTotal number of data words read T

Part b) (5 points) How many times is the add instruction at address 1024 executed

Number of times 4shy

Part c) (5 points) What are the values in the following registers at the end of the program fragment

$1= S z+-shy$2 = 1() $3 = 0

$4 = 10

$5 = 0

Part d) (5 points) What does this program fragment do

IJ 12

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

13

- - -- - - - - - -- - - -- - - - - - - -- - - --

High Level Language

Assembly Language

Instruction Set

Memory Data Path Controller

Storage Functional

lInits

State

Mchinps Building Blocks

Gate

Switches and Wires

10) ( 5 points) Instruction Fonnat For the third instruction type we discussed the Immediate Instruction

Fonnat show the actual 32 bits for the instruction

addi $10 $84

assuming the opcode for addi is 00] 000

tTNtllCO pI V-VE 4shy~Opt-vI) f -X

~ l 0 0 0 6 000 0 D60 00 00 o oot) 0 I 00D o 0 - - ---

11

9) Assembly language progranuning

Consider the following MIPS program fragment The attached last exam page lists the instruction set and

explains them with examples

addl~ss labtl insh11CtiOll 1000 st art a ddi $1 $ 0 300

1004 lw $2 ($1)

1008 l oop a d d i $1 $ 1 4

1012 lw $4 ($1)

1016 sI t $ 3 $2 $ 4

1020 b eq $ 3 $Oskip l

1 024 add $2 $0$ 4

1 028 s k i p1 s lti $ 3 $ 1 324

1032 b ne $ 3 $0 loop

10 36 a d d $5 $0 $ 2

Assume memory holds the following starting at address 300

Part a) (5 points) How many words of data are read in by the program fragment

- INCIViIVCTotal number of data words read T

Part b) (5 points) How many times is the add instruction at address 1024 executed

Number of times 4shy

Part c) (5 points) What are the values in the following registers at the end of the program fragment

$1= S z+-shy$2 = 1() $3 = 0

$4 = 10

$5 = 0

Part d) (5 points) What does this program fragment do

IJ 12

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

13

9) Assembly language progranuning

Consider the following MIPS program fragment The attached last exam page lists the instruction set and

explains them with examples

addl~ss labtl insh11CtiOll 1000 st art a ddi $1 $ 0 300

1004 lw $2 ($1)

1008 l oop a d d i $1 $ 1 4

1012 lw $4 ($1)

1016 sI t $ 3 $2 $ 4

1020 b eq $ 3 $Oskip l

1 024 add $2 $0$ 4

1 028 s k i p1 s lti $ 3 $ 1 324

1032 b ne $ 3 $0 loop

10 36 a d d $5 $0 $ 2

Assume memory holds the following starting at address 300

Part a) (5 points) How many words of data are read in by the program fragment

- INCIViIVCTotal number of data words read T

Part b) (5 points) How many times is the add instruction at address 1024 executed

Number of times 4shy

Part c) (5 points) What are the values in the following registers at the end of the program fragment

$1= S z+-shy$2 = 1() $3 = 0

$4 = 10

$5 = 0

Part d) (5 points) What does this program fragment do

IJ 12

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

13

You may tear this off from the exam and you do not need to turn in this page

Mcipound cvc numb X r drIel onto X bu r tbullme dnltI QDO Y Z k wnlten frow Z bus no re-auter write fDable ilti~iJ -shy __ dible Y bu

imv(i immfOdi tt Vltrut

rwe

register file

32x 32

32

eo

logical functions shift types ltl X y out 0= logical 0 0 u I = arithmetic 1 0 If 2 = rotate Id 0 I If + count shifts right

If - count shifts left

memory

data

r middotlf DlIeI

QlIlti

-a

I l

t ld 71 middott rmiddotw m ol

d nmiddoton

arithmetic unit bl -add i b oad l=w trar io 411 unit uable i c~l funcnOD hiftUDi

ift iad bi t

-tite O wri r

1l1= Ieel 0 ration ri non

initruction example meaWnll add add 91 S S3 Sl = SZ + $3

sublIactI sub 91 S S3 S = o~ ~ - $3

add immediate addi ~1 2 100 s = 0 ~ + lGO

multiply mul Sl$2 S3 $1 - $2 $3

diide d~v $1$253 51 - S2 53 and and Sl $ $ 3 S - 52 amp 5 3 or or 5 J $ 2 $3 $ 1 - 5 I 53 xor xor SlS ~ S3 Sl - $ xo r 53 and immediate andi 61 $2 10a 51 - 52 amp 100 or immediate or 51S 100 Sl - 52 I 10 0 xor immediate xor i $1 $2 1 00 51 = 52 xor 100 rhift left logical s 11 Sl S 5 Sl - $2 laquo 5 (logical )

s1uft right logical s r I 51 5 2 5 S1 = middot2 raquo 5 (lo_g~cal )

shift left arithmtic s 1 a 51$25 5 - 52 laquo 5 lari tmae t il c)

s1uft right arithmetic sra $1$2 5 51 - s raquo 5 (ari thmetic )

load word 1 Sl (5 2) 51 - memory [52]

store word Stgt 51 ($2) me mory 52] - 51 load upper immedit lu i 51 11gt0 51 - 1 0 0 x l ~

-branch if equal beq 51$21 00 if (51 = $2) PC = PC + ~ + (10(4)

branch if not equal bne S l S2 10 0 it (51 S2 ) I PC = PC + 4 + (1004) ~et ifless than s l t SI ~ $3 t if (52 lt 53) 51 = 1 lse s - G set if Iebullbull than inunediate s lt i 51 $2 100 if I~

J_ lt 100 ) 51 - 1 else 51 = 0 jump j 10000 PC - 10000 4 jump register jr $31 PC - 931 jwnp and link jal 10000 S3 1 = PC + 4 PC = 1 0000 4

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