George Mason UniversityECE 448 – FPGA and ASIC Design with VHDL

ASICs vs. FPGAs

ECE 448Lecture 15

2ECE 448 – FPGA and ASIC Design with VHDL

FPGAs vs. ASICs

ASICs FPGAs

High performanceOff-the-shelf

Short time to the market

Low development costs

Reconfigurability

Low power

Low cost (but only in high volumes)

3ECE 448 – FPGA and ASIC Design with VHDL

Local Memory

Global Memory

ASIC Design Example – Factoring circuit/GMU

4ECE 448 – FPGA and ASIC Design with VHDL

51x

ASIC 130 nm vs. Virtex II 6000Factoring/GMU

19.80 mm

19.6

8 m

m

2.7 mm

2.82 mm

Area of Xilinx Virtex II 6000FPGA

(estimation by R.J. Lim Fong, MS Thesis, VPI, 2004)

Area of an ASIC with equivalent functionality

5ECE 448 – FPGA and ASIC Design with VHDL

Source:I. Kuon, J. Rose,

University of Toronto

“Measuring the Gap Between

FPGAs and ASICs”

IEEE Transactions on Computer-Aided

Design of Integrated Circuits and Systems,

vol. 62, no. 2, Feb 2007.

ASICs vs. FPGAs

6ECE 448 – FPGA and ASIC Design with VHDL

23 representative circuits implemented using

FPGAs and ASICs

- computer arithmetic (booth, cordic18, cordic8, etc.)

- digital signal processing (rs_encoder, fir3, fir24, etc.)

- communications (ethernet, mac1, atm, etc.)

- cryptography (des_area, des_perf, aes, aes192, etc.)

- scientific computations (molecular, raytracer, etc.)

ASICs vs. FPGAs

7ECE 448 – FPGA and ASIC Design with VHDL

8ECE 448 – FPGA and ASIC Design with VHDL

9ECE 448 – FPGA and ASIC Design with VHDL

10ECE 448 – FPGA and ASIC Design with VHDL

11

ASIC Design FlowAlgorithm

Specification

RTL DesignVerilog, VHDL

Logic Synthesis

Layout

Parasitic Extraction

stdcell lib

process lib

Simulation

LVS

Simulation

test vectors

VCD

latencythroughput(post-synthesis)

die areapin count

latencythroughput(post P&R)

power diss

Synopsys IC CompilerCadence Encounter

Synopsys Design Compiler

Mentor CalibreSynopsys StarRCXT

VCS

HerculesCalibre

PrimeTime

DesignQuality

Reference Implementation

C, C++

12ECE 448 – FPGA and ASIC Design with VHDL

Simplified ASIC Design Flow

SynthesisSynthesis

PlacementPlacement

Clock Tree SynthesisClock Tree Synthesis

RoutingRouting

FloorplanningFloorplanning

Timing AnalysisTiming Analysis

Design for ManufacturingDesign for Manufacturing

31

Front-End

Design

Back-End

Design

13ECE 448 – FPGA and ASIC Design with VHDL

Major ASIC Toolsets

Cadence

Magma

14ECE 448 – FPGA and ASIC Design with VHDL

Simplified ASIC Design Flow

SynthesisSynthesis

PlacementPlacement

Clock Tree SynthesisClock Tree Synthesis

RoutingRouting

FloorplanningFloorplanning

Timing AnalysisTiming Analysis

Design for ManufacturingDesign for Manufacturing

31

Front-End

Design

Back-End

Design

Synopsys

Tools

Design Compiler

Primetime

Astro

15ECE 448 – FPGA and ASIC Design with VHDL

A Complete Placed and Routed Chip

IP

28

Digital system design technologiescoverage in the CpE & EE programs at GMU

Microprocessors ASICsFPGAs

ECE 445

ECE 447

ECE 586

ECE 681

ECE 448

ECE 511

ECE 611

ECE 431Computer Organization

Single ChipMicrocomputers

FPGA and ASIC Design with VHDL

Digital Circuit Design

Microprocessors

Advanced Microprocessors

Digital Integrated Circuits

VLSI Design for ASICs

ECE 545 Digital System Design with VHDL

ECE 645 Computer Arithmetic

DIGITAL SYSTEMS DESIGN

1. ECE 545 Digital System Design with VHDL– K. Gaj, project, FPGA design with VHDL, Aldec/Xilinx/Altera

2. ECE 645 Computer Arithmetic– K. Gaj, project, FPGA design with VHDL or Verilog,

Aldec/Xilinx/Altera/Synopsys

3. ECE 586 Digital Integrated Circuits – D. Ioannou

4. ECE 681 VLSI Design for ASICs– N. Klimavicz, project/lab, front-end and back-end ASIC design with Synopsys tools

5. ECE 682 VLSI Test Concepts– T. Storey, homework