ece483syllabus

7/28/2019 ece483syllabus

1/4

EE 483/EE 580 Course Syllabus Spring 2001

Instructor: Dr. George Engel

Office: EB3043Phone: (618) 650-2806

E-mail: [email protected]

WWW: http://www.ee.siue.edu/~mentor

http://www.ee.siue.edu/~mentor

Lectures: T R 6:00 pm - 7:15 pm

Course Description:

Principles of computer design and performance evaluation. Implementation of data andcontrol units. Memory, I/O, bus, and operating system issues. Introduction to hardwaredescription languages (VHDL). Review of current processor architectures.

Prerequisites:

EE382 or consent of instructor.

Grading:

Semester grades will be computed as follows:

Exam #1 ............ 20%Exam #2 ............ 20%Exam #3 ............ 20%Lab Exercises and Homework ............ 20%Final Project .............. 20%

Text:

Computer System Architecture: Third Edition Morris ManoPrentice Hall, 1993

Optional (Many VHDL tutorials exist on the WEB so the book is not mandatory)VHDL Made Easy (I personally like the book!)David Pellerin and Douglas TaylorPrentice Hall, 1997


2/4

EE483/EE580 Lecture Schedule For Spring 2001

Jan 09 (T) Ch 1: Review: Combinational and Sequential Logic Design-- Schematic Driven Design ---- Introduction to VHDL --

Jan 11 (R) Ch 2: Review: Digital Components-- A First Look at VHDL --

Jan 16 (T) Ch 3: Review: Number Representations and Systems-- VHDL: Exploring Objects and Data Types-- VHDL: Using Standard Logic

Jan 18 (R) Ch 4: Register Transfer and Micro-operations-- VHDL: Understanding Concurrent Statements-- VHDL: Understanding Sequential Statements

Jan 23 (T) -- VHDL: Creating Modular Designs-- VHDL: Partitioning Your Design-- VHDL: Writing Test Benches

Jan 25 (R) Ch 5: Basic Computer Organization and Design5.1 Instruction Codes5.2 Computer Registers

Jan 30 (T) Ch 5 5.3 Computer Instructions5.6 Memory Reference Instructions

Feb 01 (R) Ch 5: Basic Computer Organization and Design5.4 Timing and Control5.5 Instruction Cycle

Feb 06 (T) Ch 5: Basic Computer Organization and Design5.9 Hardwired Control5.10 Design of Accumulator Logic

Feb 08 (R) Ch 6: Programming the Basic Computer

Feb 13 (T) -- EXAM # 1 --

Feb 15 (R) Behavioral Level VHDL Model of SEP

Feb 20 (T) Ch 7: Microprogrammed Control7.1 Control Memory7.2 Address SequencingDesign of Control Unit

Feb 22 (R) Ch 7: Microprogrammed ControlNanoprogrammingMinimizing the width of control memory

Feb 27 (T) Ch 8: CPU8.2 Register Organization8.3 Stack Organization

Mar 01 (R) Ch 8: CPU8.4 Instruction Formats8.5 Addressing Modes

Mar 06 (T) Ch 8: CPU8.6 Data Transfer and Manipulation


3/4

Mar 08 (R) Ch 8: CPU8.7 Program Control8.8 CISC versus RISC

Mar 13 (T) *** SPRING BREAK ***

Mar 15 (R) *** SPRING BREAK ***

Mar 20 (T) Ch 9: Pipelining9.1 Parallel Processing9.2 Pipeline Concept

Mar 22 (R) Ch 9: Pipelining9.3 Arithmetic Pipeline9.4 Instruction Pipeline

Mar 27 (T) Ch 10: Computer Arithmetic10.2 Addition and Subtraction10.3 Multiplication

Mar 29 (R) -- EXAM # 2 --

Apr 03 (T) Ch 10: Computer Arithmetic

10.3 Multiplication

Apr 05 (R) Ch 10: Computer Arithmetic10.4 Division10.5 Floating-point

Apr 10 (T) Ch 11: I/O Organization11.1 Peripheral Devices11.2 I/O Interface11.3 Asynchronous Data Transfer

Apr 12 (R) Ch 11: I/O Organization11.4 Modes of Transfer11.5 Priority Interrupt

Apr 17 (T) Ch 11: I/O Organization11.6 DMA11.7 I/O Processor11.8 Serial Communications

Apr 19 (R) Ch 12: Memory Organization12.2 Main Memory12.3 Auxiliary Memory12.4 Associative Memory

Apr 24 (T) Ch 12: Memory Organization12.5 Cache Memory12.6 Virtual Memory

Apr 26 (R) Ch 12: Memory Organization12.6 Virtual Memory12.7 Memory Management Hardware


4/4

ece483syllabus

Documents