[ece486] report lab3_group1

8/10/2019 [ECE486] Report Lab3_Group1

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ECE486

REPORT LAB 3

Group 1:

L Vn V An

Ng Thanh Quang

Trn Phc TTm

Class: 11ES


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Table of Contents

I. Introduction .................................................................................................... 3

II.

Implementation .............................................................................................. 3

1. Overview .......................................................................................................... 4

2. Multiplexer 2to1 (5bit) .................................................................................... 5

3. Multiplexer 2to1 (32bit) .................................................................................. 6

4. Module Shift left 2 ........................................................................................... 6

5. Module Extension ............................................................................................ 7

6. Adder 32bit ...................................................................................................... 8

7.

Program Counter .............................................................................................. 8

8. ALU Control .................................................................................................... 9

9. MIPS Controller ............................................................................................. 10

10.How it works .................................................................................................. 12

11.Simulation ...................................................................................................... 12

III.

Conclusion .................................................................................................... 20


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I. Introduction:

In this lab, we implement a MIPS processor (single cycle) by combining the

register file, ALU and some wiring work. Just like the previous reports, we only

show the important parts of the implementation file. Therefore, if you want to seethe parts which are not mentioned in this report, just open our .v files.

The important blocks for this CPU are:

Controller

ALU/ALU control

Registers

Instruction Memory

Data Memory

Instruction and Data memory are already available, not to mention the

implementation of register file and ALU are handled in previous labs. Therefore,

we only need to implement the main controller, ALU control and a few

connections to put all things together.


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II. Implementation:

1. Overview:

The figure above indicates a MIPS processor that is capable of handling the

following instructions: LW, SW, J, BNE, XORI, ADD, SUB, and SLT.

However, according to the requirement, this processor must be able to process

the JR instruction. To solve this problem, we add a few lines and blocks to the

figure above, which is illustrated below.


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Before moving on to the essential blocks which constitute the whole MIPS

processor, lets take a look at the smaller blocks first.

2.

Multiplexer 2to1 (5bit)


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The way to implement this Mux is quite familiar as we already mentioned in the

previous lab. Firstly, we create a Mux2to1. Then by combining 5 of this Mux,

we have a Mux2to1 (5bit).

3. Multiplexer 2to1 (32bit)

It is similar to Mux2to1 (5bit) but with some adjustment. Moving on.

4.

Module Shift left 2

a.

32bit to 32bit:


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b.

26bit to 28bit:

5. Module Extension

a.

Zero extension:

b.

Signed extension:


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6. Adder 32bit:

We already explained thoroughly this module in lab2. Guess further explanation

is not necessary. Lets move on to the crucial blocks.

7. Program Counter:

A program counter is a register in a computer processor that contains the

address (location) of the instruction being executed at the current time.

Note: The Verilog code for D_FF (D flip flop) is in the regfile.v


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8. ALU Control:

Instruction ALUOp Function ALUCtrl

Load/Store 00

X

00 (Add)

XOR 01 01 (Xor)

BNE 10 10 (Sub)

J 10 XX

R

11

100000 00 (Add)

100010 10 (Sub)

101010 11 (SLT)

JR 001000 XX


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9. MIPS Controller:

Basically, this controller handles all the controlling signals for the above blocks

and modules.

We implement the controller based on this table with corresponding values.

Instruction ADD SUB SLT JR LW SW BNE XORI J

RegDst 1 1 1 0 0 x x 0 x

ALUSrc 0 0 0 0 1 1 0 1 x

MemToReg 0 0 0 0 1 x x 0 x

RegWrite 1 1 1 0 1 0 0 1 0

MemRead 0 0 0 0 1 x x x x

MemWrite 0 0 0 0 0 1 0 0 0

Branch 0 0 0 1 0 0 1 0 1

Jump 0 0 0 0 0 0 0 0 1

JumpReg 0 0 0 1 0 0 0 0 0

SignEx 0 0 0 0 1 1 1 0 x

Opcode 0x00 0x00 0x00 0x00 0x23 0x2B 0x05 0x0E 0x02

Funct 0x20 0x22 0x2A 0x08 xx xx xx xx xx


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Note: By applying SOP (Sum of Product) for ALUOp, the value of ALUOp is

as following:

ALUOp[1]: BNE + R + J + JR

ALUOp[0]: XORI + R + JR


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10.How it works:

The explanation of how the MIPS (single cycle) functions is described in detail

in the textbook.

Reference:

MK Computer Organization and Design 5th Edition (Oct 2013) Start with

section 4.

Therefore, it is not necessary to explain it again in this report.

Now we come to an interesting partsimulation.

11.Simulation:

For this section, we will show the illustrations corresponding to specific

instructions handled by the MIPS processor (LW, SW, J, BNE, XORI, ADD,

SUB, and SLT).

To begin with, we would like to start with LW and SW. Since these instructions

have relation to the Data Memory, there is something tricky here.

Take a look at these examples:

sw $13, 0($18)

lw $20, 0($18)

For the MIPS to deal with these instructions, there must have some values in

register $18 which is the address of memory location pointed to.

According to this function call:

To get the value of ReadData, ALUResult and ReadData2 must have values as

well.

Register file is the module that decides whether ReadData2 has value or not.


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Come to this point, we will have two possible situations.

Case #1, Register file is subject to controlling signal reset, whichmeans 31 registers ($0 always has value 0) will have initial value 0.

Case #2, Register file has nothing to do with reset, this means 31registers (except $0) will not have initial value (NULL).

Take a look at the content of instr.dat.

Before the LW and SW instructions, $16, $17 and $18 had not been used. We

can conclude that:

Case #1: MIPS processor will work just fine with LW and SW since $16,

$17 and $18 already have initial value (zero).

Case #2: MIPS processor cannot handle LW and SW instructions as there

is no value in those three registers.

Therefore, for these examples:

sw $13, 0($18)

lw $20, 0($18)


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Only in the case #1, the MIPS processor can work properly with the file

instr.dat for LW, SW instructions since $18 (mentioned above) has initialvalue 0.

Note: We attached two regfile (one with controlling signal reset and anotherdoes not have) so you can use those files respectively to compare the results

between two cases (case #1 and case #2). Remember to adjust the function call

regfile before change the regfile.

a.

Store word (SW):

sw $13, 0($18)

Case #1: $18 has initial value (zero).

ALUOp = ALUCtrl = 2b00 (Store word) ReadRegister1: 16

ReadData1: 0 (initial value)

ReadRegister2: 13

ReadData2: 13

ReadData: 13


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Case #2: $18 has no initial value (NULL).

ALUOp = ALUCtrl = 2b00 (Store word)

ReadRegister1: 16

ReadData1: X

ReadRegister2: 13

ReadData2: X

ReadData: X

b.

Load word (LW):

lw $20, 0($18)

Case #1: $18 has initial value (zero).


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ALUOp = ALUCtrl = 2b00 (Load word)

ReadRegister1: 18

ReadData1: 0 (initial value)

ReadRegister2: 20

ReadData2: 13

ReadData: 13 (since $18 points to the memory location which has

value 13 of register $13.

Case #2: $18 has no initial value (NULL).

ALUOp = ALUCtrl = 2b00 (Load word) ReadRegister1: 18

ReadData1: X

ReadRegister2: 20

ReadData2: X

ReadData: X

c.

Jump (J):

j 0x00400070

In this case, the PC (PC_In) must be 0x00400070 and the instruction will be

0x0810001C.


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ALUOp = 2b10

ALUCtrl = 2b10

d.

Branch on not equal (BNE):

bne $13, $0, 16 [label]

Since $13 != $0, it should jump to the label has PC = 96

label: sw $24, 16($23)


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e.

XORI:

xori $6, $0, 5

ALUOp = ALUCtrl = 2b01 (XORI) ReadRegister1: 0

ReadData1: 0

ReadRegister2: 6

ReadData2 and WriteData to $6: 5

f .

ADD:

add $11, $6, $7

ALUOp = 2b11 ALUCtrl = 2b00

WriteData to $11: 5 + 6 = 11


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g.

SUB:

sub $13, $12, $2

ALUOp = 2b11

ALUCtrl = 2b10

WriteData to $13: 141 = 13

h.

SLT:

slt $21, $2, $0

$2 = 1 while $0 has value zero. Since $2 > $0, $21 will get value 0.

We can see that WriteData to $21 = 0 as expected.


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III.

Conclusion:According to the simulation section, we can conclude that our design for MIPS

single cycle works properly with no problem so far. Although there exist somesignal delay, it still does not affect the overall results.

One thing that causes trouble for us is the file instr.dat. To have our design works

with this file (LW and SW in particular), we have to change our regfile.v a bit and

this is not comfortable.

In brief, we got much experience after handling this lab. We can comprehend

thoroughly how the instructions are dealt with as well as the functions of the

internal parts which constitute the processor.

[ece486] report lab3_group1

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