ecen 610 mixed-signal interfaces - computer engineeringhoyos/courses/610/dacs.pdf · s....
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![Page 1: ECEN 610 Mixed-Signal Interfaces - Computer Engineeringhoyos/courses/610/DACs.pdf · S. Hoyos-ECEN-610 30. Summary • Nyquist DAC architectures – Binary-weighted DAC – Unit-element](https://reader036.vdocument.in/reader036/viewer/2022081505/604c8ae578cfcf16f92b1849/html5/thumbnails/1.jpg)
S. Hoyos-ECEN-610 1
ECEN 610Mixed-Signal Interfaces
Sebastian Hoyos
Texas A&M UniversityAnalog and Mixed Signal Group
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S. Hoyos-ECEN-610 2
DAC Architectures
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S. Hoyos-ECEN-610 3
Binary-Weighted DAC
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S. Hoyos-ECEN-610 4
Binary-Weighted CR DAC
• Binary-weighted capacitor array → most efficient architecture
• Bottom plate @ VR with bj = 1 and @ GND with bj = 0
Cu = unit capacitanceVX
2Cu Cu Cu8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
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S. Hoyos-ECEN-610 5
Binary-Weighted CR DAC
• Cp → gain error (nonlinearity if Cp is nonlinear)• INL and DNL limited by capacitor array
mismatch
Ru
Np
N
1ju
jNjN
RN
1ju
jNup
N
1ju
jNjN
o
VC2C
C2b
VC2CC
C2bV
⋅
+
⋅=
⋅
++
⋅=
∑
∑
∑
=
−−
=
−
=
−−
∑=
⋅⋅
+=
N
1jjj-N
Ru
Np
uN
o 2b
VC2C
C2V
VX
2Cu Cu Cu8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
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S. Hoyos-ECEN-610 6
VX
2Cu Cu
16Cu
8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
A
Stray-Insensitive CR DAC
∑=
+ ⋅⋅
−++
=N
1jjj-N
Ruu
1Np
uN
uN
o 2b
V
ACC2C
C2
C2V
Large A needed to attenuate summing-node charge sharing
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S. Hoyos-ECEN-610 7
MSB Transition
Largest DNL error occurs at the midpoint where MSB transitions, determined by the mismatch between the MSB
capacitor and the rest of the array.
( ) R4
1j
j4p
4o V
C2CC
C1000V ⋅
++=
∑=
−
( ) R4
1j
j4p
321o V
C2CC
CCC0111V ⋅
++
++=
∑=
−
( ) δC,CCCCC :Assume u3214 +=++−
( ) ( )[ ]
uu
oo
CδCC
CC
δC1LSB1LSB0111V1000VDNL
==
−−=
∑∑
Code 0111 Code 1000
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S. Hoyos-ECEN-610 8
Midpoint DNL
• δC > 0 results in positive DNL.• δC < 0 results in negative DNL or even
nonmonotonicity.
δC > 0 δC < 0
Di
Ao
00111 1000
+DNL
Di
Ao
00111 1000
-DNL
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S. Hoyos-ECEN-610 9
Output Glitches
• Glitches cause waveform distortion, spurs and elevated noise floors.
• High-speed DAC output is often followed by a de-glitching SHA.
• Cause: Signal and clock skew in circuits
• Especially severe at MSB transition where all bits are switching –0111…111 →1000…000
Time
Vo
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S. Hoyos-ECEN-610 10
De-Glitching SHA
Time
Vo
DAC...
b1
bN
VoSHA
SHA output must be smooth (exponential settling can be viewed as pulse shaping → SHA BW does not have to be
excessively large).
SHA samples the output of the DAC after it settles and then hold it for T, removing the glitching energy.
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S. Hoyos-ECEN-610 11
Frequency Response
f
|H(f)|
0 fs 2fs 3fs
SHA
ZOH
HZOH jω( )= e− jωT
2 ⋅sin ωT
2( )ωT
2
HSHA jω( )=1
1+ jωω−3dB
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S. Hoyos-ECEN-610 12
Binary-Weighted Current DAC
• Current switching is simple and fast.• Vo depends on Rout of current sources without op-amp.• INL and DNL depend on matching, not inherently monotonic.• Large component spread (2N-1:1)
VX
Vob3 b2 b1 b0 A
I/2 I/4 I/8 I/16
R∑=
⋅=N
1jjj-N
o 2b
IRV
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S. Hoyos-ECEN-610 13
R-2R DAC
• A binary-weighted current DAC• Component spread greatly reduced (2:1)
∑=
⋅=N
1jjj-N
o 2b
IRV
VX
Vob3 b2 b1 b0 A
R
R R R2R 2R 2R 2R
I
2RI/2 I/4 I/8 I/16
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S. Hoyos-ECEN-610 14
Unit-Element DAC
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S. Hoyos-ECEN-610 15
Resistor-String DAC
• Simple, inherently monotonic → good DNL performance
• Complexity ↑ speed ↓ for large N, typically N ≤ 8 bits
VR
Vo
Vo
Di
0
b0 b0 b1 b1
1
2
3
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S. Hoyos-ECEN-610 16
Code-Dependent Ro
• Ro of ladder varies with signal (code).• On-resistance of switches depend on tap
voltage.
t
Vo
VR
Vo
Ro
Dib0 b0 b1 b1
Co
Signal-dependentRoC causes HD.
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S. Hoyos-ECEN-610 17
INL and DNL
Vj =Rk
1
j−1
∑
Rk1
N
∑⋅ VR =
j −1( )R + ∆Rk1
j−1
∑
NR + ∆Rk1
N
∑⋅ VR
R+ΔRNR+ΔRN-1R+ΔR1 R+ΔR2
VR...V1 V2 VN VN+1
Vj-1 =j − 2( )R + ∆Rk
1
j−2
∑
NR + ∆Rk1
N
∑⋅ VR
Vj − Vj-1 =R + ∆Rj−1
NR + ∆Rk1
N
∑⋅ VR ≈
VR
N+
∆Rj−1
NR⋅ VR
DNLj = Vj − Vj-1 −VR
N
VR
N≈
∆Rj−1
R⇒ DNL = 0, σDNL =
σR
R.
∆R = 0,σR[ ]
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S. Hoyos-ECEN-610 18
INL and DNL
Vj =Rk
1
j−1
∑
Rk1
N
∑⋅ VR =
j −1( )R + ∆Rk1
j−1
∑
NR + ∆Rk1
N
∑⋅ VR ≈
j −1N
VR +
N - j +1( ) ∆Rk1
j−1
∑ − j −1( ) ∆Rkj
N
∑N2R
VR
INLj = Vj −j -1N
VR
VR
N⇒ INL = 0, σ INL max( ) ≈
N2
σR
R
.
⇒ Vj =j −1N
VR, σ Vj
2 ≈j −1( ) N - j +1( )
N3σR
2
R2 VR2.
⇒ σ Vj
2 max( ) ≈1
4NσR
2
R2 VR2, when j =
N2
+1≈N2
.
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S. Hoyos-ECEN-610 19
Current DAC
• Fast, inherently monotonic → good DNL performance• Complexity increases for large N, requires B2T decoder.
Io
…… …
…
Binary-to-Thermometer Decoder
...b1 bN
I I I
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S. Hoyos-ECEN-610 20
Unit Current Cell
• 2N current cells typically broken up into a (2N/2 X 2N/2) matrix
• Current source cascoded to improve accuracy• Coupled inverters improve synchronization of
current switches.
Io
ROW/COL Decoder
...
b1
bN
I
Φ
Φ
...
Sj Sj
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S. Hoyos-ECEN-610 21
Segmented DAC
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S. Hoyos-ECEN-610 22
BW vs. UE DAC’sBinary-weighted DAC• Pros
– Small– Simple– Min. switched elements
• Cons– Large DNL and glitches– Not guaranteed
monotonic• INL/DNL
– INL(max) ≈ (√N/2)σ– DNL(max) ≈ 2*INL
Unit-element DAC• Pros
– Good DNL, small glitches– Linear glitch energy– Guaranteed monotonic
• Cons– Needs B2T decoder– Large area for N ≥ 8
• INL/DNL– INL(max) ≈ (√N/2)σ– DNL(max) ≈ σ
Combine BW and UE architectures → “segmentation”
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S. Hoyos-ECEN-610 23
Segmented DAC
0
VFS
…
Di
Vo
2N-10
LSB’s
MSB’s
• MSB DAC: M-bit UE DAC
• LSB DAC: L-bit BW DAC
• Resolution: N = M + L• 2M+L s.e.• Good DNL• Small glitches• Same INL (depends on
matching)
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S. Hoyos-ECEN-610 24
ComparisonExample: N = 12, M = 8, L= 4, σ = 1%
Architecture σINL σDNL # of S.E.
Unit-Element 0.32 LSB’s
0.01 LSB’s 2N = 4096
Binary-weighted
0.32 LSB’s
0.64 LSB’s N = 12
Segmented 0.32 LSB’s
0.06 LSB’s
2M+L = 260
Max. DNL error occurs at the MSB segment transitions.
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S. Hoyos-ECEN-610 25
Example: “8+2” Segmented Current DAC
Ref: C.-H. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6mm2," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, issue 12, 1998.
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S. Hoyos-ECEN-610 26
MSB-DAC Biasing Scheme
Common-centroid global biasing + divided 4 quadrants of current cells
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S. Hoyos-ECEN-610 27
MSB-DAC Biasing Scheme
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S. Hoyos-ECEN-610 28
Randomization and Dummies
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S. Hoyos-ECEN-610 29
Measured INL and DNL
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S. Hoyos-ECEN-610 30
Summary• Nyquist DAC architectures
– Binary-weighted DAC– Unit-element (thermometer-coded) DAC– Segmented DAC– Resistor-string, current, charge-redistribution DAC’s
• Oversampling DAC– Oversampling performed in digital domain (zero stuffing)– Digital noise shaping (ΣΔ modulator)– 1-bit DAC can be used– Analog reconstruction/smoothing filter
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S. Hoyos-ECEN-610 31
References1. K. Khanoyan et al., VLSI, 1999, pp. 73-76.2. M. J. M. Pelgrom, JSSC, vol. 25, pp. 1347-1352, issue 6, 1990.3. A. van den Bosch et al., JSSC, vol. 36, pp. 315-324, issue 3, 2001.4. A. R. Bugeja et al., JSSC, vol. 35, pp. 1841-1852, issue 12, 2000.5. G. A. M. Van Der Plas et al., JSSC, vol. 34, pp. 1708-1718, issue 12, 1999.6. A. R. Bugeja et al., JSSC, vol. 34, pp. 1719-1732, issue 12, 1999.7. C.-H. Lin et al., JSSC, vol. 33, pp. 1948-1958, issue 12, 1998.8. K. Falakshahi et al., JSSC, vol. 34, pp. 607-615, issue 5, 1999.9. D. K. Su et al., JSSC, vol. 28, pp. 1224-1233, issue 12, 1993.