ecen620: network theory broadband circuit design fall 2020...the pll more efficiently 16 next time...
TRANSCRIPT
![Page 1: ECEN620: Network Theory Broadband Circuit Design Fall 2020...the PLL more efficiently 16 Next Time • Delay-Locked Loops (DLLs) • Clock-and-Data Recovery Systems 17 Title Microsoft](https://reader036.vdocument.in/reader036/viewer/2022081411/60ae6ae06ad26100f064160b/html5/thumbnails/1.jpg)
Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
ECEN620: Network TheoryBroadband Circuit Design
Fall 2020
Lecture 10: Fractional-N Frequency Synthesizers
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Announcements• HW3 due Oct 8
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Agenda• PLL Bandwidth and Frequency Resolution
Trade-Offs
• Fractional-N Frequency Synthesizers
• Modulus Randomization and Noise Shaping
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PLL Bandwidth Constraints
• PLL loop bandwidth should be <0.1*fref in order to maintain loop stability• Continuous-time model breaks down if loop
bandwidth is too high4
out(s)ref(s)
20log10
3dB = 1.47Mrad/s
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Issues with Synthesizing Frequencies at a Tight Channel Spacing
• In a simple integer-N PLL, the output frequency resolution is equal to the input reference frequency
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[Perrott]
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Issues with Synthesizing Frequencies at a Tight Channel Spacing
• In integer-N PLLs, synthesizing tight channel spacings requires extremely low effective reference frequencies
• This results in very low loop bandwidths and high divide ratios• Slow PLL frequency switching time• Large area passives• High phase noise at low frequencies
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[Perrott]
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Agenda• PLL Bandwidth and Frequency Resolution
Trade-Offs
• Fractional-N Frequency Synthesizers
• Modulus Randomization and Noise Shaping
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Fractional-N Frequency Synthesizers
• A fractional-N frequency synthesizer allows the effective division ratio to take on a fractional value
• The output frequency can then be at a much higher resolution than the reference frequency
• Allows a higher loop bandwidth8
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Effective Divide Ratio
9
25.44
17
55
412
512
1
cycles) VCO (5 once 5 and cycles) VCO (12 times three4by divide
4.25, of ratio divide effectivean realize To :Example
1Nby divided cycles VCO ofnumber theis B
and Nby divided cycles VCO ofnumber theisA where
1
:Ratio Divide Effective
NB
NA
BAN
NB
NA
BAN
eff
eff
3TREF
4
4/5
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Dual Modulus Prescalers
10
2/3
MC=0 3MC=1 2
15/16
Synchronous 3/4 Asynchronous 4• For /15, first prescaler circuit divides by 3 once and 4 three times
during the 15 cycles
[Razavi]
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Phase Error with Simple Periodic Modulus Control
• As only the average of the feedback frequency is equal to the reference frequency, the phase error will accumulate over N reference cycles before being reset
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[Perrott]
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Fractional-N Frequency Synthesizer Spurs
• Simple periodic modulus control causes a ramp-type phase error accumulation over N reference cycles
• This is translated into periodic disturbances in the VCO control voltage, which causes relatively close-in spurs in the frequency domain
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Agenda• PLL Bandwidth and Frequency Resolution
Trade-Offs
• Fractional-N Frequency Synthesizers
• Modulus Randomization and Noise Shaping
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Spur Suppression with Modulus Randomization
• Instead of periodically changing the divider modulus, randomly switch it such that the average division factor still yields the desired fractional value
• This converts the systematic fractional spurs into random noise
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Including Noise Shaping in Modulus Control
• This technique can be extended by in addition to randomization, shaping the noise in such a way that it can be filtered by the PLL
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Sigma-Delta Modulation Noise Shaping• High-pass noise shaping can
be realized by using a sigma-delta modulator for modulus control
• The divider quantization noise can then be filtered by the PLL more efficiently
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Next Time• Delay-Locked Loops (DLLs)
• Clock-and-Data Recovery Systems
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