edc unit 6

EDC-UNIT6 Question&answer

GRIET-ECE G.Surekha

UNIT-VI FIELD EFFECT TRANSISTOR

1. Explain about the Field Effect Transistor and also mention types of FET’s.

The Field Effect Transistor, or simply FET however, uses the voltage that is applied to

their input terminal, called the Gate to control the current flowing through them resulting in the

output current being proportional to the input voltage. As their operation relies on an electric

field (hence the name field effect) generated by the input Gate voltage, this then makes the Field

Effect Transistor a "VOLTAGE" operated device.

The Field Effect Transistor is a three terminal unipolar semiconductor device that has very

similar characteristics to those of their Bipolar Transistor counterparts ie, high efficiency, instant

operation, robust and cheap and can be used in most electronic circuit applications to replace

their equivalent bipolar junction transistors (BJT). Field effect transistors can be made much

smaller than an equivalent BJT transistor and along with their low power consumption and

power dissipation makes them ideal for use in integrated circuits such as the CMOS range of

digital logic chips. The field effect transistor is a three terminal device that is constructed with no

PN-junctions within the main current carrying path between the Drain and the Source terminals,

which correspond in function to the Collector and the Emitter respectively of the bipolar

transistor. The current path between these two terminals is called the "channel" which may be

made of either a P-type or an N-type semiconductor material. The control of current flowing in

this channel is achieved by varying the voltage applied to the Gate. As their name implies,

Bipolar Transistors are "Bipolar" devices because they operate with both types of charge carriers,

Holes and Electrons. The Field Effect Transistor on the other hand is a "Unipolar" device that

depends only on the conduction of electrons (N-channel) or holes (P-channel).

The Field Effect Transistor has one major advantage over its standard bipolar transistor, in

that their input impedance, ( Rin ) is very high, (thousands of Ohms), while the BJT is

comparatively low. This very high input impedance makes them very sensitive to input voltage

signals, but the price of this high sensitivity also means that they can be easily damaged by static

electricity. There are two main types of Field Effect Transistor, the Junction Field Effect

Transistor or JFET and the Insulated-gate Field Effect Transistor or IGFET), which is more

commonly known as the standard Metal Oxide Semiconductor Field Effect Transistor or

MOSFET for short.

2. Explain the working principle of JFET with characteristics.

The Junction Field Effect Transistor

A bipolar junction transistor is constructed using two PN-junctions in the main current carrying

path between the Emitter and the Collector terminals. The Junction Field Effect Transistor

(JFET) has no PN-junctions but instead has a narrow piece of high-resistivity semiconductor

material forming a "Channel" of either N-type or P-type silicon for the majority carriers to flow

through with two ohmic electrical connections at either end commonly called the Drain and the

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Source respectively. There are two basic configurations of junction field effect transistor, the N-

channel JFET and the P-channel JFET. The N-channel JFET's channel is doped with donor

impurities meaning that the flow of current through the channel is negative (hence the term N-

channel) in the form of electrons. Likewise, the P-channel JFET's channel is doped with acceptor

impurities meaning that the flow of current through the channel is positive (hence the term P-

channel) in the form of holes. N-channel JFET's have a greater channel conductivity (lower

resistance) than their equivalent P-channel types, since electrons have a higher mobility through

a conductor compared to holes. This makes the N-channel JFET's a more efficient conductor

compared to their P-channel counterparts. There are two ohmic electrical connections at either

end of the channel called the Drain and the Source. But within this channel there is a third

electrical connection which is called the Gate terminal and this can also be a P-type or N-type

material forming a PN-junction with the main channel. The relationship between the connections

of a junction field effect transistor and a bipolar junction transistor are compared below.

Comparison of connections between a JFET and a BJT

Bipolar Transistor Field Effect Transistor

Emitter - (E) >> Source - (S)

Base - (B) >> Gate - (G)

Collector - (C) >> Drain - (D)

The symbols and basic construction for both configurations of JFETs are shown below.

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The semiconductor "channel" of the Junction Field Effect Transistor is a resistive path through

which a voltage VDS causes a current ID to flow. The JFET can conduct current equally well in

either direction. A voltage gradient is thus formed down the length of the channel with this

voltage becoming less positive as we go from the Drain terminal to the Source terminal. The PN-

junction therefore has a high reverse bias at the Drain terminal and a lower reverse bias at the

Source terminal. This bias causes a "depletion layer" to be formed within the channel and whose

width increases with the bias. The magnitude of the current flowing through the channel between

the Drain and the Source terminals is controlled by a voltage applied to the Gate terminal, which

is a reverse-biased. In an N-channel JFET this Gate voltage is negative while for a P-channel

JFET the Gate voltage is positive. The main difference between the JFET and a BJT device is

that when the JFET junction is reverse-biased the Gate current is practically zero, whereas the

Base current of the BJT is always some value greater than zero.

Bias arrangement for an N-channel JFET and corresponding circuit symbols.

The cross sectional diagram above shows an N-type semiconductor channel with a P-type region

called the Gate diffused into the N-type channel forming a reverse biased PN-junction and it is

this junction which forms the depletion region around the Gate area when no external voltages

are applied. JFETs are therefore known as depletion mode devices. This depletion region

produces a potential gradient which is of varying thickness around the PN-junction and restrict

the current flow through the channel by reducing its effective width and thus increasing the

overall resistance of the channel itself. The most-depleted portion of the depletion region is in

between the Gate and the Drain, while the least-depleted area is between the Gate and the

Source. Then the JFET's channel conducts with zero bias voltage applied (i.e. the depletion

region has near zero width).

With no external Gate voltage ( VG = 0 ), and a small voltage ( VDS ) applied between the Drain

and the Source, maximum saturation current ( IDSS ) will flow through the channel from the

Drain to the Source restricted only by the small depletion region around the junctions.

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If a small negative voltage ( -VGS ) is now applied to the Gate the size of the depletion region

begins to increase reducing the overall effective area of the channel and thus reducing the current

flowing through it, a sort of "squeezing" effect takes place. So by applying a reverse bias voltage

increases the width of the depletion region which in turn reduces the conduction of the channel.

Since the PN-junction is reverse biased, little current will flow into the gate connection. As the

Gate voltage ( -VGS ) is made more negative, the width of the channel decreases until no more

current flows between the Drain and the Source and the FET is said to be "pinched-off" (similar

to the cut-off region for a BJT). The voltage at which the channel closes is called the "pinch-off

voltage", ( VP ).

JFET Channel Pinched-off

In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little or

no effect.

JFET Model

The result is that the FET acts more like a voltage controlled resistor which has zero resistance

when VGS = 0 and maximum "ON" resistance ( RDS ) when the Gate voltage is very negative.

Under normal operating conditions, the JFET gate is always negatively biased relative to the

source.

It is essential that the Gate voltage is never positive since if it is all the channel current will flow

to the Gate and not to the Source, the result is damage to the JFET. Then to close the channel:

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No Gate voltage ( VGS ) and VDS is increased from zero.

No VDS and Gate control is decreased negatively from zero.

VDS and VGS varying.

The P-channel Junction Field Effect Transistor operates the same as the N-channel above, with

the following exceptions: 1). Channel current is positive due to holes, 2). The polarity of the

biasing voltage needs to be reversed.

The output characteristics of an N-channel JFET with the gate short-circuited to the source is

given as

Output characteristic V-I curves of a typical junction FET.

The voltage VGS applied to the Gate controls the current flowing between the Drain and the

Source terminals. VGS refers to the voltage applied between the Gate and the Source while VDS

refers to the voltage applied between the Drain and the Source. Because a Junction Field Effect

Transistor is a voltage controlled device, "NO current flows into the gate!" then the Source

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current ( IS ) flowing out of the device equals the Drain current flowing into it and therefore (

ID = IS ).

The characteristics curves example shown above, shows the four different regions of operation

for a JFET and these are given as:

Ohmic Region - When VGS = 0 the depletion layer of the channel is very small and the

JFET acts like a voltage controlled resistor.

Cut-off Region - This is also known as the pinch-off region were the Gate voltage, VGS is

sufficient to cause the JFET to act as an open circuit as the channel resistance is at

maximum.

Saturation or Active Region - The JFET becomes a good conductor and is controlled by

the Gate-Source voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no

effect.

Breakdown Region - The voltage between the Drain and the Source, ( VDS ) is high

enough to causes the JFET's resistive channel to break down and pass uncontrolled

maximum current.

The characteristics curves for a P-channel junction field effect transistor are the same as those

above, except that the Drain current ID decreases with an increasing positive Gate-Source

voltage, VGS.

The Drain current is zero when VGS = VP. For normal operation, VGS is biased to be somewhere

between VP and 0. Then we can calculate the Drain current, ID for any given bias point in the

saturation or active region as follows:

Drain current in the active region.

Note that the value of the Drain current will be between zero (pinch-off) and IDSS (maximum

current). By knowing the Drain current ID and the Drain-Source voltage VDS the resistance of the

channel ( ID ) is given as:

Drain-Source channel resistance.

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Where: gm is the "transconductance gain" since the JFET is a voltage controlled device and

which represents the rate of change of the Drain current with respect to the change in Gate-

Source voltage.

3. Explain the working of Insulated Gate Field Effect transistor(IGFET) or MOSFET in

depletion mode.

Insulated gate field-effect transistors are unipolar devices just like JFETs: that is, the

controlled current does not have to cross a PN junction. There is a PN junction inside the

transistor, but its only purpose is to provide that non-conducting depletion region which is used

to restrict current through the channel.

Here is a diagram of an N-channel IGFET of the "depletion" type:

Notice how the source and drain leads connect to either end of the N channel, and how the gate

lead attaches to a metal plate separated from the channel by a thin insulating barrier. That barrier

is sometimes made from silicon dioxide (the primary chemical compound found in sand), which

is a very good insulator. Due to this Metal (gate) - Oxide (barrier) - Semiconductor (channel)

construction, the IGFET is sometimes referred to as a MOSFET. There are other types of IGFET

construction, though, and so "IGFET" is the better descriptor for this general class of transistors.

Notice also how there are four connections to the IGFET. In practice, the substrate lead is

directly connected to the source lead to make the two electrically common. Usually, this

connection is made internally to the IGFET, eliminating the separate substrate connection,

resulting in a three-terminal device with a slightly different schematic symbol:

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With source and substrate common to each other, the N and P layers of the IGFET end up being

directly connected to each other through the outside wire. This connection prevents any voltage

from being impressed across the PN junction. As a result, a depletion region exists between the

two materials, but it can never be expanded or collapsed. JFET operation is based on the

expansion of the PN junction's depletion region, but here in the IGFET that cannot happen, so

IGFET operation must be based on a different effect. Indeed it is, for when a controlling voltage

is applied between gate and source, the conductivity of the channel is changed as a result of the

depletion region moving closer to or further away from the gate. In other words, the channel's

effective width changes just as with the JFET, but this change in channel width is due to

depletion region displacement rather than depletion region expansion.

In an N-channel IGFET, a controlling voltage applied positive (+) to the gate and negative (-) to

the source has the effect of repelling the PN junction's depletion region, expanding the N-type

channel and increasing conductivity:

Reversing the controlling voltage's polarity has the opposite effect, attracting the depletion

region and narrowing the channel, consequently reducing channel conductivity:

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The insulated gate allows for controlling voltages of any polarity without danger of forward-

biasing a junction, as was the concern with JFETs. This type of IGFET, although its called a

"depletion-type," actually has the capability of having its channel either depleted (channel

narrowed) or enhanced (channel expanded). Input voltage polarity determines which way the

channel will be influenced.

If the IGFET is an N-channel and the input voltage is connected so that the positive (+) side is on

the gate while the negative (-) side is on the source, the channel will be enhanced as extra

electrons build up on the channel side of the dielectric barrier. Think, "negative (-) correlates

with N-type, thus enhancing the channel with the right type of charge carrier (electrons) and

making it more conductive." Conversely, if the input voltage is connected to an N-channel

IGFET the other way, so that negative (-) connects to the gate while positive (+) connects to the

source, free electrons will be "robbed" from the channel as the gate-channel capacitor charges,

thus depleting the channel of majority charge carriers and making it less conductive.

For P-channel IGFETs, the input voltage polarity and channel effects follow the same rule. That

is to say, it takes just the opposite polarity as an N-channel IGFET to either deplete or enhance:

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Illustrating the proper biasing polarities with standard IGFET symbols:

When there is zero voltage applied between gate and source, the IGFET will conduct current

between source and drain, but not as much current as it would if it were enhanced by the proper

gate voltage. This places the depletion-type, or simply D-type, IGFET in a category of its own in

the transistor world. Bipolar junction transistors are normally-off devices: with no base current,

they block any current from going through the collector. Junction field-effect transistors are

normally-on devices: with zero applied gate-to-source voltage, they allow maximum drain

current (actually, you can coax a JFET into greater drain currents by applying a very small

forward-bias voltage between gate and source, but this should never be done in practice for risk

of damaging its fragile PN junction). D-type IGFETs, however, are normally half-on devices:

with no gate-to-source voltage, their conduction level is somewhere between cutoff and full

saturation. Also, they will tolerate applied gate-source voltages of any polarity, the PN junction

being immune from damage due to the insulating barrier and especially the direct connection

between source and substrate preventing any voltage differential across the junction.

4. Explain the construction of Enhancement MOSFET or IGFET with neat diagrams and

also draw the symbols.

Enhancement Mode MOSFET or Insulated Gate FET (IGFET)

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The Metal Oxide Silicon FET (MOSFET) or Metal Oxide Silicon Transistor (M.O.S.T.) has an

even higher input resistance (typically 1012

to 1015

ohms) than that of the JFET. In this device the

gate is completely insulated from the rest of the transistor by a very thin layer of metal oxide

(Silicon dioxide SiO2). Hence the general name applied to any device of this type, the IGFET or

Insulated Gate FET.

Construction

The layers are laid down one by one, by diffusing various semiconductor materials with suitable

doping levels and layers of insulation into the surface of the device under carefully controlled

conditions at high temperatures. Parts of a layer may be removed by etching using photographic

masks to make the required pattern of the electrodes etc. before the next layer is added. The

insulating layers are made by laying down very thin layers of silicon dioxide; conductors are

created by evaporating a metal such as aluminum on to the surface. The transistors produced in

this way have a much higher quality than is possible using other methods, and many transistors

can be produced at one time on a single slice of silicon, before the silicon slice is cut up into

individual transistors or integrated circuits.

Fig. 4.1 Construction of a N Channel Enhancement Mode MOSFET

The basic construction of a MOSFET is shown in fig 4.1. A body or substrate of P type silicon is

used, into whose top surface are diffused two heavily doped N type regions in the form of a pair

of closely spaced strips. A very thin (about 10-4

mm) layer of silicon dioxide is then evaporated

onto the top surface forming an insulating layer. Parts of this layer are then etched away above

the N type regions using a photographic mask to leave these regions uncovered. On top of the

insulating layer, between the two N type regions a layer of aluminum is deposited. This acts as

the GATE electrode. Metal contacts are also deposited on the N type regions, which act as the

SOURCE and DRAIN connectors

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Fig 4.2 Enhancement Mode Operation

The gate has a voltage applied to it that makes it positive with respect to the source. This causes

holes in the P type layer close to the silicon dioxide layer beneath the gate to be repelled down

into the P type substrate and at the same time this positive potential on the gate attracts free

electrons from the surrounding substrate material. These free electrons form a thin layer of

charge carriers beneath the gate electrode (they can't reach the gate because of the insulating

silicon dioxide layer) bridging the gap between the heavily doped source and drain areas. This

layer is sometimes called an "inversion layer" because applying the gate voltage has caused the P

type material immediately under the gate to firstly become "intrinsic" (with hardly any charge

carriers) and then an N type layer within the P type substrate.

Any further increase in the gate voltage attracts more charge carriers into the inversion layer, so

reducing its resistance and increasing current flow between source and drain. Reducing the gate

source voltage reduces current flow. When the power is switched off of course, the area beneath

the gate reverts to P type once more. As well as the type described above, devices having N type

substrates and P type (inversion layer)channels are also available. Operation is identical, but of

course the polarity if the gate voltage is reversed.

The method of operation described is called "ENHANCEMENT MODE" as the application of

gate source voltage makes a conducting channel "grow", therefore it enhances the channel. Other

devices are available in which the application of a bias voltage reduces or "depletes" the

conducting channel.

Fig 4.3 Circuit Symbols for Enhancement Mode MOSFETs (IGFETs)

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5. Explain the construction of Depletion mode MOSFET or IGFET with neat diagrams and

also draw the symbols.

Depletion Mode MOSFET

Reducing The Conduction Channel

The depletion mode MOSFET shown as a N channel device (P channel is also available) in fig

5.1 is more usually made as a discrete component, i.e. a single transistor rather than IC form. In

this device a thin layer of N type silicon is deposited just below the gate-insulating layer, and

forms a conducting channel between source and drain. Thus when the gate source voltage VGS is

zero, current (in the form of free electrons) can flow between source and drain. Note that the gate

is totally insulated from the channel by the layer of silicon dioxide. Now that a conducting

channel is present the gate does not need to cover the full width between source and drain.

Because the gate is totally insulated from the rest of the transistor this device, like other IGFETs,

has a very high input resistance.

Fig 5.1 Depletion Mode N Channel MOSFET

In the N channel device, shown in Fig. 5.2 the gate is made negative with respect to the source,

which has the effect creating a depletion area free from charge carriers, beneath the gate. This

restricts the depth of the conducting channel, so increasing channel resistance and reducing

current flow through the device.

Fig 5.2 Operation of a Depletion Mode MOSFET

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Depletion mode MOSFETS are also available in which the gate extends the full width of the

channel (from source to drain). In this case it is also possible to operate the transistor in

enhancement mode. This is done by making the gate positive instead of negative. The positive

voltage on the gate attracts more free electrons into the conducing channel while at the same time

repelling holes down into the P type substrate. Thus the more positive the gate potential, the

deeper, and lower resistance is the channel. Increasing positive bias thus increases current flow.

This useful depletion/enhancement version has the disadvantage that, as the gate area is

increased; the gate capacitance is also larger than true depletion types. This may present

difficulties at higher frequencies.

Fig 5.6 Circuit Symbols for Depletion Mode MOSFETs (IGFETs)

Notice the solid bar indicating the presence of a conducting channel between source and drain.

Note: Making the gate more negative reduces conduction between source & drain In N channel

devices, but increases conduction between source & drain In P channel devices.

6. Draw the Volt Ampere characteristics of MOSFET (or) Output characteristics of

MOS FET

Volt Ampere characteristics of MOSFET (or) Output characteristics of MOS FET

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7. Mention the Applications of FETs.

Applications of FETs

Although FETs have a lower gain than bipolar transistors their very high input impedance makes

them suitable for applications where input signals may be severely reduced if applied to a bipolar

transistor base, which needs base current to operate. A useful feature of FETs is that they tend to

produce less background noise than Bipolar types and so are useful in the initial stages of

systems such as amplifiers; radios etc. where signal levels are very small and could be swamped

by excessive background noise.

8. Compare MOS FET and JFET

COMPARISON OF MOS FET WITH JFET

1) In JFET, the transverse electric field across the reverse biased P N junction controls

the conductivity of the channel. In FET Transverse electric field is induced across the

insulating layer.

2) Input impedance of MOS FET is much higher (1010

to 1015

) compared to that of

JFET (108

) because gate is insulated from channel.

3) The output characteristics of JFET are flatter than that of MOS FET because drain

resistance of JFET is much higher than MOS FET.

4) JFET is operated in depletion mode only where as MOSFET can be operated in

depletion and enhancement mode.

5) MOSFET are easier to fabricate than JFET

6) MOSFETs are easily get damaged due to static change

7) In MOSFET source and drain can be interchanged

8) CMOSFETs dissipates very low power

9) MOS FETs are widely used in VLSI.

.

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Problems

Q 1) When a reverse gate voltage is 12V, gate current is 1mA. Determine the resistance

between gate & source.

3

1212

1 10

VR k

I

Q 2) When reverse Gate voltage changes from 4.0 to 3.9V, the drain current changes from 1.3

to 1.6 mA. Find the Trans conductance.

Solution:

Given VGS = 4.0 – 3.9 = 0.1 V

ID = 1.6 – 1.3 = 0.3 mA

gm = ? 3

30.3 103 10

0.1

D

m

GS

Ig mho

V

Q 3) A FET has a drain current of 4mA. If IDSS = 8mA and VGS off = -6V. Find values of VGS

and VP.

Given IDS = 4 mA

IDSS = 8mA

VGS off = - 6V.

Solution: -

(i) VP = VGS off = -6V = 6V.

(ii)

2

1 GS

DS DSC

P

VI I

V

2

3 34 10 8 10 16

GSV

21 1

1 12 6 62

GS GSV Vor

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or

6

6

( )0.707 1 ;

( ) 1 0.707 0.293

6 0.293 1.758 .

GS

GS

V

V

GS

or

or

V Volts

SATURATION DRAIN CURRENT (IDSS)

2

1 GSDS DSS

P

VI I

V

2 DS DSS

m

P

I Ig

V

gmo is gm when VGS = 0

2

1DSS GS

mo m mo

P P

I Vg andg g

V V

4. The readings obtained from a JFET are as follows: -

Drain to source voltage (volts) = 5 12 12

Gate to source voltage (volts) = 0 0 -0.25

Drain current Id (mA) = 8 8.2 7.5

Determine (i) AC drain resistance (ii) Trans. Conductance (iii) Amplification Factor

SOLUTION:

(i) Ac Drain Resistance / constantDS

d GS

VR V

ID

= 3

12 5( ) 735

8.2 8( ) 0.2 10

Voltsk

mA

(ii) Trans conductance dm

Ig

VGSVDS constant

= 8.2 7.5 0.7 70

2.80 ( 0.25) 0.25 25

mAm m

(iii) Amplification factor = gm. Rd = 2.8 x 10-3

x 35x 103 = 98

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edc unit 6

Engineering

field effect transistors

standard bipolar transistor

electric field

equivalent bjt transistor

input gate voltage

bipolar transistors

input terminal

main current