ediwn111

EDI System Whats New 111

Product Version 111

April 2012

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Contents

About This ManualHow This Document Is OrganizedRelated Documents

EDI System Product Documentation

Release OverviewNew Text Commands and Global VariablesNew Command ParametersObsolete Text Commands and Global Variables

Supported in this ReleaseObsolete Command Parameters

Supported in this ReleaseRemoved from the Software

Default Behavior ChangesSupport to On-Chip Thermal Analysis Solution is WithdrawnNew and Revamped Documentation

New Chapter on Clock Concurrent Optimization CommandsNew Section on Post-Mask ECO Changes from a New Verilog Netlist (Using SpareCells Flow)

Foundation FlowsDefining ccoptDesign for Clock Tree ConstructionDefining ccopt Top and Bottom LayersScript changes for Hier Two-pass Flow

EDI System Display and ToolsNew Buttons in the Design BrowserOption for Reading Net Names File in the SelectDeleteDeselect RoutesFormOption for Saving Highlight SettingsOption To Specify Stream Map File in Verify Litho FormEnhanced Snapping Capability in the RulerOption for Customizing DPT ColorsSupport for Net Name DisplaySave Foundation Flow Files

Importing and Exporting the DesignTechnology Section Ignored for Subsequent LEF File

LEF-DEF PropertiesLEF 58 Properties for Creating New DRC Rules for 32-28 nm and Smaller

21212224

25

2526

272828

282929303030313131323232343434353536373839394040

41414242

NodesCut Layer EnhancementsRouting Layer EnhancementsMacro Enhancements

Flip ChipBump Placement Enhanced To Check Overlapping Based on RealGeometryfindPinPortNumber Enhanced To Report Port Number for IO CellsviewBumpConnection Enhanced To Automatically Redraw Flightlines afterBump Manipulation

Netlist VerilogNew Global Variable To Ignore Non-fatal Verilog Netlist ErrorssetDoAssign Exclusion File Enhanced To Support Bus Names withoutQualifiers

Netlist-to-NetlistrunN2NOpt Enhanced To Support Semiauto Mode

PartitioningDPT Colorizer SupporteditPin Command EnhancedEnhanced Pin QoR for Multi-Partition NetsIncremental assembleDesign Capability EnhancedinsertPtnFeedthrough Command EnhancedNew Clone Place Menu CommandNew Commands for Setting Pin Assignment ModeSupport for Wildcards in Net Name

FloorplanningcreatePlaceBlockage Command EnhancedEnhanced Support for High Effort planDesignflipOrRotateObject Command EnhancedFloorplan Toolbox EnhancedPlan Design GUI Form EnhancedSpecify Floorplan GUI Form EnhancedSupport for Adding Named Prefixes to BlockagesSupport for Aligning Objects of Mixed TypeSupport for Shifting SDP Groups

Multiple Supply Voltage (MSV)New Option for addPowerSwitch

NanoRoute RouterEnhanced NanoRoute Reporting

Metal Fill and Via FillNew trimMetalFill Parameter To Support Non-Default Spacing

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4242

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48505050505050515151515151515152525252

545455555657

Metal Fill Enhanced To Honor Non-default Rule HardspacingtrimMetalFillNearNet -createFillBlockage Now Supports Custom NamesNew trimMetalFillNearNet Parameter To Remove Metal Fill Near CriticalNetsaddMetalFill Now Supports Check Board ViasaddMetalFill Enhanced To Allow User-specified List of Critical Nets inTiming-aware ModesetMetalFill -diagOffset Now Supports 0 Value

Timing BudgetingAdded Global VariablesjustifyBudget Enhanced to Honor report_timing_format Global VariableNew Command to Reset Modified Budget

RC ExtractionpreRoute Extraction Enhanced to Support height_over Construct in the ICTor QRC Technology FileRC Extraction Mode GUI Enhanced for Specifying Standalone Signoff QRCSettingsSupport for Selecting SPEF par_value Triplet Field and Assigning toCorresponding RC Corner

TimingReporting Enhancements

report_propertyget_property Supports Power and Ground PinsAdded New Global to Report Constant Mismatch

Timing Library EnhancementsAdded New Command to Check Library Database VersionAdded New Global to Derive Capacitance RangeAbility to Read Library Without ECSM DataAdded New Global to Disable ECSM Sensitivity Data

SSTA EnhancementsAbility to Report Sensitivity Details of Process Parameters

Other EnhancementsAdded New Parameters to MMMC RC Corner CommandsAdded New Global to Use Clock Slew for Check ArcsAbility to ResetUpdate MMMC Data By DefaultAdded New write_sdf Parameters

Default Behavior Changes in Timingreport_timing -not_through Parameter Default Behavior Change

Timing DebugTiming Debug Paths Now Nested Trees

VerificationEnhanced Verify AC Limit FormEnhanced Verify Cut Density FormEnhanced Verify Metal Density Form

5859606061

61

6364646565

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Enhanced Verify Power Via FormEnhanced Verify Routing Constraints FormNew Verify Geometry Option To Report Out-of-die ObjectsSupport for Rectangular EdgesEnhanced Verify Geometry Support for LEF PropertiesverifyGeometry -noMinSpacing Enhanced To Ignore All Spacing RuleChecksverifyACLimit Enhanced To Perform Peak and Average Current Analysis

Yield AnalysisPower Calculation

Annotation Summary Reporting EnhancementsEnhanced Register Gating Efficiency ReportingNew Parameter to Control Output of Clock GatesPreviously Supported but not Documented Parameter Added toDocumentation

Rail Analysisauto_fetch_dc_sources Command EnhancedNew Parameter to Support User-Specified Technology FileResistance Extraction for TL Junctionsset_power_data -instance Command Parameter Enhanced to Honor -format ascii Parameterset_rail_analysis_mode -power_up_fast_mode Parameter DefaultBehavior ChangedSupport for Decoupling Capacitance Static Violation GIF PlotSupport for Embedded Bumps in Hierarchical TSV Designs

Early Rail AnalysisAuto Trace Function for Switched Nets SupportedNew Parameters to Control Virtual Followpin Generation

Mixed-Signal InteroperabilityGUI UpdatesNew Commands Added

Clock Concurrent OptimizationClock Tree Synthesis

New Parameter Added to Size Up Gating Components to MaximumsetCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesisor Optimization

OpenAccessNew Beta Control VariableNew Global to Specify a Constraint Group Name

TSV

767677777878

New Option Added to the Create TSVBump FormNew Options Added to the Assign TSVBump Form

Power PlanningNew Option for setAddStripeMode

ECO FlowsNew Flow Added to Make Late Logic Changes

1

About This ManualThis manual provides information about Product Version 11 the Cadencereg Encounterreg DigitalImplementation System family of products

The Encounter Digital Implementation System (EDI System) family encompasses the following products

Encounter Digital Implementation System LEncounter Digital Implementation System XLNanoRoutereg Ultra SoC Routing SolutionVirtuosoreg Digital ImplementationEncounter Timing System LEncounter Timing System XLEncounter Power System LEncounter Power System XLFirst Encountertrade LFirst Encounter XLFirst Encounter GXL

How This Document Is OrganizedThis Whats New manual is organized into chapters that cover broad areas of EDI System softwarefunctionality Each chapter contains topics that may address one or more of the following areas

New functionality in the EDI System software and enhancements made to existing forms andcommands to support a new featureChanges in default behavior name changes to existing commands and forms and syntax changesFeatures that were removed since version 10 of the softwareMajor documentation changes such as a new chapter or substantial reorganization

Related DocumentsFor more information about the EDI System family of products see the following documents You canaccess these and other Cadence documents with the Cadence Help documentation system

EDI System Product DocumentationEDI System Known Problems and SolutionsDescribes important Cadence Change Requests (CCRs) for the EDI System family of productsincluding solutions for working around known problems

EDI System User GuideDescribes how to install and configure the EDI System software and provides strategies forimplementing digital integrated circuits

EDI System Whats New 111 111

April 2012 8 Product Version 111

EDI System Text Command ReferenceDescribes the EDI System text commands including syntax and examples

EDI System Menu ReferenceProvides information specific to the forms and commands available from the EDI System graphicaluser interface

EDI System Database Access Command ReferenceLists all of the EDI System database access commands and provides a brief description of syntaxand usage

EDI System Foundation Flows User GuideDescribes how to use the scripts that represent the recommended implementation flows for digitaltiming closure with the EDI System software

EDI System Library Development GuideDescribes library development guidelines for the independent tools that make up the EDI Systemfamily of products

README fileContains installation compatibility and other prerequisite information including a list of CadenceChange Requests (CCRs) that were resolved in this release You can read this file online atdownloadscadencecom



2

Release OverviewNew Text Commands and Global VariablesNew Command ParametersObsolete Text Commands and Global VariablesObsolete Command ParametersDefault Behavior ChangesSupport to On-Chip Thermal Analysis Solution is WithdrawnNew and Revamped Documentation

New Text Commands and Global VariablesThe following table lists the commands that were added to the EDI System software The second columnidentifies the chapter of the EDI System Text Command Reference where the command is documented

New Commands and Globals Chapter

ccoptDesign Clock Concurrent Optimization Commands

check_ldb_version Timing Analysis Commands

fpgDefaultBlockageNamePrefix Floorplan Commands and GlobalVariables

generateCCOptRCFactor Clock Concurrent Optimization Commands

getCCOptMode Clock Concurrent Optimization Commands

getPinAssignMode Partition Commands and Global Variables

init_oa_default_rule Import and Export Commands and GlobalVariables

resetModifiedBudget Timing Budgeting Commands and GlobalVariables

setCCOptMode Clock Concurrent Optimization Commands

setPinAssignMode Partition Commands and Global Variables

spgM3StripePushDown Placement Commands and GlobalVariables

spgM3StripeShrink Placement Commands and Global



Variables

tbgConsolidateTrialNoTrialIPO Timing Budgeting Commands and GlobalVariables

tbgCorrelateMaxTranWithActualTran Timing Budgeting Commands and GlobalVariables

timing_enable_case_analysis_conflict_warning Timing Global Variables

timing_library_infer_cap_range_from_ccs_receiver_model Timing Global Variables

timing_path_based_use_min_max_clock_slew_for_check Timing Global Variables

timing_read_library_without_ecsm Timing Global Variables

timing_read_library_without_sensitivity Timing Global Variables

timing_ssta_report_endpoint_description Timing Global Variables

vl_tolerate_illegal_syntax Import and Export Commands and GlobalVariables

New Command ParametersThe following table lists the parameters that were added to the EDI System software The second columnidentifies the chapter of the EDI System Text Command Reference where the command is documented

New Parameters Chapter

addPowerSwitch

-netPrefix

Low Power Commands

auto_fetch_dc_sources

-region-region_pitch-layer

Rail Analysis Commands

ckSynthesis

-substituteValidCell

Clock Tree Synthesis Commands

create_delay_corner

-early_rc_corner-late_rc_corner

Timing Analysis Commands



createPlaceBlockage

-noCoreByCut-prefixOn

Floorplan Commands and Global Variables

createRouteBlk

-prefixOn


findPinPortNumber

-cellName

Flip Chip Commands and Global Variables

run_vsr

-share_shields

-no_taper_to_pinwidth

Mixed-Signal Commands

runN2NOpt

-floorplanOnly

Netlist-to-Netlist Command

setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning

setVerifyGeometryMode

-boundaryHalo

Verify Commands

setCTSMode

-synthUpsizeClockGate


set_default_switching_activity

-clock_gates_output_ratio

Power Calculation Commands

set_power_analysis_mode

-compatible_internal_power




setPlaceMode

-groupFlopToMacroLevel

-groupFlopToMacroList

Placement Commands and Global Variables

set_rail_analysis_mode

-extraction_tech_file


setIntegRouteConstraint

-shieldWidth

-shieldGap

-tandemWidth

-groupToOutsideSpacing


spefIn

-early_rc_corner-early_spef_field-late_rc_corner-late_spef_field-spef_field

RC Extraction Commands

streamOut

-attachNetProp

Import and Export Commands and Global Variables

trimMetalFill

-useNonDefaultSpacing

Metal and Via Fill Commands and Global Variables



trimMetalFillNearNet

-remove


update_delay_corner



verifyACLimit

-avgRecovery-deltaTemp-method-minPeakDutyRatio-minPeakFreq-useQrcTech-scaleCurrent

Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf

-exclude_whatif_arcs

-target_application


Obsolete Text Commands and Global VariablesSupported in this Release

The following obsolete text commands and global variables will continue to be supported in this release butwill be removed in the next major release of the software

reportYield This command is not being replaced

Obsolete Command Parameters



Supported in this Release

The following obsolete text command parameters will continue to be supported in this release but will beremoved in the next major release of the software

-lowest_layerThe -lowest_layer parameter of the auto_fetch_dc_sources command has been replaced by -layer

-clock_gates_outputThe -clock_gates_output parameter of the set_default_switching_activity command has beenreplaced by -clock_gates_output_ratio

Removed from the Software

The following obsolete text command parameters have been removed from the software

getPlanDesignMode and setPlanDesignMode

-abSpacingX-abSpacingY-exclusiveSpacing-maxDistToGuide-spacingX-spacingY

These parameters are not being replaced

Default Behavior ChangesThe following list briefly describes changes in default behavior that take effect in this release

Note Each description in this list is also the section in the Whats New where you can find more detailedinformation on the specific behavior change

Chapter Default Behavior Change

Verification verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule Checks

Clock Tree Synthesis setCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis orOptimization

Timing Analysis report_timing -not_through Parameter Default Behavior Change



Commands

Rail Analysis Resistance Extraction for TL Junctions

Support to On-Chip Thermal Analysis Solution is WithdrawnWith this release the support to on-chip thermal analysis solution is being withdrawn

New and Revamped DocumentationNew Chapter on Clock Concurrent Optimization CommandsThe EDI System Text Command Reference now contains a new chapter on Clock Concurrent Optimization(CCOpt) This chapter describes the CCOpt commands used to run this flow For more information see theClock Concurrent Optimization Commands chapter of the Text Command Reference

New Section on Post-Mask ECO Changes from a New Verilog Netlist(Using Spare Cells Flow)The ECO Flows appendix of EDI System User Guide now contains a new section on post-mask ECOchanges from a new Verilog netlist using spare cells flow For more information see Post-Mask ECOChanges from a New Verilog Netlist (Using Spare Cells Flow)



3


Defining ccoptDesign for Clock Tree ConstructionThe following vars are used for defining ccoptDesign for Clock Tree Construction

Variable Name Value Type Usage Description

cts_inverter_cells list Specify the CTS inverter cells

cts_buffer_cells list Specify the CTS buffer cells

clock_gate_cells list Specify the clock gate cells

cts_use_inverters boolean Specify true or false

update_io_latency boolean Specify true or false

cts_target_skew float Specify the skew

cts_target_slew float Specify the slew

cts_io_opt enum Specify on | off | secondary

cts_effort enum Specify low | medium | high

Defining ccopt Top and Bottom LayersThe following vars define top and bottom layers for clock tree and leaf nets non default rules and clockshielding net (ccopt only)


clk_tree_top_layer string Specify setCTSMode | setCCoptMode



clk_tree_bottom_layer string Specify setCTSMode | setCCoptMode

clk_leaf_top_layer string Specify setCTSMode | setCCoptMode

clk_leaf_bottom_layer string Specify setCTSMode | setCCoptMode

clk_tree_ndr string Specify setCTSMode | setCCoptMode

clk_leaf_ndr string Specify setCTSMode | setCCoptMode

clk_tree_shield_net string Specify setCTSMode | setCCoptMode

Script changes for Hier Two-pass FlowThe Hierarchical Two Pass flow can now be enabled using

set vars(hier_flow_type) 2pass

For execution It produces two makefiles

For partition-CTS

Makefilepass1

For rebudget-assembly

Makefilepass2

Note For simpler inter-partition timing flows you can use the hierarchical one-pass flow which utilizes asingle iteration of top-level budgeting



4

EDI System Display and ToolsNew Buttons in the Design BrowserOption for Reading Net Names File in the SelectDeleteDeselect Routes FormOption for Saving Highlight SettingsOption To Specify Stream Map File in Verify Litho FormEnhanced Snapping Capability in the RulerOption for Customizing DPT ColorsSupport for Net Name DisplaySave Foundation Flow Files

New Buttons in the Design BrowserThe following buttons have been added to the Design Browser to improve usability

Clear Use the Clear button to clear any existing text string in the text input fieldTop Page Use the new Top Page button in the Design Browser to return to the top of the designquickly In previous releases you had to click the Previous Page button several times or restart thebrowser to return to the top of the design

Option for Reading Net Names File in the SelectDeleteDeselect RoutesForm



This release makes it easier for you to specify net names in the SelectDeleteDeselect Routes form Earlieryou had to enter net names in the Nets input box on the form manually This was quite tedious if you wantedto specify several nets Now you can use the new Read Nets button on the form to read in an ASCII filewhich comprises a list of net names as the input

Option for Saving Highlight SettingsThe following buttons have been added to the Edit Highlight Color form to enable you to save and reloadcustom highlight settings

Save Saves highlight settings Use this button after you have customized the highlight sets in somewayLoad Loads highlight settings that have been previously saved in a fileDefault Reverts to the default settings for all highlight sets



Option To Specify Stream Map File in Verify Litho FormTo improve usability the GUI equivalent of an additional

verifyLitho

parameter has been added to the Routing Layers page on the Verify Litho formStream Map Specifies the name and path of the stream out map file which maps the GDS streamto the layers in the EDI System database This option is equivalent to using verifyLitho -mapFile filename

Note The GDS layer numbers in the stream out layer map should match the numbers in the LPA layer map

Enhanced Snapping Capability in the RulerIn this release the ruler in EDI System has been enhanced to snap to any type of edge not just horizontal orvertical edges This enhancement makes it easier for you to measure the diagonal distance betweenoctagonal bumps in flip chip designs as the ruler can now snap to 45-degree edges as well

Option for Customizing DPT ColorsIn this release Double Pattern Technology (DPT) display has been enhanced to show different boundary



patterns for different colors In addition you can now customize the DPT colors by using the Double Patternoption on the View-Only page of the Color Preferences form

Support for Net Name DisplayIn this release the tool has been enhanced to support the display of net names in the design area



Save Foundation Flow FilesThe Save Testcase form provides a new Check-box to save Foundation Flow Files The form can beaccessed from the EDI System graphical user interface File - Save - Testcase Check the box to savefoundation flow files



5


Technology Section Ignored for Subsequent LEF FileIn previous releases when a LEF file was read during the design import process the EDI system showed anerror if some of the layers were not defined in the first technology LEF file

In this release the system ignores definitions of new LEF LAYERs after the first technology file is read for thedesign Now by default the EDI system issues a warning and ignores the layers that are not defined in the firsttechnology LEF file



6

LEF-DEF PropertiesLEF 58 Properties for Creating New DRC Rules for 32-28 nm and Smaller Nodes

LEF 58 Properties for Creating New DRC Rules for 32-28 nm andSmaller NodesCut Layer Enhancements

You can define new CUT LAYER properties to create rules for cut layers that

Add FORBIDDENSPACING rule to indicate that if the spacing between two cuts belonging to a classname is greater than or equal to the specified minimum spacing and less than or equal to thespecified maximum spacing then there will be a violation

Add PARALLEL to cut layer ENCLOSURE rules to indicate that the enclosure values must be fulfilledbut not other ENCLOSURE statements if the wire containing a cut has a neighbor wire less the definedparallel within value and has a common parallel run length to the cut greater than or equal to thespecified parallel length on only one side

Add MINSUM in cut layer ENCLOSURETABLE rules to indicate that it is legal if two opposite sideshave overhang values greater than or equal to the sum of the specified overhangs and the smalleroverhang value is greater than or equal to the specified smaller overhangs

Add NONZEROENCLOSURE to CUTCLASS SPACINGTABLE rules to indicate that the inter-layer cutspacing between cuts in the current layer to cuts in the specified second layer only applies to cutedges with enclosure on the above metal layer of the cuts in the current layer greater than zero andhave parallel run length greater than 0 with the cuts in the second layer

Add EOLMINLENGTH to ENCLOSURETOJOINT rules to indicate that the joint must not be a EOL edgewith length greater than or equal to the specified minimum length along both sides and the length ofthe EOL edge is no longer necessarily equal to the wire width

Add the following keywords in cut layer SPACING rulesEXTENSION Specifies that the given extension should be extended on the cut edges that donot fulfill the overhang value defined in the ENCLOSUREEDGE OPPOSITE rule before thespecified cut spacing is applied between the extended edges to a metal in the second layer



NONEOLCONVEXCORNER Specifies the spacing of a cut to a convex corner that does nottouch a EOL edge with width less than the specified EOL width of a metal shape containing thecut in the form of a triangle formed by the smaller edge length or the specified cut spacingABOVEWIDTH Specifies that the cut to different-net metal spacing only applies on the abovemetal layer wire with width greater than or equal to the specified widthMASKOVERLAP Specifies the cut to metal containing the cut spacing on the overlap area oftwo different masks

Add the following in cut layer EOLENCLOSURE rulesABOVEBELOW Specifies that the EOL enclosure rule only applies on the above or belowrouting layer PARALLELEDGE Indicates that the EOL enclosure rule only applies if there is a parallel edgeon one side that is less than the specified parallel space lengthMINLENGTH Indicates that the EOL enclosure only applies if EOL edge has length greater thanor equal to the specified minimum length along both sides

Other cut layer enhancements includeEnhanced CUTCLASS SPACINGTABLE Rule

The number of possible inter-layer CUTCLASS SPACINGTABLE rules has been increasedfrom two to three Now you can specify up to three additional tables for intercut layer spacing- one with SAMENET one with SAMEMETAL and one with neither of them Earlier you couldspecify up to two cut class SPACINGTABLE rules

For more information see Defining Cut Layer Properties to Create 3228 nm and Smaller Nodes Rules in theLEF Syntax chapter of the LEFDEF Language Reference Guide

Routing Layer Enhancements

You can define new ROUTING LAYER properties to create rules for routing layers that

Add FORBIDDENSPACING ruleTo indicate that if the spacing between the rightleft or topbottom edge of a wire with width lessthan the specified maximum width to the rightleft or topbottom of another wire is greater thanor equal to the specified minimum spacing and less than or equal to the specified maximumspacing with parallel run length greater than the specified PRL value then it will be a violationif there is a different-metal polygon wire between the two wiresTo indicate that it will be a violation if two wires are at a certain distance apart that is greaterthan or equal to the specified minimum spacing and less than or equal to the maximumspacing and are within a specified distance from a wire having a width greater than or equalto the specified minimum width and has a parallel run length greater than the PRL value



Add WIDTH in routing layer FORBIDDENSPACING rule to indicate that it will be a violation if two wiresare at a certain distance apart that is greater than or equal to the specified minimum spacing andless than or equal to the maximum spacing and are within a specified distance from a wire having awidth greater than or equal to the specified minimum width and has a parallel run length greater thanthe PRL value

Add NONEOLCORNERONLY in PARALLELEDGE in routing layer SPACING ENDOFLINE rule to indicatethat the parallel edge neighbor wire must contain a corner that does not belong to another EOL edge

Add WIDTH in SPACING NOTCHLENGTH to routing layer SPACING rules to indicate that the minimumnotch length spacing only applies if the width of a single side of the notch is greater than or equal tothe specified notch width of the side

Add CONCAVECORNER in MINADJACENTLENGTH in routing layer MINSTEP rules to indicate that if aconcave corner is between two convex corners and if one of the length of the edges to form theconcave corner is less than the specified minimum adjacent length then the length of the other edgemust be greater than or equal to the specified minimum step length

Add the following keywords to routing layer SPACINGTABLE rulesSAMEMASK Specifies that the spacing(s) only apply to objects that belong to the same mask EXCEPTWITHIN in WIDTH Specifies that any wire that is at a distance greater than or equal tothe specified low exclude spacing and less than the high exclude spacing away from the widewire must be ignored

Add the following new keywords in WRONGDIRECTION to routing layer SPACING rulesPRL Indicates that the wrong direction spacing is only applied if longside edges of two wireshave common parallel run length greater than the specified PRL valueLENGTH Specifies that the wrong direction spacing is switched to apply to the shortend edgesif the length of both the wires is less than or equal to the specified length

Other routing layer enhancements includeEnhanced LENGTH in Routing Layer PROTRUSIONWIDTH Rule

If the given value of LENGTH in PROTRUSIONWIDTH is zero then the length of theprotrusion wire is irrelevant In this case the width of the protrusion wire should alwaysbe checked independent of the length of the wire

For more information see Defining Routing Layer Properties to Create 3228 nm and Smaller NodesRules in the LEF Syntax chapter of the LEFDEF Language Reference Guide



Macro Enhancements

You can define new MACRO properties to create rules for macros that

Add CELLROW in EDGETYPE rule to indicate which cell row the edge type is defined on for multipleheight cells

In addition the EDGETYPE rule has been enhanced to define multiple edge types on an edge includingsingle height cells such that different type of constraints can be defined on an edge

For more information see Macro in the LEF Syntax chapter of the LEFDEF Language Reference Guide



7

Flip ChipBump Placement Enhanced To Check Overlapping Based on Real GeometryfindPinPortNumber Enhanced To Report Port Number for IO CellsviewBumpConnection Enhanced To Automatically Redraw Flightlines after Bump Manipulation

Bump Placement Enhanced To Check Overlapping Based on RealGeometryIn previous releases overlapping of bumps was checked on the basis of their rectangular cell frames duringbump placement and manipulation This meant that for rectilinear bumps ciopCreateBump would not allowbumps to be placed together if their cell frames overlapped even if there was no overlap in their realgeometry In this release bump placement has been enhanced to check overlapping based on the realgeometry of the bumps instead of their rectangular cell frames As a result bump placement is now morearea efficient because bumps can be placed closer together



findPinPortNumber Enhanced To Report Port Number for IO CellsThis release makes the usage of findPinPortNumber more flexible as you can now find the pin port numberof the instance of the specified cell using the new -cellName parameter The -cellName parametercannot be used with the existing -instName parameter which is used to find the pin port number of thespecified instance

Additionally findPinPortNumber has been enhanced to return a list of suitable port numbers as a Tcl listThis means you can now use set result [findPinPortNumber] or catch findPinPortNumberresult to get the result

For example the command findPinPortNumber -instName IOPADS_INSTesd -pinName VDDmay return the following port number string as result

IOPADS_INSTesdVDD1 IOPADS_INSTesd1VDD1



viewBumpConnection Enhanced To Automatically Redraw Flightlinesafter Bump ManipulationIn flip chip designs flightlines are used extensively to interact with the design You can display flip chiprelated flightlines using viewBumpConnection This release makes flightline usage more user friendly byenhancing viewBumpConnection to automatically redraw flightlines after bump manipulation Specifically flightlines are now redrawn after the following actions

Bump assignments are swapped using swapSignal Flightlines of the selected bumps are swapped toreflect the manipulation

Bumps are unassigned using unassignBump Flightlines of specified bumps are removed

A bumpIO pad is moved Flightlines are redrawn to reflect the new location

An instance is deleted from the floorplan area using deleteSelectedFromFPlan Flightlines of thatinstance are also removed



8

Netlist VerilogNew Global Variable To Ignore Non-fatal Verilog Netlist ErrorssetDoAssign Exclusion File Enhanced To Support Bus Names without Qualifiers

New Global Variable To Ignore Non-fatal Verilog Netlist ErrorsDuring design import the software by default issues an error and quits when it detects netlist errors such asport mismatches However in a live design environment you may want to view the physical data in thelayout even though the design is not in a perfect state In such cases you will want to proceed despite thenetlist errors

A new feature of this release is that you can use the new vl_tolerate_illegal_syntax global variableto ignore non-fatal Verilog netlist errors during design import If you set this variable to 1 the softwaredisplays the following warning but continues with the design import

WARN (ENCSYC-1975) Encounter will try to proceed in the presence ofVerilog netlist errors because vl_tolerate_illegal_syntax is set to non-zero bythe user for prototyping Carefully examine and resolve all unexpectederrors Then proceed with caution

Note Although you can use vl_tolerate_illegal_syntax to enable the software to read a Verilognetlist with invalid syntax Cadence strongly advises you to resolve netlist errors before proceeding

setDoAssign Exclusion File Enhanced To Support Bus Names withoutQualifiersThis release makes it easier for you to specify assign nets and buses that are not to be replaced with a user-specified assign buffer The setDoAssign exclusion file has been enhanced to accept bus names without aqualifying range If the bus name is specified without a qualifier setDoAssign -excNetFile treats it thesame way as a bus name with a full range For example the following two entries are treated as equivalent

module N3TSBASTA adrs_map_adrs_900module N3TSBASTA adrs_map_adrs_900 [0899]



9

Netlist-to-Netlist

runN2NOpt Enhanced To Support Semiauto ModeIn this release the runN2NOpt command has been enhanced to support the semiauto mode to import orexport data from or to EDI System and allow you to execute a script in between In previous releases youcould run the command only either completely automatically (default auto mode) or completely customized(custom mode) The new semiauto mode now allows you to use a custom script while using the standardEDI System interface flow as in auto mode

Additionally you can use the new -floorplanOnly parameter to save and reload only the floorplan in thesemiauto mode



10


DPT Colorizer SupportThe colorizer support has been added in the 20nm partitioning and pin assignment domain to track DoublePattern Technology If the color of the first track is undefined then red color is assigned to the first track Thecolorizer support helps to identify if a design has double patterning or not by checking tracks signal andregular wires and vias

editPin Command EnhancedIn this release the editPin command has been enhanced to simplify the pin-attribute manipulation Changeshave been made to the following parameters to support this enhancement

ndashspreadTypeSpecifies how to spread pins along a blocks edges This parameter is now optional However theresults of pin updation will take into account values of other options (default or specified by user)For example if ndashfixOverlap is set as 1 and after updation the pin is not legal then it will traversethe partition periphery according to ndashspreadDirection and find the closest legal locationndashlayerSpecifies the layer on which the pins will be assigned This parameter is now optional but only when -spreadType is not specified

The updated syntax of the editPin command is as follows



Enhanced Pin QoR for Multi-Partition NetsEarlier for multi-partition nets pin assignment tried to align the pair of pins near the routing cross-point Inthis release pin assignment tries to minimize the distance from the source pin to the sink pins

Additionally the reportUnalignedNets command has been enhanced to measure the average misalignmentwith standard deviation for multi-partition nets

reportUnalignedNets -ptnToPtn multiFanout -topToPtn multiFanout -statisticsmultiFanoutrpt

This is helpful in measuring the QoR of multi-partition nets

Incremental assembleDesign Capability EnhancedIn the previous release the partition command had to be used in order to call the incremental design of ablock again With enhancements in this release you can call the incremental assembleDesign multiple times in a sessionwithout partitioning the block

insertPtnFeedthrough Command EnhancedIn the previous release the -noBuffer parameter of the insertPtnFeedthrough command could not be usedon a design that had master-clone partitions With enhancements in this release this limitation has beenaddressed and the insertPtnFeedthrough -noBuffer command now supports master-clonefeedthrough insertions



New Clone Place Menu CommandIn this release the Clone Place menu command has been added to the Partition menu You can now usethe Clone Place menu command to place all clone instances with location and orientation relative to themaster partition instances It adjusts the instance orientation based on the clone orientation

Alternatively you can use the clonePlace command

New Commands for Setting Pin Assignment ModeYou can now use the setPinAssignMode command to set the global parameters of the partition or block pinassignment feature Parameters specified with the setPinAssignMode command are used whenever yourun pin-related commands

You can use the new getPinAssignMode command to return the information about setPinAssignModeparameters in the log file and in the console

Support for Wildcards in Net NameIn this release the createNetGroup and addNetToNetGroup commands have been enhanced to supportwildcards while specifying the net names using the -net parameter This enhancement makes it easier foryou to select multiple nets with a common prefix or suffix





11


createPlaceBlockage Command EnhancedYou can now use the -noCutByCore parameter of the createPlaceBlockage command to specify that theplacement blockages should not be cut by row area in the core The -noCutByCore parameter allowscreation of placement blockages that overlap the core boundary and the IO ring area

Enhanced Support for High Effort planDesignIn this release high effort planDesign (setPlanDesignMode -effort high) has been enhanced to fullysupport VERSION 10 of the constraint file format including the following

For seed selection and auto fence creation it honors the user-specified utilization and the minmaxaspect ratio constraintsFor auto fence creation and macro placement it honors all the spacing constraints specified in theconstraint file

For details of the constraint file see Automatic Floorplan Synthesis Constraint File Format As a result of thenew constraints and options added for high effort flow the following spacing options for medium effortplanDesign have been removed from the setPlanDesignMode and getPlanDesignMode commands




flipOrRotateObject Command EnhancedThe flipOrRotateObject command has now been enhanced to flip or rotate objects that can be modulesgroups placement blockage routing blockage hard macros special routings and special vias (including45 degree) and special wires

Floorplan Toolbox EnhancedIn this release the Floorplan Toolbox had been enhanced to add the Set Placement Status button Youcan now use the Set Placement Status button on the Floorplan Toolbox to access the Set PlacementStatus form directly which you can use to change the placement status for either all or selected instances

Alternatively you can access the Set Placement Status form by choosing Floorplan ndash Edit Floorplan ndash SetInstance Placement Status



Plan Design GUI Form EnhancedIn this release the setPlanDesignMode page of the Plan Design form which is used to set the AutomaticFloorplan Synthesis global parameters has been enhanced to provide options that matchthe setPlanDesignMode command

The newly added GUI options are highlighted below



Specify Floorplan GUI Form EnhancedIn this release the Specify Floorplan ndash Advanced form which is used to specify the standard cell rows andbottom IO pad orientation has been enhanced to provide options that match the floorplan command




Support for Adding Named Prefixes to BlockagesSince some routing or placement blockages are valid only for certain steps while other blockages should bemaintained throughout enchancements have been made in this release to allow the user to name routing orplacement blockages with prefixes These prefixed blockages can then be easily identified and removed indifferent flow steps

To accomodate this enhancement -prefixOn parameter has been added tothe createPlaceBlockage and createRouteBlk commands Additionallythe fpgDefaultBlockageNamePrefix global variable has been added that you can use to set the prefix namefor routing and placement blockages



Support for Aligning Objects of Mixed TypePreviously the alignObject command did not align selected objects or mixed type For example if theselected objects contained an instance and a blockage they were not aligned However with enhancementsin this release selected objects of mixed type can be aligned

Support for Shifting SDP GroupsIn the previous release the shiftObject command was used to shift instances modules groups placementblockage routing blockage hard macros special routings and IO pins vertically or horizontally by aspecified distance In this release the shiftObject command has been enhanced to support the shiftingof Structured Data Path (SDP) groups as well This capability is also accessible through the FloorplanToolbox



12


New Option for addPowerSwitchWith this release a new option -netPrefix has been added to the command addPowerSwitch The optionadds a prefix to power switch enable nets



13


Enhanced NanoRoute ReportingWith enhancements in this release the number of nets that were not routed due to the existence of mixedsignal constraints is reported in the log file using the NanoRoute Router



14

Metal Fill and Via FillNew trimMetalFill Parameter To Support Non-Default SpacingMetal Fill Enhanced To Honor Non-default Rule HardspacingtrimMetalFillNearNet -createFillBlockage Now Supports Custom NamesNew trimMetalFillNearNet Parameter To Remove Metal Fill Near Critical NetsaddMetalFill Now Supports Check Board ViasaddMetalFill Enhanced To Allow User-specified List of Critical Nets in Timing-aware ModesetMetalFill -diagOffset Now Supports 0 Value

New trimMetalFill Parameter To Support Non-Default SpacingIn this release the trimMetalFill command has been enhanced to support non-default spacing Some criticalnets use a non-default rule (NDR) for routing as they may need to have wider wires or wider spacing thanother nets The new -useNonDefaultSpacing parameter enables you to use non-default spacing whiletrimming metal fill Use this parameter to extend NDR control to trimming metal fill

Metal Fill Enhanced To Honor Non-default Rule HardspacingNon-default rule (NDR) hardspacing is supported in LEFDEF From this release the following metal fillcommands honor NDR hardspacing

addMetalFilladdViaFilltrimMetalFill

This enables NanoRoute to support the NDR hardspacing rules

trimMetalFillNearNet -createFillBlockage Now Supports Custom NamesIn this release trimMetalFillNearNet -createFillBlockage has been enhanced to support custom namesIf you specify a name the tool uses that name as the fill blockage name If you do not specify a name thetool uses the default name netName_layerName_ for the fill blockage The advantage of using a customname is that it makes it easier for you to delete all the fill blockage when required using thedeleteRouteBlk command

New trimMetalFillNearNet Parameter To Remove Metal Fill Near CriticalNetsIn this release a new option has been added to trimMetalFillNearNet to remove the metal fill nearnets Use the new -remove parameter if you want to remove the metal fill around critical nets instead of justtrimming it

addMetalFill Now Supports Check Board ViasIn this release addMetalFill has been enhanced to support check board via generationaddMetalFill checks the snap grid and cut spacing to determine if the check board via is needed



Check board vias are used between metal fill

addMetalFill Enhanced To Allow User-specified List of Critical Nets inTiming-aware ModeIn this release addMetalFill has been enhanced to enable you to specify a list of critical nets whenadding metal fill in the timing-aware mode If you are using a third-party tool for sign-off static timing analysis(STA) your list of timing critical nets may be different from that generated by report_timing in EDIETS Insuch a case you can use the new -extraCriticalNet option in addMetalFill to specify additionalcritical nets

You can use the -extraCriticalNet option in one of the following ways

In the -timingAware sta mode There is likely to be some overlap between the list you specify andthe EDI list of critical nets The tool adds the extra nets you specify to the EDI list of critical netsdetermined via the -slackThreshold method If the list you specify is exactly the same as the EDIlist of critical nets the tool works in the same way as it would without the -extraCriticalNetoption

In the -timingAware on mode In this mode the tool considers the specified citical net list asmedium cost Use the -extraCriticalNet option in this mode if you want to avoid the run time hitthat is associated with performing timing analysis using the -timingAware sta option

Note If you use -extraCriticalNet option in the -timingAware off mode the tool waives the -extraCritcalNet option and issues a warning message

setMetalFill -diagOffset Now Supports 0 ValueIf you want to add metal fill shapes in a staggered pattern (addMetalFill -stagger diag) you must



first set -diagOffset offset_x offset_y in setMetalFill In previous releases both offset_x and offset_yvalues had to be larger than 0 In this release setMetalFill has been enhanced to support the value 0for offset_x and offset_y This makes it possible for you to add metal fill staggered in one direction Forexample you can choose to have just a horizontal offset as follows

setMetalFill -diagOffset 6 0



15


Added Global VariablesIn this release the following Timing Budgeting global variables have been added

tbgConsolidateTrialNoTrialIPO mdash Specifies that the method used to create the DRV constraints is thesame as that for performing timing budgeting both with or without trial In-Place-Optimization (IPO)tbgCorrelateMaxTranWithActualTran mdash Correlates the estimated max transition with the actualtransition

justifyBudget Enhanced to Honor report_timing_format Global VariableThe justifyBudget command now honors the report_timing_format global variable which allows you to customize the timing report according to the user-specified columns Previously the justify report createdduring budgeting did not honor report_timing_format therefore the timing report format displayedonly fixed columns by default Now the columns can be customized through the global variable Forexample the following command only lists the instance arc slew and arrival times in the report

set_global report_timing_format instance arc slew arrival

You must set this global before specifying justifyBudget or deriveTimingBudget -justify to getthe report in the desired format

New Command to Reset Modified BudgetYou can now use the new command resetModifiedBudget to reset the budget that was modified using themodifyBudget command resetModifiedBudget allows you to revert to the original generated budget ifthe modified budget is not yielding the correct timing for a block or rectify an incorrectly modified budgetThe syntax of the command is

resetModifiedBudget

-ptn partitionName | -inst instanceName

-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

RC ExtractionpreRoute Extraction Enhanced to Support height_over Construct in the ICT or QRC Technology FileRC Extraction Mode GUI Enhanced for Specifying Standalone Signoff QRC SettingsSupport for Selecting SPEF par_value Triplet Field and Assigning to Corresponding RC Corner

preRoute Extraction Enhanced to Support height_over Construct in theICT or QRC Technology FileEarlier the ICT construct height_over was not supported in preRoute extraction

In this release preRoute extraction is enhanced to support height_over construct defined in the 20NMinterconnect technology (ICT) file or QRC technology file

RC Extraction Mode GUI Enhanced for Specifying Standalone SignoffQRC SettingsEarlier the RC Extraction Mode form only supported the auto cmd mode wherein the QRC cmd file wasautomatically created from the EDI settings

In this release the form is enhanced to provide additional controls for running Standalone Signoff QRC The Signoff Run Settings include options to specify Run Mode including Auto Partial or Custom modeCommand Type Command File name and Layer Map File name This enhancement enables users to setQRCs CCL scripts in RC extraction form in the GUI



For details see Specify RC Extraction Mode section in the EDI Menu Reference document

Support for Selecting SPEF par_value Triplet Field and Assigning toCorresponding RC CornerIn this release spefIn command is enhanced to allow selection of SPEF par_value triplet field and itsassignment to the appropriate RC corner For this the following parameters are added to the command

-early_rc_corner Annotates the parasitics to the early RC corner for multi-corner analysis-early_spef_field Specifies the field of the triplet values in spef to be loaded corresponding to earlyRC corner-late_rc_corner Annotates the parasitics to the late RC corner for multi-corner analysis-late_spef_field Specifies the field of the triplet values in spef to be loaded corresponding to late RC



corner-spef_field Specifies the field of the triplet values in spef to be loaded

The -spef_field parameter is used only when an existing RC corner is specified or when no corner isspecified This parameter is mutually exclusive to the -late_rc_corner -early_rc_corner -late_spef_field and -early_spef_field parameters



17

TimingReporting EnhancementsTiming Library EnhancementsSSTA EnhancementsOther EnhancementsDefault Behavior Changes in Timing

Reporting Enhancementsreport_propertyget_property Supports Power and Ground PinsAdded New Global to Report Constant Mismatch

report_propertyget_property Supports Power and Ground PinsYou can now use the report_property and get_property commands to report and query on related powerand ground pins names for the corresponding library pins The following new properties have been added

related_ground_pin_namerelated_power_pin_name

For example

get_property [get_lib_pins CELLAA] related_power_pin

get_property [get_lib_pins CELLAA] related_ground_pin

Added New Global to Report Constant MismatchWhen the timing_enable_case_analysis_conflict_warning global variable is set to true during a full timingupdate the software issues a warning when propagated and asserted constant values are not same Areport named CTE_constant_mismatchrpt is generated that contains details of pins and the reasonfor constant mismatch This report file is over-written each time a full timing update takes placeBy default the timing_enable_case_analysis_conflict_warning global is set to false


Added New Command to Check Library Database VersionYou can use the following command to check the library database version

check_ldb_version

If the library version is not updated the details of missing features and recommendations for recompiling the



library database will be displayed

Added New Global to Derive Capacitance RangeThe following global variable has been added to infer the rise or fall of capacitance range values from CCSreceiver capacitance model

timing_library_infer_cap_range_from_ccs_receiver_model

By default the global is set to false

Ability to Read Library Without ECSM DataThe EDI system now allows you to change the mode of use (without ECSM timing model) if the timing librarycontains NLDM ECSM or CCS data in the same file You can use the following global variable to disableloading ECSM data

timing_read_library_without_ecsm


Added New Global to Disable ECSM Sensitivity DataYou can use the following global variable to disable loading of ECSM timing sensitivity data when librariesare read

timing_read_library_without_sensitivity

By default the global is set to 0

SSTA Enhancements

Ability to Report Sensitivity Details of Process ParametersYou can use the following global variable to report sensitivity details of each process parameter for slackarrival and required times at the endpoint of a timing path

timing_ssta_report_endpoint_description


Added New Parameters to MMMC RC Corner CommandsThe following new parameters have been added to the create_delay_corner andupdate_delay_corner commands

-early_rc_corner Specifies the RC corner object to associate with the early corner object-late_rc_corner Specifies the RC corner object to associate with the late corner object

Added New Global to Use Clock Slew for Check Arcs



The following new global variable has been added to compute delays for check arc based on slews

timing_path_based_use_min_max_clock_slew_for_check

When set to true slews for delay calculation of check arc are deduced from the following

Slew at the signal pin of check arc is considered as retimed slewFor the reference pin slews of both minmax (or setuphold) modes are considered

Based on the above slew conditions two delays for a check arc are calculated The worst value isconsidered as the check arc delay

By default this global variable is set to false

Ability to ResetUpdate MMMC Data By DefaultIn this release the EDI system resets the timing delay calculation and RC corner data for MMMC objects bydefault This is specific to MMMC objects that are created during system initialization

In previous releases this data had to be reset or updated using the respective update commands -update_analysis_view update_constraint_mode update_delay_cornerupdate_io_latency update_library_set and update_rc_corner

Added New write_sdf ParametersThe following new parameters have been added to the write_sdf command

-exclude_whatif_arcs Excludes what-if arcs in the SDF file-target_application Allows customization of the SDF output for use with STA or Verilogapplications


report_timing -not_through Parameter Default Behavior ChangeThe report_timing -not_through parameter default behavior has been changed as follows

Previous Behavior New Behavior Impact

Earlier the -not_throughparameter reported all thepaths not traversing throughthe specified nets ports orpins of a cell

Now by default the -not_through parameterwill be ignored when an object has already beenspecifiedThe following behavior changes have beenmade

If a collection of all the input ports have beenspecified (using all_inputs command) thenthe report will show paths to the inout part andpaths starting from the internal part of inout willbe excludedIf a collection of all output ports have beenspecified (using the all_outputs command)

This behavior changewas made so thatpaths goingfromtothrough inoutparts are alsoreported



then the report will show paths starting from theinternal part of inout and paths ending at inoutpart will be excludedIf any other collection (not specified usingall_inputs and all_outputs commands)is specified then paths to both the parts will notbe reported



18


Timing Debug Paths Now Nested TreesThe Timing Debug Paths are now nested trees for easier collapse and un-collapse The entries display thecategory information The columns in this field include name of the category worst negative slack (WNS)total negative slack (TNS) and number of failing paths



19

VerificationEnhanced Verify AC Limit FormEnhanced Verify Cut Density FormEnhanced Verify Metal Density FormEnhanced Verify Power Via FormEnhanced Verify Routing Constraints FormNew Verify Geometry Option To Report Out-of-die ObjectsSupport for Rectangular EdgesEnhanced Verify Geometry Support for LEF PropertiesverifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule ChecksverifyACLimit Enhanced To Perform Peak and Average Current Analysis

Enhanced Verify AC Limit FormIn this release the GUI equivalent of an additional verifyACLimit parameter has been added to the Verify ACLimit form to improve usability

Rule File Writes a file with suggested routing rules The fixACLimitViolation command uses this filefor widening wires and repairing AC current density violations TheRule File option is equivalent tousing verifyACLimit -ruleFile filename



Enhanced Verify Cut Density FormThe GUI equivalent of an additional verifyCutDensity parameter has been added to the Verify Cut Densityform to improve usability

Ignore blocked window Disables checking of windows that are fully covered by block or padobstructions This option is equivalent to using verifyCutDensity -ignoreCellBlock

In addition the Oversize check box has been renamed to Size Up Area By for consistency with the VerifyMetal Density form



Enhanced Verify Metal Density FormThe GUI equivalent of two additional verifyMetalDensity parameters have been added to the Verify MetalDensity form

Save to DB Saves density information to the EDI System database This option is equivalent tousing verifyMetalDensity -saveToDBSize Up Area By Specifies an offset value to the area that is to be verified The value is in user units(not in DBU) and can be positive or negative A positive value adds to the area that is verified Thisoption is equivalent to using verifyMetalDensity -oversize value



Enhanced Verify Power Via FormIn this release the GUI equivalent of an additional verifyPowerVia parameter has been added to the VerifyPower Via form to improve usability

Keep Previous Setting Specifies that all previous verifyPowerVia settings will be kept This option isequivalent to using verifyPowerVia-append



Enhanced Verify Routing Constraints FormIn this release the Detailed option has been added to the Verify Routing Constraints form If you select thisoption the Verify Routing Constraints report will contain all information related to routing constraints insteadof only violations



New Verify Geometry Option To Report Out-of-die ObjectsUse the new setVerifyGeometryMode -boundaryHalo value option to report objects that are out of the dieboundary At the chip level if any shape is outside the die-boundary it may cause a problem This option isdefined to check if any shape such as pin routing special routing or cell is outside the die boundary The -boundaryHalo value option specifies an offset value to the area to be verified The value can be positiveor negative A positive value adds to the area that is verified If (-area) + (-boundaryHalo) is within thedesign boundary the behavior is same as with -area If (-area) + (-boundaryHalo) is outside the designboundary the out-of-die objects are checked

Support for Rectangular EdgesIn this release as part of the NanoRoute2 implementation EDI System introduces virtual nodes and addspatches in the form of rectangular edges The rectangular edge defined by dbsWire is a virtual edge with atag marked as rect verifyGeometry and verifyConnectivity have been enhanced to support theserectangular edges In previous releases the wires were connected by the end points of the center line Rectedges are rectangular patches in which connectivity cannot be traced through the center line Without the rectedges there would have been gaps between the regular wires connected by the center line and pins As a



result verifyGeometry would flag many same-net violations

Enhanced Verify Geometry Support for LEF PropertiesVerify Geometry has been enhanced to support the following LEF properties

NONEOLCORNERONLY keyword in PARALLELEDGE in end-of-line (EOL) SPACING rule

The NONEOLCORNERONLY keyword specifies that the parallel edge neighboring wire must containa corner that does not belong to another EOL edge

ABOVE BELOW PARALLELEDGE and MINLENGTH keywords in the EOLENCLOSURE rule

ABOVE | BELOW Specify that the EOL enclosure rule only applies on the routing layer above orbelow

PARALLELEDGE parSpace EXTENSION backwardExt forwardExt Indicates that theEOLENCLOSURE rule only applies if there is a parallel edge on one side that is less than parSpacesubtracting the width of the EOL edge and by extending backwardExt going backward andforwardExt going forward in the direction orthogonal to the EOL edge

MINLENGTH minLength Indicates that if the EOL length is less than minLength along the sidethen any parallel edge on that side is ignored and the EOLENCLOSURE rule may not apply

verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing RuleChecks


verifyGeometry

-noMinSpacingignores minimumspacing rule checks

verifyGeometry -noMinSpacing ignores all spacingrules and not just minimum spacingrule

This also applies tothe setVerifyGeometryMode -minSpacing false setting

Improves Verify Geometry run time due tofewer checks

Usually there is no need for checkingadvanced spacing rules when minimumspacing rules are being ignored

verifyACLimit Enhanced To Perform Peak and Average CurrentAnalysisTraditionally verifyACLimit is used to check RMS current (Irms ) violations In this release

verifyACLimit has been enhanced to support peak current (Ipeak ) and average current (Iavg )

calculations The following parameters have been added to verifyACLimit to enable these calculations



-method Use this parameter to specify the type of checks to be performed -- rms peak or avg

Note Only the Advanced Analysis Engine (AAE) delay calculation engine supports I peak and I

avg calculation If you specify -method as peak or avg but AAE is not enabled the tool displays

the following error message

ERROR(ENCVAC-92) verifyACLimit checks for -method peak or avgrequires the AAE delay calculation engine You must uselsquosetDelayCalMode -engine aaersquo in EDI before running verifyACLimit forpeak or avg checks

-scaleCurrent Use this parameter to specify the scale factor for the current verifyACLimitmultiplies the final current value (I rms I peak I avg ) by the specified scale factor before

comparing it to the appropriate current limit to check for violations This allows derating

-minPeakDutyRatio Use this parameter to change the default minimum duty ratio value for I

peak calculation If a signal net has a duty ratio less than the minimum duty ratio the minimum duty

ratio will be used

-minPeakFreq Use this parameter to ignore the I peak current limit calculation for signal nets that

have an effective frequency below the specified value in Hertz

-avgRecovery Use this parameter to specify the recovery factor for calculating the I avg current

density with recovery By default the recovery factor (per layer) is read from the QRC techfile If youspecify -avgRecovery em_recover it overrides the QRC tech em_recover factor for all thelayers used in I avg limits

In addition to the above the following parameters were also added to verifyACLimit

-useQrcTech Use this parameter to force verifyACLimit to use the QRC tech file instead of theLEF technology file for Irms checks

Note If either I peak or Iavg is also checked all checks including Irms will use the QRC tech

file

-deltaTemp This parameter specifies the maximum temperature rise permitted in units of CelsiusThis value is normally used in the QRC tech file for the RMS current limit equation



20

Yield AnalysisThe reportYield command is now obsolete This command still works in this release but will be removedin the next major release of the software



21

Power CalculationAnnotation Summary Reporting EnhancementsEnhanced Register Gating Efficiency ReportingNew Parameter to Control Output of Clock GatesPreviously Supported but not Documented Parameter Added to Documentation

Annotation Summary Reporting EnhancementsThe annotation summary reported in the EPS log file and validation file (validation) has been enhanced tosupport object type based categorization The summary is based on the mapping file specified using themap_activity_file command

This enhancement is useful when performing RTL VCD-based power analysis since it categorizes the entriesused for annotation based on the following Primary Input (PI) Primary Output (PO) Flops (DFF) Latches(DLAT) and Blackbox (BBOX)

The following is a sample of the information appended to the log file

PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590

The validation file has the following categories

Eliminated Entries with same names in RTL amp GL netlistEliminated Entries which are missing in GL netlist which could be in RTLEntries which matched the RTL VCD Variables to Gate Level objectsEntries in which RTL VCD Variables were found directly in designEntries in which RTL names are not covered in VCD file

Each category is further categorized by object types The following is a sample validation file

Entries in which RTL names are not covered in VCD file

PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin

Enhanced Register Gating Efficiency ReportingIn this release the Register Gating Efficiency (RGE) reporting has been improved to display the ICG clusterinformation The report now contains information about registers at the fanout of each ICG instance alongwith their RGE metrics

A sample report is given below

ICG Root ClockToggles

Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance

block1_CG 10000e+08 10000e+08 50000e+07 0 1 block1SEQDFF

block2_CG 10000e+08 10000e+08 50000e+07 0 1 block2SEQDFF2

New Parameter to Control Output of Clock GatesYou can use the new parameter -clock_gates_output_ratio of the set_default_switching_activitycommand to control the transition density at the output pin(s) of the integrated and combinational clockgating cells This parameter is equivalent to specifying the parameters -icg_ratio and -comb_clockgate_ratio together and with the same value For example theset_default_switching_activity -clock_gates_output_ratio 06 is equivalent toset_default_switching_activity -icg_ratio 06 -comb_clockgate_ratio 06

The -clock_gates_output parameter of the command set_default_switching_activity is nowobsolete and has been replaced by -clock_gates_output_ratio The obsolete parameter still works inthis release but to avoid a warning message and to ensure compatibility with future releases update yourscript to use -clock_gates_output_ratio

Previously Supported but not Documented Parameter Added toDocumentationThe -compatible_internal_power parameter of the set_power_analysis_mode command waspreviously supported but not documented This parameter has been set to true by default in the 111release The parameter specifies whether to use the new or old algorithm for internal power calculation Whenset to true the software uses the new algorithm The new algorithm fixes problems in arc handling of somestandard cells and is proven to be more accurate leading to better correlation with other third party toolsThis would change the internal power numbers in 111 as compared to previous releases At the designlevel internal power can vary between 0-10





22

Rail Analysisauto_fetch_dc_sources Command EnhancedNew Parameter to Support User-Specified Technology FileResistance Extraction for TL Junctionsset_power_data -instance Command Parameter Enhanced to Honor -format ascii Parameterset_rail_analysis_mode -power_up_fast_mode Parameter Default Behavior ChangedSupport for Decoupling Capacitance Static Violation GIF PlotSupport for Embedded Bumps in Hierarchical TSV Designs

auto_fetch_dc_sources Command EnhancedIn this release the auto_fetch_dc_sources command was improved to fetch the voltage sources within thespecified region of a specific layer controlled by the region pitch (xPitchyPitch) If the voltage sources withthe specified region pitch are not on the stripe you can use the -snap parameter to snap the voltagesources to the stripe As a result the voltage sources are generated only on the stripes and the region pitch ishonored This feature was added to enable the software to generate mesh type voltage sources on anyprocess layer

Earlier when the Edit Pad Location GUI form was used to auto fetch voltage sources within a region usingthe xPitchyPitch option the software always used the lower-left point of the defined region as the startpoint without checking if this point is on the net or not Now the start point will be snapped to the specifiednet automatically and then the region pitch will be used to fetch

The following parameters were added to the auto_fetch_dc_sources command to support this feature

-region x1 y1 x2 y2 mdashgenerates the voltage sources in the specified region-region_pitch xpitch ypitch mdashspecifies the region pitch in the x and y direction for thevoltage sources-layer layername mdashspecifies the process layer in LEF on which the voltage sources are to begenerated

The -lowest_layer parameter of the command auto_fetch_dc_sources is now obsolete and hasbeen replaced by -layer The obsolete parameter still works in this release but to avoid a warningmessage and to ensure compatibility with future releases update your script to use -layer

New Parameter to Support User-Specified Technology FileYou can now use the -extraction_tech_file parameter of the set_rail_analysis_mode command tospecify the extraction technology file to be used for top-level power-grid extraction If you do not specify thisparameter the software will use the extraction technology file stored inside the power-grid view library



Resistance Extraction for TL JunctionsA minor change has been made to the resistance extraction algorithm for TL junctions of metal geometriesto produce more accurate results This would change resistance values of such topology in the design andcould result in some changes in IRdrop

set_power_data -instance Command Parameter Enhanced to Honor -format ascii ParameterThe set_power_data -instance command parameter now honors the -format ascii option Thisenhancement allows you to specify the power consumption data for individual hierarchical instances in asimple ASCII two-column or three-column instance power file The first column specifies the instance namethe second column specifies the power consumption in watts and the third column specifies the power pin ofthe instance for MSMV designs

Previously the set_power_data -instance parameter was supported only when the power format wasset to -format current

set_rail_analysis_mode -power_up_fast_mode Parameter DefaultBehavior ChangedIn this release the default value of the -power_up_fast_mode parameter of the set_rail_analysis_modecommand has been changed to true In the current implementation the software enables fast-modesimulation for native power-up analysis by default

Previously the default value of this parameter was false This default value has been changed because ofperformance penalty that was being caused when considering IRdrop feedback between always-on andpowering-up domains Even though IRdrop feedback is turned off during power-up analysis the softwaredoes not use ideal voltage on power-gate always-on pins and uses realistic voltage considering the IRdropeffects of the always-on domain

Support for Decoupling Capacitance Static Violation GIF PlotDecap optimization in EDI System (set_rail_analysis_mode -decap_opt_method) does not calculatedecap requirement in the regions of high static or average IRdrop because IRdrop in such regions cannotbe fixed with decaps In this release rail analysis will generate a new gif plot calleddecap_static_violationsgif inside the state directory to highlight these regions when the averageIRdrop exceeds the specified IRdrop threshold

To calculate the average IRdrop the average current for the instances are derived from dynamic currentsThe GIF plot will not be generated if the average IRdrop does not exceed the IRdrop threshold at any nodeon the power-grid

Support for Embedded Bumps in Hierarchical TSV Designs



The auto_fetch_dc_sources command has been enhanced to support IR drop analysis for a hierarchicalTSV design When you specify the auto_fetch_dc_sources command to fetch the voltage sources fromthe LEF file the command not only searches for the PG pin of the pad connected to the specified PG netbut also fetches for the embedded bump property definition for the PG pin The port that contains the pointdefined in the embedded bump property is considered as the center point of the embedded bump

The following LEF file syntax shows how to define an embedded bump

PROPERTYDEFINITIONS

PIN EMBEDDEDBUMP STRING

END PROPERTYDEFINITIONS

MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER

PROPERTY EMBEDDEDBUMP ldquoM7 100 50rdquo

PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS

The following command saves the voltage source name of the embedded bump the pad location x and ycoordinates and the layer data to a file named bumppp

save_pad_location ndashformat xy ndashtsv ndashfile bumppp

The syntax of the pad location file is

ltblock_instance_namegtEmbeddedBumpltNogt x y ltlayer_namegt



23


Auto Trace Function for Switched Nets SupportedIn this release ERA has been enhanced to read the power-grid view library and trace switched-on nets ofpower gate cells automatically using the information stored in power gates power-grid view Previously ERAcould only trace switched-on nets using the power gate file specified with the analyze_early_rail -power_gate_file command If the power gate file was not specified ERA could not trace switched-onnets of the power gate cells and you had to specify the switched-on net explicitly using the -net parameter

New Parameters to Control Virtual Followpin GenerationIn this release the analyze_early_rail command was enhanced to specify the extension target for followpingeneration This feature allows you to reduce the turnaround time for generating followpin wire by srouteThe following parameters were added to the analyze_early_rail command

-extend_followpins_to_trunkmdashextends the followpins to the next stripe You can use thisparameter if followpins extend its previous stripe but cannot reach the next stripe-stop_followpins_at_rowendmdashextends all followpins till the row end By default followpins stopat the last instance they reach



24


GUI UpdatesThe Integration Constraints Editor form now includes the following new buttons Set OutsideSpacing SetShieldWidth Set ShieldGap and Set TandemWidth

New Commands AddedIn this release the following new parameters have been added to the mixed-signal commands

run_vsr

The run_vsr command is used for launching the Virtuoso Space-based Router (VSR) from EDI System Itaccepts the library name cell name and view name and opens the cellview for speciality routing It routesthe selected nets in the following order bus diffPair symmetry match nets and shield Then it saves thisinformation within the given cell view The following new parameters have been added to this command

-no_taper_to_pinwidth-share_shields




The setIntegRouteConstraintcommand applies specialty routing constraints in the database for netsin the designs It allows creation of differential pair match pair shield nets and nets with non-defaultrules The following new parameters have been added to this command

-shieldWidth-shieldGap-tandemWidth-groupToOutsideSpacing



25

Clock Concurrent OptimizationThis release is enhanced to provide a new technology called Clock Concurrent Optimization (CCOpt) whichis a single-step process that optimizes both the clock tree and the datapath to meet global timingconstraints

As clock trees become more complex in todayrsquos high-performance designs with considerations required foraggressive chip frequency clock gating and power domains a skew-driven clock tree synthesis (CTS)solution is not the best approach

EDI Systemrsquos CCOpt technology combines CTS with power performance and area optimizationCompared to the traditional skew-driven CTS this technology provides a 10 improvement in designperformance and total power a 30 reduction in clock power and area and a 30 reduction in dynamicIR drop

The following commands support this feature

ccoptDesign Performs CCOpt on the current loaded design in the EDI system Thiscommand optimizes both the clock tree and the datapath to meet global timing constraintsgenerateCCOptRCFactor Automatically computes resistance and capacitance multipliers foreach operating condition and creates a script that sets these multipliersgetCCOptMode Displays information about the setCCOptMode command parameters in the EDISystem log file and in the EDI System consolesetCCOptMode Sets global parameters for ccoptDesign

For more information about the commands see the Clock Concurrent Optimization Commands chapterin the EDI System Text Command Reference

For more information about the CCOpt flow see the Clock Concurrent Optimization section in theSynthesizing Clock Trees chapter in the EDI System User Guide



26

Clock Tree SynthesisNew Parameter Added to Size Up Gating Components to MaximumsetCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis or Optimization

New Parameter Added to Size Up Gating Components to MaximumUse the new setCTSMode -synthUpsizeClockGate parameter to size up gating componentsto maximum These can be sized down later by the software in order to reduce power and area withoutdegrading the skew The default value of this parameter is false

setCTSmode -routeClkNet Enhanced to Route Clock Nets afterSynthesis or Optimization

Previous Behavior NewBehavior

Impact

The default value of setCTSmode ndashrouteClkNet option isfalse So when you run clockDesign to synthesize a clocktree the command internally sets the setCTSmode -routeClkNet option to true routes clock nets after synthesisand then resets this option back to false This behavior is notdesired as it ignores user option setting

In this releasethe defaultvalue ofsetCTSmodendashrouteClkNetoption is set totrue

With this changesetCTSMode ndashrouteClkNetdefault value andclockDesigndefault behavior arenow consistent



27

OpenAccess

New Beta Control VariableThe following commands will now work using a new beta control variable

copy_designcopy_design_hiercompare_cellviewsave_abstractsaveDesign -hierset_cell_binding

Contact your Cadence representative for more information

New Global to Specify a Constraint Group NameYou can use the new init_oa_default_rule global to specify a constraint group name at the start of EDISystem session The name provided would be used by EDI System for reading the place-and-routetechnology rules from the constraint group



28

TSVNew Option Added to the Create TSVBump FormNew Options Added to the Assign TSVBump Form

New Option Added to the Create TSVBump FormThe following new option has been added to the Create TSVBump form

Perimeter Matrix Creates TSVBump along the rings on perimeter based on users definition

New Options Added to the Assign TSVBump FormThe following new options have been added to the Assign TSVBump form

Assign Region Assign TSVBump within the region only

Exclude Region Do not assign TSVBumps within the specified region

Assign Net Assign the specified nets to TSVBumps

Exclude Net Do not assign the specified nets to TSVBumps



29

Power Planning

New Option for setAddStripeMode

New Option for setAddStripeModeThe following two options have been added for the command setAddStripeMode

-stripe_min_width Specifies the minimum width of the remaining stripe after being trimmed

-trim_stripeSpecifies if shape is trimmed by the specified shape



30


New Flow Added to Make Late Logic ChangesA new flow has been added that allows you to make late logic changes after the masks are made This flowuses pre-existing spare cells so no polydiffusion changes are allowed and only the routing is modifiedYou can direct the software to make routing changes only on specific layers For more details refer Post-Mask ECO Changes from a New Verilog Netlist (Using Spare Cells Flow)



Contents

About This Manual

How This Document Is Organized

Related Documents


Release Overview

New Text Commands and Global Variables

New Command Parameters

Obsolete Text Commands and Global Variables





Default Behavior Changes

Support to On-Chip Thermal Analysis Solution is Withdrawn

New and Revamped Documentation

New Chapter on Clock Concurrent Optimization Commands

New Section on Post-Mask ECO Changes from a New Verilog Netlist (Using Spare Cells Flow)

Foundation Flows

Defining ccoptDesign for Clock Tree Construction

Defining ccopt Top and Bottom Layers

Script changes for Hier Two-pass Flow

EDI System Display and Tools

New Buttons in the Design Browser

Option for Reading Net Names File in the SelectDeleteDeselect Routes Form

Option for Saving Highlight Settings

Option To Specify Stream Map File in Verify Litho Form

Enhanced Snapping Capability in the Ruler

Option for Customizing DPT Colors

Support for Net Name Display

Save Foundation Flow Files

Importing and Exporting the Design

Technology Section Ignored for Subsequent LEF File

LEF-DEF Properties

LEF 58 Properties for Creating New DRC Rules for 32-28 nm and Smaller Nodes

Cut Layer Enhancements


Macro Enhancements

Flip Chip

Bump Placement Enhanced To Check Overlapping Based on Real Geometry

findPinPortNumber Enhanced To Report Port Number for IO Cells

viewBumpConnection Enhanced To Automatically Redraw Flightlines after Bump Manipulation

Netlist Verilog

New Global Variable To Ignore Non-fatal Verilog Netlist Errors

setDoAssign Exclusion File Enhanced To Support Bus Names without Qualifiers

Netlist-to-Netlist

runN2NOpt Enhanced To Support Semiauto Mode

Partitioning

DPT Colorizer Support

editPin Command Enhanced

Enhanced Pin QoR for Multi-Partition Nets

Incremental assembleDesign Capability Enhanced

insertPtnFeedthrough Command Enhanced

New Clone Place Menu Command

New Commands for Setting Pin Assignment Mode

Support for Wildcards in Net Name

Floorplanning

createPlaceBlockage Command Enhanced

Enhanced Support for High Effort planDesign

flipOrRotateObject Command Enhanced

Floorplan Toolbox Enhanced

Plan Design GUI Form Enhanced

Specify Floorplan GUI Form Enhanced

Support for Adding Named Prefixes to Blockages

Support for Aligning Objects of Mixed Type

Support for Shifting SDP Groups

Multiple Supply Voltage (MSV)

New Option for addPowerSwitch

NanoRoute Router

Enhanced NanoRoute Reporting

Metal Fill and Via Fill

New trimMetalFill Parameter To Support Non-Default Spacing

Metal Fill Enhanced To Honor Non-default Rule Hardspacing

trimMetalFillNearNet -createFillBlockage Now Supports Custom Names

New trimMetalFillNearNet Parameter To Remove Metal Fill Near Critical Nets

addMetalFill Now Supports Check Board Vias

addMetalFill Enhanced To Allow User-specified List of Critical Nets in Timing-aware Mode

setMetalFill -diagOffset Now Supports 0 Value

Timing Budgeting

Added Global Variables

justifyBudget Enhanced to Honor report_timing_format Global Variable

New Command to Reset Modified Budget

RC Extraction

preRoute Extraction Enhanced to Support height_over Construct in the ICT or QRC Technology File

RC Extraction Mode GUI Enhanced for Specifying Standalone Signoff QRC Settings

Support for Selecting SPEF par_value Triplet Field and Assigning to Corresponding RC Corner

Timing

Reporting Enhancements

report_propertyget_property Supports Power and Ground Pins

Added New Global to Report Constant Mismatch

Timing Library Enhancements

Added New Command to Check Library Database Version

Added New Global to Derive Capacitance Range

Ability to Read Library Without ECSM Data

Added New Global to Disable ECSM Sensitivity Data

SSTA Enhancements

Ability to Report Sensitivity Details of Process Parameters

Other Enhancements

Added New Parameters to MMMC RC Corner Commands


Ability to ResetUpdate MMMC Data By Default

Added New write_sdf Parameters

Default Behavior Changes in Timing

report_timing -not_through Parameter Default Behavior Change

Timing Debug

Timing Debug Paths Now Nested Trees

Verification

Enhanced Verify AC Limit Form

Enhanced Verify Cut Density Form

Enhanced Verify Metal Density Form

Enhanced Verify Power Via Form

Enhanced Verify Routing Constraints Form

New Verify Geometry Option To Report Out-of-die Objects

Support for Rectangular Edges

Enhanced Verify Geometry Support for LEF Properties

verifyGeometry -noMinSpacing Enhanced To Ignore All Spacing Rule Checks

verifyACLimit Enhanced To Perform Peak and Average Current Analysis

Yield Analysis

Power Calculation

Annotation Summary Reporting Enhancements

Enhanced Register Gating Efficiency Reporting

New Parameter to Control Output of Clock Gates

Previously Supported but not Documented Parameter Added to Documentation

Rail Analysis

auto_fetch_dc_sources Command Enhanced

New Parameter to Support User-Specified Technology File

Resistance Extraction for TL Junctions

set_power_data -instance Command Parameter Enhanced to Honor -format ascii Parameter

set_rail_analysis_mode -power_up_fast_mode Parameter Default Behavior Changed

Support for Decoupling Capacitance Static Violation GIF Plot


Early Rail Analysis

Auto Trace Function for Switched Nets Supported

New Parameters to Control Virtual Followpin Generation

Mixed-Signal Interoperability

GUI Updates

New Commands Added

Clock Concurrent Optimization

Clock Tree Synthesis

New Parameter Added to Size Up Gating Components to Maximum

setCTSmode -routeClkNet Enhanced to Route Clock Nets after Synthesis or Optimization

OpenAccess

New Beta Control Variable

New Global to Specify a Constraint Group Name

TSV

New Option Added to the Create TSVBump Form

New Options Added to the Assign TSVBump Form

Power Planning


ECO Flows

New Flow Added to Make Late Logic Changes

copy 2011-2012 Cadence Design Systems Inc All rights reservedPrinted in the United States of America

Cadence Design Systems Inc (Cadence) 2655 Seely Ave San Jose CA 95134 USA

Trademarks Trademarks and service marks of Cadence Design Systems Inc(Cadence) contained in this document are attributed to Cadence with the appropriatesymbol For queries regarding Cadencersquos trademarks contact the corporate legaldepartment at the address shown above or call 1-800-862-4522

All other trademarks are the property of their respective holders

Restricted Print Permission This publication is protected by copyright and anyunauthorized use of this publication may violate copyright trademark and other lawsExcept as specified in this permission statement this publication may not be copiedreproduced modified published uploaded posted transmitted or distributed in any waywithout prior written permission from Cadence This statement grants you permission toprint one (1) hard copy of this publication subject to the following conditions

1 The publication may be used solely for personal informational and noncommercialpurposes

2 The publication may not be modified in any way3 Any copy of the publication or portion thereof must include all original copyright

trademark and other proprietary notices and this permission statement and4 Cadence reserves the right to revoke this authorization at any time and any such

use shall be discontinued immediately upon written notice from Cadence

Disclaimer Information in this publication is subject to change without notice and doesnot represent a commitment on the part of Cadence The information contained herein isthe proprietary and confidential information of Cadence or its licensors and is suppliedsubject to and may be used only by Cadencersquos customer in accordance with a writtenagreement between Cadence and its customer Except as may be explicitly set forth insuch agreement Cadence does not make and expressly disclaims any representationsor warranties as to the completeness accuracy or usefulness of the informationcontained in this document Cadence does not warrant that use of such information willnot infringe any third party rights nor does Cadence assume any liability for damages orcosts of any kind that may result from use of such information

Restricted Rights Use duplication or disclosure by the Government is subject torestrictions as set forth in FAR52227-14 and DFAR252227-7013 et seq or itssuccessor

4444

667

101010111111121212

12

13131314

1515

15161717171819202021

Contents












21212224

25

2526

272828

282929303030313131323232343434353536373839394040

41414242










4242

4242

43434545454547

47

47

48505050505050515151515151515152525252

545455555657












5859606061

61

6364646565

6567676768

68

686868707070717171737474

7475757576

61










TSV

767677777878




1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


4444

667

101010111111121212

12

13131314

1515

15161717171819202021

Contents












21212224

25

2526

272828

282929303030313131323232343434353536373839394040

41414242










4242

4242

43434545454547

47

47

48505050505050515151515151515152525252

545455555657












5859606061

61

6364646565

6567676768

68

686868707070717171737474

7475757576

61










TSV

767677777878




1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


21212224

25

2526

272828

282929303030313131323232343434353536373839394040

41414242










4242

4242

43434545454547

47

47

48505050505050515151515151515152525252

545455555657












5859606061

61

6364646565

6567676768

68

686868707070717171737474

7475757576

61










TSV

767677777878




1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


4242

4242

43434545454547

47

47

48505050505050515151515151515152525252

545455555657












5859606061

61

6364646565

6567676768

68

686868707070717171737474

7475757576

61










TSV

767677777878




1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


5859606061

61

6364646565

6567676768

68

686868707070717171737474

7475757576

61










TSV

767677777878




1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


767677777878




1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


1



















2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows










2


















Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


Variables












addPowerSwitch

-netPrefix

Low Power Commands




ckSynthesis



create_delay_corner





createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


createPlaceBlockage



createRouteBlk

-prefixOn


findPinPortNumber

-cellName


run_vsr

-share_shields



runN2NOpt

-floorplanOnly


setAddStripeMode

-stripe_min_width

-trim_stripe

Power Planning


-boundaryHalo

Verify Commands

setCTSMode











setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


setPlaceMode








-shieldWidth

-shieldGap

-tandemWidth



spefIn



streamOut

-attachNetProp


trimMetalFill






-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows



-remove


update_delay_corner



verifyACLimit


Verify Commands

verifyPowerVia

-stackedVia

Verify Commands

writeDieAbstract

-noFilter

TSV Commands

write_sdf


-target_application

























Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows



















Commands







3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


3



























For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows











For partition-CTS

Makefilepass1


Makefilepass2




4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


4













verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows








verifyLitho














5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows









5






6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


6

































Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows























Macro Enhancements







7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


7


















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows















8










9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


9

Netlist-to-Netlist





10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


10

























11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows



















11






























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows























12





13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


13





14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


14
























15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows















15








resetModifiedBudget


-pin pinName

[-setup | -hold]



[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


[-view viewName]

[-help]



16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


16

















17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows











17





For example






check_ldb_version














SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows












SSTA Enhancements































18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows
























18





19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


19




































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows
































verifyGeometry




















ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows











ratio will be used








file




20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


20




21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


21





PI 2547

PO 1020

DFF 299350

DLAT 345500

BBOX 4590





PI entries

PO entries

DFF entries



DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


DLAT entries

BBOX entries

G inv R vin




Toggles atClock Pin

Toggles at Qpin

RGE DAGE Instance










22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows




22






















PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows














PROPERTYDEFINITIONS



MACRO SUBSYS

CLASS BLOCK

PIN VDD

USE POWER


PORT

LAYER M7

POLYGONE xxx

END

END VDD

END SUBSYS







23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


23







24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


24




run_vsr










25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows







25










26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


26





Impact






27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


27

OpenAccess







28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


28











29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


29

Power Planning







30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


30





Contents

About This Manual


Related Documents


Release Overview













Foundation Flows















LEF-DEF Properties




Macro Enhancements

Flip Chip




Netlist Verilog



Netlist-to-Netlist


Partitioning









Floorplanning












NanoRoute Router










Timing Budgeting




RC Extraction




Timing









SSTA Enhancements


Other Enhancements







Timing Debug


Verification











Yield Analysis

Power Calculation





Rail Analysis








Early Rail Analysis




GUI Updates

New Commands Added





OpenAccess



TSV



Power Planning


ECO Flows


ediwn111

Documents

adding named

signal interoperabilitygui

make late

resetupdate

qrc tech file

spare cells

early rc corner

auto fence