edn design ideas 2000

www.ednmag.com January 6, 2000 | edn 119

ideasdesign

Acommon technique for imple-menting PWM involves comparinga triangular waveform of fixed am-plitude and frequency with a variable dcvoltage level. Although this approach re-sults in a PWM signal of precise fre-quency and with duty cycle variable from0 to 100%, the need for a reference tri-angle waveform and a suitable fast com-parator can be prohibitively expensive inlow-cost applications. Furthermore, if anapplication requires a high-frequencyPWM signal, the power consumptionmay be unacceptable in power-sensitiveapplications, such as high-efficiency, low-power switch-mode regulators.

The circuit in Figure 1 is a relativelysimple alternative to the triangle/com-parator approach. Although the frequen-cy of the output waveform is not stableand varies with input voltage, the circuitis inexpensive, requires only a handful ofreadily available parts, and exhibits a lin-ear relationship between inputvoltage and output duty cycle.The circuit lends itself to applicationsthat enclose a simple PWM section with-in a feedback loop. Also, the excellent dy-namicsthe duty cycle responds to aninput step change within one cycle of theoutput waveformmake the circuit ide-

ally suited to switch-mode-regulator ap-plications.

In the circuit, the dc input voltage, VI,

varies the duty cycle of the rectangularsignal at the output of Schmitt inverter,IC

1A. Q

1and Q

2function as switched-cur-

rent sources. These sources charge anddischarge timing capacitor C

1at a rate

that their base voltages and, hence, thevoltage at the junction of R

2and R

3de-

termine. When the output of IC1A

is high,C

1charges through R

6and Q

1(Q

2is cut

off) with a charge current set by R6

andthe emitter voltage of Q

1. Similarly, when

the output of IC1A

is low, C1

dischargesvia Q

2and R

6(Q

1is cut off) with a dis-

charge current set by R6

and the emitterpotential of Q

2. Adjusting the input volt-

age changes the emitter potentials andthus varies the charge and discharge cur-rents so that the duty cycle of the output

waveform varies in direct linear propor-tion to V

I.

Figure 2 shows the relationship be-tween V

C, which is the voltage on C

1, and

the output waveform.VTU

and VTL

are theupper and lower thresholds of theSchmitt inverter, V

His the Schmitt trig-

gers hysteresis, and VOH

and VOL

are thehigh and low output levels, respectively,of the inverter.

If you assume that VOH

5VCC

andV

OL50V and taking the base-emitter

voltages of Q1

and Q2

to be roughly equaland denoted by V

BE, you can derive the

following first-order expressions for T1

and T2, where K

15R

2/(R

21R

3), and

K25R

4/(R

31R

4):

and

+

2

R333k R5

10M

R65.6k

C1

Q2BC847C

Q1BC857C

IC1A74HC14R2

33k

R122k

R422k

INPUTVOLTAGE

VI

OUTPUT

VCC (5V NOMINAL)

100 pF

F igure 1

Low-power PWM circuit is simple, inexpensiveAnthony Smith, Scitech, Biddenham, England

In this PWM circuit, adjusting the input voltage, VI, changes the emitter potentials of Q1 and Q2 andthus varies the charge and discharge currents of C1 so that the duty cycle of the output varies indirect linear proportion to VI.

Low-power PWM circuit is simple, inexpensive..................................119

Manchester co-decoder fits into 32-macrocell PLD..........................122

Input-protection scheme tops other approaches ..............................124

Level-shifting nixes need for dual power supply ................................126

Synchronize asynchronous reset..............128

Circuit resolves 0.1-fF change from 100 pf ....................................................130

Edited by Bill Travis and Anne Watson Swager

,V)1K(V)K1(V

VRCT

BE1I1CC

H611

111 +

=

120 edn | January 6, 2000 www.ednmag.com

ideasdesign

Defining the output duty cycle as equalto 100%2T

1(T

1+T

2), you can combine

the expression for T1

and T2

to yield

If the R1-to-R

4divider network is sym-

metrical, or R15R

4and R

25R

3, this ex-

pression simplifies to

Taking the values for R1to R

4in Figure

1, the equation reduces to

This expression shows that the dutycycle is directly proportional to the inputvoltage and that V

Imust be greater than

VBE

/0.4 for the circuit to work. IfV

BE50.6V, this equation suggests that V

I

must be at least 1.5V, although, in bread-board tests, the circuit produced low dutycycles with V

Ias low as 1V.

You select C1

and R6

according to therequired operating-frequency range. Fig-ure 3 illustrates the results of breadboardtests with R

655.6 kV and C

15100 pF.

The circuit exhibits linear performance

with VIat approximately 1.2 to 3.6V with

a corresponding duty-cycle range of ap-proximately 2 to 95%. This figure alsoshows that the output frequency varies byas much as 15 to 1 over this range; theoutput frequency peaks when V

Iis ap-

proximately equal to VCC

/2.You need to observe a few caveats when

selecting R1to R

4and IC

1A. To ensure that

the duty cycle is variable from near zeroto near 100%, the charge and dischargecurrents through Q

1and Q

2must be able

to approach zero. You can meet this re-quirement simply by ensuring that V

E1, or

Q1s emitter potential, can approach V

CC

and that VE2

, or Q2s emitter potential, can

approach ground.You can make V

E1approach V

CCwhen

VIis a maximum by the suitable selection

of R1and R

2, provided that you choose R

3

and R4

so that VE2

can goa few hundred millivoltsbelow the minimum low-er threshold voltage, V

TL

(minimum), of IC1A

when VI

is a maximum.This feature isnecessary to en-

sure that Q2

does not sat-urate when V

Capproach-

es VTL

(minimum) as C1

discharges.Similarly, by suitably

selecting R3

and R4, you

can make VE2

approachzero when V

Iis a mini-

mum, provided that you choose R1

andR

2so that V

E1can go a few hundred mil-

livolts above the maximum upper thresh-old voltage, V

TU(maximum), of IC

1A

when VI

is a minimum. This feature isnecessary to ensure that Q

1does not sat-

urate when VC

approaches VTU

(maxi-mum) as C

1charges.

The values R15R

4522 kV and R

25

R3533kV meet these requirements and

provide an optimum range for VI. These

values should provide reliable operationfor V

CC55V65% and IC

1Aand IC

1A5

74HC14, but you may need to recalculatethe values if you use a different supplyvoltage or a different inverter.

Two possible devices to use for IC1A

arethe 74HC14 and the 4093. The 74HC14is preferable because the minimum tomaximum variation in its hysteresis volt-age is only about 3.3 to 1, whereas thevariation in V

Hfor the 4093 is approxi-

mately 6.7 to 1. However, the 4093 allowsoperation at supply voltages greater than5V, but take care to avoid base-emitterbreakdown of Q

1and Q

2at higher supply

voltages.Power consumption is low. For exam-

ple, with C15100 pF, the maximum cur-

rent draw is 570 mA at the point of max-imum frequency, which is approximately200 kHz. The maximum practical oper-ating frequency is limited to around 500kHz (C

1510 pF, R

655.6kV), where the

relationship between VIand the duty cy-

cle starts to become noticeably nonlinear.(DI #2461)

To Vote For This Design,Circle No. 458

VTU

VH

T1 T2

VC

VTL

VOL

VOH

IC1AOUTPUT

F igure 2

The changing voltage, VC, across C1 and the hysteresis, VH, of IC1Adetermine the duty cycle, T1/(T11T2), of the output waveform. VTUand VTL are IC1As upper and lower thresholds, respectively.

Although the frequency of the output waveform varies with the input voltage, the PWM circuitexhibits a linear relationship between input voltage and output duty cycle.

.VVK

VRCT

BEI2

H612

1

=

%.100V2)1KK(V)K1(V

VVK

DUTYCYCLE

BE21I1CC

BEI2 ++

=

111

1

%.100V2)K1(V

VVKDUTYCYCLE

BE1CC

BEI2

=

11

1

%.100V2 V0.4

VV 4.0DUTYCYCLE

BECC

BEI =1

1

F igure 3


ideasdesign

Manchester encoding is com-mon, and this scheme erasesthe dc-spectrum componentpresent in an NRZ signal in basebandtransmissions. An important applicationis in Ethernet-interface adapters, inwhich several kinds of media-attachmentunits interface with OSI layers. Manycommercial transceivers work on allphysical layers of the IEEE 802.3 stan-dard. Figure 1 and the correspondingsource code realize a customized versionof the 10BaseT standard in which thephysical layer is a coupled stripline in abackplane. Figure 1 shows the simpleschematic of the LAN controller.

With an 80-MHz external clock, the32-macrocell PLD implements a com-plete Manchester co-decoder at a 10-MHz bit-speed rate. You can downloadthe VHDL source code from EDNs Website, www.ednmag.com. Click on SearchDatabases and then enter the SoftwareCenter to download the file for DesignIdea #2462.

The Manchester coder comprises anXOR gate between the transmitted datafrom the mC data_in) and the internal10-MHz clock. Both the data_in and cod-ed output lan_out signals are synchro-

nous with the 10- and 80-MHz clocks, re-spectively. Asserting a high at the 10 in-put enables the coder.

The decoders operation is more com-plicated than that of the encoder. A be-havioral simulation (Figure 2) shows theinternal signals that are involved in thedecoding process. Note that the spike onthe cd signal is not a true spike; it ap-pears only in the behavioral simulationand disappears in postlayout simulation.The signal in_trans is a short triggerpulse that occurs at every positive andnegative lan_intransaction. These puls-

es trigger a filter maker that gen-erates an impulse signal called fil-ter, and each pulse of this filtersignal lasts 75% of the bit inter-val. The end of each filter pulsemarks the start of a pulse of a 10-MHz recovered clock. The designgenerates decoded data by sam-pling the data stream with the ris-ing edge of the recovered clock.After a bit violation, or whendata_in remains a one or a zerofor more than 100 nsec, the sys-tem deasserts the carrier-detectsignal,cd.Many mC families re-quire that five or six recovered

clock pulses are present after the systemdeasserts the carrier-detect signal. Toconserve space in the PLD, this designroughly multiplexes the recovered clockand the 10-MHz system clock. (The68360 mP tolerates one pulse with no as-pect of duty cycle.) The carrier-detect sig-nal is the multiplexer controller. The 80-MHz clock has no stability requirements,and the system tolerates jitter on 10-MHzManchester-coded signals. (DI #2462)

mC

X485DATA IN

DATA OUT

CK_DATA_OUT

TEN

CLK_10

LAN_OUT

LAN_IN

CODER

DECODER

CLK_80MR

2032VE

F igure 1

Manchester co-decoder fits into 32-macrocell PLDAntonio Di Rocco, Siemens ICN Spa, LAquila, Italy

A 32-macrocell PLD implements a complete Manchesterco-decoder at a 10-MHz bit-speed rate.

F igure 2

A behavioral simulation of the decoders operation shows the internal signals involved in decoding.


124 edn | January 6, 2000

ideasdesign

You typically accomplish over-voltage or surge protection at circuitinputs by connecting diodes to thesupply rails, connecting zener diodes toground, or connecting transzorbs toground. Unfortunately, for high-energysurges at the inputs, connecting diodes tothe supply rails results in surges in sup-ply lines and affects other componentsbecause of the inductance of supply rails,regulator shutdown, and so on. Zenerdiodes have limited surge capability, andtranszorbs have large capacitance and aretherefore suited only for low-bandwidthapplications.

The circuit in Figure 1 has many ad-vantages over these approaches: widebandwidth and low capacitance; highsurge-energy handling because the di-odes can carry 50A peak; 1A continuouscurrent; and fast response. Also, the cir-cuit doesnt affect the supply rails and issuitable for protecting multiple I/O linesbecause the lines can share the bias volt-age. You can further improve the re-sponse time by using faster diodes; aground plane; low-inductance, shortconnections; and close, high-frequencydecoupling.

The circuit reverse-biases D1

and D4

tobias voltages of 61.2V, respectively. R

1

and R2

bias two pairs of diodes, D2/D

3

and D5/D

6, respectively, to generate the

61.2V. R1

and R2

prevent input surgesfrom reaching the supply rails. The surge

shunt path consists of D1, D

2, and D

3to

ground or D4, D

5, and D

6to ground, de-

pending on the surges polarity. Becauseof the 612V bias-voltage settings, the cir-cuit works with maximum input signalsof 61V. Above thislevel, D

1and

D4start to leak

and distort the signal.The circuit was testedusing a 100-mF/50Vtest capacitor chargedto 30V and then dis-charged to the input.ADSO captured the re-sults (Figure 2). InFigure 2a, with R

S5

100V, the peak is ap-proximately 3.5V, andsettling to around 2Voccurs within 15 nsec.Figure 2b shows thesame response as Fig-ure 2a but with a hor-izontal scale of 1msec/div. Figure 2c isalso the response un-der the same condi-tions but shows thelong-term responseand the coupling-ca-pacitor recovery. Ifyou let R

S50, the peak

rises to 10V and settleswithin 500 nsec. Thus,

some small resistance, such as 100V, isnecessary for R

S. (DI #2463)

NOTES: ALL DIODES=1N4935 FAST-RECOVERY TYPE.

IN

2.2k

TO CIRCUITDSO

10 mF/NONPOLAR

RS

D1D2

D5

D6

R1

R2

D3

D44.7k

5V

0.1 mF

15V

470

470

F igure 1

Input-protection scheme tops other approachesKannan Natarajan, Mediatronix Private Limited, Kerala, India

Two surge shunt paths, consisting of D1, D2, and D3 to ground or D4, D5, andD6 to ground, provide overvoltage protection.

Tests with a 30V charged capacitor at the input show the circuitsresponse with a horizontal scale of 25 nsec/div (a) and 1 msec/div(b). The long-term response shows the recovery of the couplingcapacitor (c).


F igure 2

(a)

(b)

(c)


ideasdesign

The AD736 true-rms-to-dc convert-er is useful for many applications thatrequire precise calculation of the rmsvalue of a waveform. This converter candetermine the true rms value, the averagerectified value, or the absolute value of amyriad input waveforms. Basically, all ap-plications require both a positive and anegative power supply. According to thedata sheet, you can use the device with asingle supply by ac-coupling the inputsignal and biasing the common pin aboveground. However, the ability to processonly ac signals is a major performancelimitation. You can lift this limitation byusing a level-shifting approach (Figure1). This approach requires more circuit-ry, but it removes the ac-only input-waveform restriction.

The circuit consists of three sections.The first is a differential amplifier thatadds the level-shifting offset, V

REF, to the

input waveform. This amplifiers primaryfunction is to level-shift the waveform,but it can also provide gain and filteringif necessary. The output of the op ampneeds to swing to the value of V

REFmi-

nus the peak negative swing of the inputwaveform times the gain of the op amp(V

REF2(AV

IN)) and to the value of V

REF

plus the peak positive swing of the input

voltage times the gain of the op amp(V

REF1(AV

IN)). By adjusting the value of

VREF

and the gain of the op amp, you caneliminate the need for an expensive rail-to-rail op amp and can then use any sin-gle-supply op amp. All three sections usethe same level-shifting offset, V

REF.

The second section is the rms-to-dc-converter stage. The output of this stageis the dc (rms) value of the input wave-form plus the offset value (V

REF). The in-

put voltage divider reduces the amplitudeof the input waveform. For successfulrms-to-dc conversion, the circuit mustkeep the voltage going into the AD736within the specified range, which is 1Vrms for a V

CCof 65 to 616V. If amplitude

reduction is unnecessary, you can elimi-nate these resistors and simply groundPin 1 of the AD736. The offset voltageneeds to connect to the AD736 (Figure1). This connection provides a referencefor the circuit that is above ground. TheAD736 cannot provide accurate calcula-tions for inputs that go below or evenequal the converters negative rail, 2V

S.

VREF

should be greater than the peak neg-ative swing of the input waveform. V

CC

should be greater than VREF

plus the peakpositive swing of the input voltage.

The third section of the circuit is a lev-

el-shifting circuit, which subtracts VREF

from the output of the AD736. The last-stage differential amplifier can provideany necessary gain, and you can use thisgain to eliminate the need for a rail-to-rail op amp.

The application of the circuit in Figure1 is to measure the current draw of apower supply and detect overcurrentconditions. For this application, only apositive power supply was available. Theinput op amp raises the amplitude of theinput signal and filters out any noisegreater than 5 kHz. The power-supply in-put is a three-phase 60-Hz signal, so theripple frequency is 360 Hz. By providinggain in this first stage and a 5V level shift,any single-supply op amp is suitable.Also, a rail-to-rail op amp is unnecessary.The circuit divides down the output ofthe first stage to be sure not to exceed theinput voltage range of the AD736. Theoutput amplifier provides gain to the dcsignal and level-shifts the signal back toa ground-referenced signal. Again, thegain of this op amp produces a signalwith an amplitude suitable for use withany single-supply op amp. (DI #2466)

+

2+

2

LOAD

VRMS

MC34072

7

47.5k

5

6

1.02k

5V REF

5V REF5V REF

4 8

37

COM

+VS

2VSCAV

OUT

CFVIN

CC

4.87k 294k

33.2k

LIN

RSENSE

COUT

0.0055W1%

330 pF

330 pF

10k

10k

5VREF

0.1 mF0.1 mF

10 mF

10 mF

15V

1k

1k

CURRENT SENSE (+)

CURRENT SENSE (2)

12

3

MC34072

1

2

+

+

1.02k

47.5k

15V

6

5

AD736

F igure 1

Level-shifting nixes need for dual power supplyRon Olmstead, Westcor, Sunnyvale, CA

Level-shifting the input to an rms-to-dc converter allows you to use the converter with only positive supply voltages.


128 edn | january 6, 2000 www.ednmag.com

ideasdesign

Synchronous reset and asynchro-nous reset are both common resetmechanisms for state machines, andthe reset circuit in Figure 1 combines theadvantages of each. Synchronous resethas the advantage of synchroniza-tion between clock and reset sig-nals, which prevents race conditions fromoccurring between the clock and the re-set signal. However, synchronous resetdoes not allow a state machine to operatedown to a dc clock because reset does notoccur until a clock event occurs. In themeantime, uninitialized I/O ports can ex-perience severe signal contention.

Asynchronous reset has the advantageof allowing state machines to operatedown to dc clock. This operation is pos-sible because asynchronous reset imme-diately initializes the state machine whena reset signal occurs independently of theclock. Unfortunately, asynchronous resetmay cause a race condition between thereset signal and the clock. Race condi-tions can cause problems, includingmetastability or wrong-state initializa-tion.

The reset circuit in Figure 1 asserts thereset signal immediately after detectingthe asynchronous reset signal. However,the circuit also synchronizes the reset re-lease with the clock. The circuit uses thissynchronized asynchronous-reset signalto drive a state machine that uses flip-

flops and the asynchro-nous-reset input.

The reset circuit consistsof two back-to-back D flip-flops that synchronize theasynchronous reset signal.In addition, the asynchro-nous reset causes the Dflip-flop outputs to imme-diately go low. Figure 1also shows the correspon-ding signal names for theVerilog description of thecircuit (Listing 1), whichyou can immediately in-corporate into a design orsimulation. Figure 2 showsthe simulation waveformfrom the Verilog code inListing 1 using Altera

Max1PlusII. Observe that the circuit im-mediately asserts the output-reset signal(orst_n) when the system asserts the in-put reset signal, irst_n. Also notice thatthe reset release is synchronous with theclock within two cycles. (DI #2465)

Synchronize asynchronous resetWilly Tjanaka, Philips Semiconductors, Sunnyvale, CA

A simple circuit combines the advantages of asynchronous and synchronous resets.


A STATE MACHINE USING FLIP-FLOPS WITH ASYNCHRONOUS-

RESET INPUT

ASYNCHRONOUSRESET

(IRST_N)

CLR

SYNCHRONIZEDRESET

(ORST_N)D Q

CLR

D Q

CLR

CLOCKSIGNAL(CLK)

F igure 1

IRST_N

ORST_N

CLK

500 nSEC 1 mSEC 1.5 mSECNAME

1

1

0

F igure 2

The simulation waveform shows that the circuit asserts the output reset signal, orst_n, immediatelyafter the system asserts the asynchronous input signal, irst_n, and shows that the reset release issynchronous with the clock signal within two cycles.

LISTING 1VERILOG DESCRIPTION OF THE SYN-CHRONIZED ASYNCHRONOUS-RESET CIRCUIT


ideasdesign

The circuit in Figure 1 can resolve0.1-fF changes in a 100-pF bridge el-ement and can accommodate large-scale changes in the bridge without ad-justment. You can use changes in ca-pacitance to measure applied pressure,rotation, torque, liquid level, the watercontent of toast, and a host of otherthings. Many variants of the circuit arepossible.

IC1, an analog switch, provides both

bridge excitation and synchronous rec-tification. A chopper-stabilized amplifi-

er, IC2, which the circuit configures for a

gain of 2, buffers and amplifies the out-put of the synchronous rectifier, IC

1B. No

amplification occurs before the rectifica-tion stage. IC

1s internal oscillator and an

external capacitor determine the fre-quency of the square-wave excitation sig-nalin this case, 20 kHzthat the cir-cuit delivers to the bridge via IC

1A.

If, as in this case, the excitation wave-form is essentially a square wave, the sys-tem is not oversensitive to oscillator fre-quency and thus not oversensitive to the

supply voltage. This circuit reduces theslew rates of the excitation to reduce EMIand to prevent transient load changesfrom disturbing the reference and buffer,IC

3and IC

4, respectively. Further signifi-

cant reductions in the slew rate cause thefrequency of commutation in IC

1 to af-

fect the output. A delta-sigma ADC, IC5,

resolves the output of amplifier IC2to ap-

proximately 1 ppm.You can use a capacitance change of

this magnitude to measure subtlechanges in dielectric constant, such as

100 mF

IC3LT1460-5

+10 mF

+

10 mF+

8V

6

18

5

2

3

15

2

+

LT1112

IC4

2

+LTC1250

IC2

IC1B

IC5

10k 10k

1k

VCC

VREF

VIN

GND

OSE

SCK

EDO

CS

LTC2400

1

2

3

4

5k

5k

5k

10k

10k

25V

5V

5V

8

11

12

14

7

13

LTC1043IC1A

25V

5V

100 pF

100 pF

100 pF

10 TO 10O pF

100 pF

100 pF

K

5k

1k

150 pF

0.1 mF

3

26

5k

1 mF2

36

12

F igure 1

Circuit resolves 0.1-fF change from 100 pFDerek Redmayne, Linear Technology Corp, Milpitas, CA

Using an analog switch, IC1; a chopper-stabilized amplifier, IC2; a reference, IC3; a buffer, IC4; and a delta-sigma ADC, IC5, this circuit can resolve 0.1-fFchanges in a 100-pF bridge element.


ideasdesign

Circle 9 or visit www.ednmag.com/infoaccess.asp

those that may occur in oil due to con-tamination. For example, if you create acapacitor using 535-in. plates that are 1/4in. apart, the dielectric constant, K, of themedia between the plates could be re-solvable over the range of 1 to 4.5 (22.48to 101.2 pF). A change in K of as little as0.000004 would be measurable. Therigidity and separation between theseplates would have to be constant and sta-ble because movement of as little as 0.3mm would produce the same 0.1-fFchange. The use of low-thermal-coeffi-cient materials would be necessary tomaintain this separation, but this meas-urement is practical with good mechan-ical design.

Other capacitor geometries are possi-ble, of course. For example, the plates ofthe capacitor could be coplanar inter-leaved fingers etched onto an insulator,and the unknown dielectric could eithertouch the surface or be distanced with aninsulator. Also, many configurations ofbridges are possible. For example, youcould devise bridges to compare two sub-

stances. You could also construct bridgesto deflect the field toward the plates ofone capacitor or another, depending onthe K of some substance runningthrough channelsfor example, to com-pare the dielectric constant of two liq-uids. Assuming good sensor design, E-field (ac) measurements can becomparatively free of the effects, includ-ing drift, hysteresis, creep, nonlinearities,thermocouple effects, self-heating, leak-age, and electromigration that compro-mise dc measurements.

The circuit in Figure 1 is usable, butyou can improve the circuits long-termdrift and temperature stability by deriv-ing a timing signal from a quartz oscilla-tor. Note that resolving small capacitancechanges requires diligent attention toparasitics. If a single variable capacitor, asin this example, sits remotely from theother bridge elements, it is recommend-ed that you use shielded cable with theshield driven from either the other bridgearm or even a third arm (see the dashedline in Figure 1). If this situation occurs,

you should route the lower end of thebridge separately to the external capaci-tor. If you plan to bundle these cables,you should use the upper arm of the ex-citation to shield the excitation to thelower end of the unknown capacitor.This cable capacitance loads and henceattenuates the bridge drive, and youshould perhaps use a separate synchro-nized analog switch to sense these loadsto provide a reference signal for ratio-metric operation.

Alternatively, you can ground theshield if the bridge is symmetrical aboutthe midpoint. If the bridge is asymmet-rical, the inputs to IC

1see a substantial ac

component. You can potentially drive anasymmetrical bridge with a transformerand ground the midpoint of the thirdarm to reduce the common mode seen inthe taps. (DI #2464)


Global-system-for-mobile-com-munication phones have asubscriber-identificationmodule (SIM) that allows local wirelessproviders to recognize the user and his orher billing information. Although mostSIMs are changing to 3V operation, theyalso accommodate 5V as well during thetransition. IC

1in Figure 1 combines a

step-up dc/dc converter with a linear reg-ulator, allowing it to regulate up or downfor a range of input voltages. It offershardware-selectable fixed outputs of 3.3and 5V; however, 3.3V is out of spec fora 3V SIM card. With properly chosenR

1/R

2/R

3values, you can switch the reg-

ulated output between 3 and 5V (or anyother two outputs within the allowedrange) by applying digital control to thepower-good input (PGI). The power-good output (PGO), the output of an in-ternal comparator, then changes the ICsfeedback by grounding the node betweenR

2and R

3. If the power-good com-

parator is in use, you can imple-ment the digital control using the 3/5 in-put and an external MOSFET (Figure 2).(DI #2468)

www.ednmag.com January 20, 2000 | edn 113

ideasdesign

Dual-voltage supply powers SIM card ........113

Design formulas simplify classic V/I converter ......................................................114

Rail-to-rail op amp provides biasing in RF amp ............................................114

Circuit multiplexes automotive sensors ......116

Analog switch acts as dc/dc converter ........118

Circuit provides message on disabled phone line ..................................120

Optocoupler isolates shift registers..............122

Tack a log taper onto a digital potentiometer....................................................124



Dual-voltage supply powers SIM cardLarry Suppan, Maxim Integrated Products, Sunnyvale, CA

+

+

INPUT1.8 TO 11V

C1100 mF

C30.1 mF

C44.7 mF

C2100 mF

R3470k/150k

R2100k

R1300k

L110 mH

IC1MAXIM

MAX1672 +

IN LX

PS

OUT

FB

GNDPGND

PG0REF

3 OR5V

9

ILIM0.8A0.5A

PGI6

ONA

ONB5

OFFOFF

3/5

ON

ON5V

3V

F igure 1

+

+

INPUT1.8 TO 11V

C1100 mF

R3

R4

C30.1 mF

C44.7 mF

C2100 mF

R2100k

Q12N7002

R2100k

R51M

R1300k

L110 mH

IC1MAXIM

MAX1672+

IN LX

PS

OUT

FB

GNDPGND

PG0

REF

3 OR5V

9

ILIM

ONA

ONB

5

OFFOFF

3/5

ON

ON

5V3V

PGI6

LOW-BATTERY-DETECTOROUTPUT

OUTPUT LEVELS;NOT LOGIC LEVELS

7

10

F igure 2

You can obtain a regulated 3 or 5V output, according to digital control applied to the power-goodinput (PGI).

This circuit provides the same outputs as the circuit in Figure 1 without tying up the internalpower-good comparator.


ideasdesign

Figure 1 shows a classic voltage-to-current(V/I) converter. You can se-lect the resistor values such that theoutput current in the load, R

L, varies only

with the input voltage, VIN

, and is inde-pendent of R

L. The circuit is widely used

in industrial instruments for supplyinga 4- to 20-mA signal. The circuit has itslimitations, however, because the resistorvalues must be quite accurate to obtain atrue current source. The literature de-scribing the circuit provides design meth-ods that are for special cases or are for ap-proximate designs. This Design Idea givestwo simple design formulas you can useto determine the component values thatproduce a true current source. It also pro-vides a general formula for the outputcurrent, I

L, for any selection of resistor

values, not just the constant-current se-lection.

For a true current output, IL, as a func-

tion of the input voltage, VIN

, you mustsatisfy the following two equations:

In Equation 1, you can arbitrarily se-lect any four of the terms and then de-termine the fifth term by solving the re-sulting equation. In Equation 2, you canarbitrarily select either R

3or R

4and then

determine the unselected resistor aftersubstituting the applicable termsfrom Equation 1. For example,you can solve Equation 1 for R

2when

IL520 mA, R

15100 kV, R

X50.1 kV, and

VIN

54V yields R2549.9 kV. Now, let

R45100 kV and, with Equation 2, solve

for R3

as follows: R35(49.9 kV10.1

kV)550 kV. This example configures adesign for the popular current source of4 to 20 mA. In a second example, if R

X

changes from 100 to 400V, the feedbackchanges fourfold, and you would expectthat the output current would changefourfold, to 1 to 5 mA. You can check theresult by substituting in the general for-mula for the output current:

When the complete coefficient (theterms inside the square brackets) of R

L

equals zero, a true current source results,and equations 1 and 2 are valid. Notethat substituting the values from the firstexample above forces the coefficient tozero. Substituting the values from the

second example above results in the fol-lowing expression:

With RL50.2 kV and V

IN54V, IL5

5.019 mA. Then, with VIN

50.8V, IL5

1.003 mA. Thus, after changing the feed-back resistor by 4-to-1, you still have cur-rents close to the 1- to 5-mA standard.Note also that I

L55.02 mA when R

L50V;

thus, the circuit is still almost a perfectcurrent source. This result is unique, asyou can convert from 4 to 20 ma to 1 to5 mA by changing only one resistor. Youcan configure the less used standard of 10to 50 mA by making R

X5100/2.5540V.

(DI #2471)

Design formulas simplify classic V/I converterDudley Nye, Nye Engineering Co, Fort Lauderdale, FL

.1R

R

R

VI

X

2

1

INL

+

=

.R

R)RR(R

1

4X23

+=

_

+R1

R2

RX

ILRL

R3

F igure 1

Design formulas make this classic V/I convertereasy to use.

.R

R1K where

,)RR(RR

RKR

RR

RRRRRR

/)RKR(VI

4

3

21X2

X2

12

21X21L

X2INL

+=

++

+

+

++

+=

1

.96.59R06.0

V25.75I

L

INL +

=

It is often useful to monitor the dclevel of an RF signal. However, mostRF systems use capacitive coupling;thus, the dc information is lost. The cir-cuit in Figure 1 is an RF amplifier com-prising two monolithic microwave inte-grated circuits (MMICs), IC

1and IC

2,

and a quad rail-to-rail op amp (IC3, an

LT1633). IC3A

restores the dc level at the

output. Inductors at both the input andthe output of the op amp isolate the am-plifier from the RF signal. The isolationis good practice, because frequencieshigher than the bandwidth of the op ampcan undergo rectification in the amplifi-ers input stages, thereby introducing off-set. MMICs IC

1and IC

2 are Hewlett-

Packard HP MSA-0785 devices, which

have an inverting gain of 13 dB; the resultis a total gain of approximately 26 dB anda noninverted signal. IC

1and IC

2have a

3-dB bandwidth of approximately 2GHz. The 1.5-nF blocking capacitors setthe low-frequency cutoff at 2 MHz.

IC1

and IC2

have a 1-dB compressionpoint of 4 dBm, or 1V p-p, into 50V, al-lowing for an input level as high as 18 mV

Rail-to-rail op amp provides biasing in RF ampFrank Cox, Linear Technology Corp, Milpitas, CA

(1)

(2)

(3)

(4)


rms. The maximum output current ofIC

3A, typically 40 mA with a sin-

gle 5V supply, limits the dc levelon the output to 2V into 50V. The out-put saturation (low) voltage of theLT1633, typically 40 mV, sets the mini-mum pedestal voltage. IC

1and IC

2use

constant-current bias sources to stabilizetheir gain with respect to temperature.Two other sections of the quad op amp,IC

3Band IC

3C, form active 22-mA current

sources. You can make the voltage di-viders on the noninverting inputs of IC

3B

and IC3C

adjustable to trim the gain ofthe RF amplifier. The rail-to-rail inputsof IC

3allow the circuit to operate to with-

in 110 mV of the positive rail. (DI #2467)


ideasdesign


IC3B14LT1633

IC3A14LT1633

IC3C14LT1633

IC1HP MSA-

0785

IC2HP MSA-

0785

220 mH

3.9 mH

0.1 mF 0.1 mF

10 nF

10k

1.5 nF

2

+

2

+

2

+

226

10k

5V

VIN VOUT

1.5 nF

50

220 mH

3.9 mH

10 nF

2N39062N3906

5.1

5V

5V

1.5 nF

1k

226

5.1

5V

A simple op-amp-follower circuit with the aid of inductive blocking restores the dc level of an RFsignal.

F igure 1

Often, a mC limits the number of in-put-capture lines to accommodatethe various types of automotivesensors with pulsed outputs, such as ve-

hicle- and engine-speed sensors. The cir-cuit in Figure 1 uses discrete componentsto multiplex two sensors with open-col-lector outputs into a single output, there-

by sharing one input-capture line of themC. The mC selects the sensor whose out-put you will measure. You can apply thisapproach to sensors whose outputs are

Circuit multiplexes automotive sensorsAdil Ansari, Delphi-Delco Electronics, Kokomo, IN

Q3BS170

Q2BS170

Q1CMPQ3906

Q1AMPQ3906

Q1BMPQ3906

Q1DMPQ3906

D21N4148

C10.1 mF

SELECT

FROMmC

R1210k

R81k

R51k

R11k

R21k

R31k

R41k

D11N4148

R101k

R71k R11

1k

R61k

R91k

D35.1V

12V

12V 12V

12V

9

10

SENSOR 11 2

1

3

8

12V

7

14

13

12

1

2

5

6

MUXED_OUT

2 1SENSOR 2

2

F igure 1

You can multiplex the output signals from two sensors into one input-capture line in a mC.


ideasdesign

amenable to time-sharing and do not re-quire continuous monitoring, such asposition sensors. In Figure 1, Sensor 1and Sensor 2 are outputs from two sen-sors using npn transistors with open-col-lector outputs. To enable Sensor 1 or Sen-sor 2, Q

1A or Q

1B , respectively, must turn

on.A logic-low signal from the mC on theSelect input turns off Q

2and Q

1C. When

Sensor 1 input goes low, D1

forward-bi-ases, and Q

1Aturns on, providing a high

signal on MUXED_OUT. When Sensor 1input turns off (high-impedance state),Q

1Aturns off, providing a low signal on

MUXED_OUT. Therefore, when the Se-lect input is low, MUXED_OUT pro-duces pulses that are inverted but syn-chronized with the Sensor 1 pulses.At thesame time, Q

3and Q

1Dare on, turning off

Q1B

and disabling the Sensor 2 input.Similarly, when Select goes high, Q

2

and Q1C

turn on, turning off Q1A

and dis-abling the Sensor 1 input. At the sametime, Q

3and Q

1Dturn off, allowing the

Sensor 2 signal to turn Q1B

on and offwhen Sensor 2 switches on (low) and off(high-impedance state), respectively.Therefore, MUXED_OUT produce puls-

es synchronized with the Sensor 2 input.You can change the values of R

1, R

4, R

5,

and R6to meet the sensors requirements.

D3

clamps MUXED_OUT to CMOS/TTL levels. The use of the MPQ3906,containing four pnp transistors in onepackage, minimizes the number of com-ponents. Similarly, you can obtain arraysof 1-kV resistors in a single package. (DI#2469)


Many low-current devices thatrequire 65V supplies can operatereliably in a single 5V power-sup-ply environment if you use an appropri-ate localized dc/dc converter to generatethe 25V bias. Often, the capabilities andadvantages of these 5V ICs far outweighthe minor inconvenience and added costs

of an additional 25V-converter function.Many companies manufacture dc/dc-converter ICs and modules in a variety ofpower ratings and footprints. However,these typical dc/dc converters can beoverkill for simple, single-chip applica-tions that require only a negative biasvoltage with low operating currents. For

these applications, typical negative- volt-age requirements range from 24 to 26Vwith a supply current of 1 mA, and re-quirements for the 25V supply are gen-erally noncritical.

A lower cost alternative to conven-tional dc/dc converter modules for gen-erating negative dc voltages from a posi-

Analog switch acts as dc/dc converterJohn P Skurla, Advanced Linear Devices Inc, Sunnyvale, CA

IN1

IN4

IN2

D2

C2

D1

IN3

D3

S2S1

S4

D4

S3

GND

V+V2 V+

V+

+

2VOUT

2VOUT

V+

V+

+

+

1

2

3

4

5

6

7

8

16

15

14

13

12

10

9

CLK11

CLK

10 mF

10 mF

10 mF

C110 mF

74HC4316

+

CLK

ALD42137 kHz

(a) (b)

1

2

3

4

5

6

7

8

16

15

10

9

13

NOTES:2V_V+_5V.CLK IS CMOS LOGIC LEVEL WITH FREQUENCY OF 5 TO 500 kHz.V+ IS THE DC-TO-DC INPUT.2VOUT IS THE DC-TO-DC OUTPUT.

< 60-dBREJECTION

80-MHz FULL-POWER BANDWIDTH

FREQUENCY (Hz)

AMPLITUDE RESPONSE (dB)

(a)

(b)

NOTES:C1, C2=FILM TYPE.C3=COG TYPE.C4, C5=CERAMIC BYPASS.

4.09V

F igure 1

You can use fully differential analog inputs, such as those of the LTC1402 ADC, to ac-couple an analog signal without this midsupply bias voltage (a).The circuits frequency response includes a low-cutoff pole at 1 kHz and low-frequency rejection of 260 dB (b).

grounded C1

at the AIN2

input of theADC cancel the low-frequency signalsand provide the basic ac-coupling func-tion. R

2and its shunt capacitor, C

2, at the

ADCs AIN1

input cancel the samplingcurrent bias offset. The optional C

3-R

3

46-MHz lowpass network isolates theADC input from sampling-glitch-sensi-tive circuitry.

The frequency response for the valuesin the circuit has a low-cutoff pole at 1kHz and low-frequency stopband rejec-tion in excess of 260 dB, as set by thecommon-mode-rejection specificationof the ADC, independent of RC-compo-nent-match accuracy (Figure 1b). TheLTC1402 accepts wide bandwidth, full-scale, 4V p-p signals as great as 80 MHz.

This ac-coupling circuit adds no distor-tion to the input signal. You can couplea 1.1-MHz Nyquist frequency sine waveinto the ADC while keeping the THD be-low 282 dB.(DI #2479)


150 edn | February 3, 2000 www.ednmag.com

ideasdesign

Many active-matrix-LCD applica-tions need multiple voltages forthin film-transistor (TFT) bias.Typically, three voltages are necessary: 5Vfor the column driver; a positive voltage,such as 10V; and a negative voltage, such15V, for the TFT gate drive, or row driv-er. For handheld electronic devices, a bat-tery must produce these voltages. Themost popular batteries in these devicesare two-cell NiCd alkaline or one-celllithium-ion batteries.

Figure 1 shows a simple, cost-effectiveway of providing these bias voltages. A

step-up regulator, IC1, forms the heart of

the circuit. This regulator switches at aconstant frequency of 1 MHz and a fixedduty cycle of 70%. IC

1steps up the input

voltage to 5V by storing the energy in theinductor when the internal MOSFET, M

1,

is on and transferring this energy to C1

when M1

is off. IC1s hysteretic gated-os-

cillator control scheme achieves the reg-ulation.

C2, C

3, D

2, and D

3form a charge-pump

inverter to provide an output of approx-imately 25V.When M

1is off, C

2connects

in parallel with C1

through D1

and D2.

Thus, C2charges to V

COL, or 5V. When M

1

turns on, C2

connects in parallel with C3

through M1

and D3. Because of the po-

larity of this connection, C3

charges toapproximately 2V

COL, or 25V.

C4, C

5, D

4, and D

5form a charge-pump

doubler that provides an output of 10V.When M

1is on, C

4connects in parallel

with C1

through D4

and M1. Thus, C

4

charges to VCOL

(5V). When M1

turns off,C

1and C

4connect in series through D

1

and D5, and this series pair connects in

parallel with C5. Thus, C

5charges to ap-

proximately two times VCOL

, or 10V.

Simple active-matrix-LCD bias supply operates from battery inputMichael Shrivathson, National Semiconductor Corp, Santa Clara, CA

++

D5

VGATE(+)10V, 10 mA

VGATE(2)25V, 10 mA

VCOL5V, 250 mA

C53.3 mF

C33.3 mF

C168 mF

C43.3 mF C2, 3.3 mF

D4

D1

D3

D2

IC1LM2621

M1

VIN

500

100 mF200k

150k

7

2

6

39 pF

51k

5 4 3

8

1

6.8 mH

2.2 mFONE CELLLI-ION

F igure 1

A step-up regulator, IC1; a charge-pump inverter comprising C2, C3, D2, and D3; and a charge-pump doubler comprising C4, C5, D4, and D5 produce thethree voltages necessary for active-matrix-LCD applications.


ideasdesign

This circuit provides 250 mA at the 5Voutput, V

COL, with 3% accuracy. The ac

ripple is less than 100 mV. The circuitregulates the 10V output, V

GATE(+), with

5% accuracy, and this output can provide10 mA. The ac ripple at the 10V outputis approximately 30 mV. The circuit reg-

ulates the 25V output,VGATE(1)

, with 6%accuracy and provides as much as 10 mAof output current. The ac ripple voltageat this output is 40 mV. A minimum loadof 25 mA at the V

COLoutput ensures suf-

ficient charge-pump action and thusmaintains V

GATE(+) and V

GATE(1)at their

nominal values. The efficiency of this cir-cuit varies from 75 to 82% when operat-ing from a one-cell lithium-ion battery.(DI #2477)

Pulse-sonar applications requiregenerating bursts of a givenfrequency, duration, and rep-etition rate. Traditionally, the burst gen-erator comprises a crystal oscillator withpulse modulation. But the easiest andcheapest way to generate the bursts is byusing an inexpensive 8-bit mC, such asthe 68HC705KJ1 and 68HC705J1A (Mo-torola) and do the whole job using soft-ware. You can get additional benefits byoutputting two signals in opposite phaseto feed the ultrasonic transducer direct-ly or via a push-pull buffer (Figure 1).Note that only two mC pins are necessaryfor burst generation. You can use the restof the pins for different purposes.

The highest frequency that the mC cangenerate depends on the value of thehighest oscillator frequency, f

OSC, that the

manufacturer specifies and the structureof the instruction set, namely the quan-tity of machine cycles the mC takes to ex-ecute an instruction. With f

OSC54.00

MHz, the mentioned mCs can generate amaximum frequency of 58.8 kHz. Thisvalue is a good match for sonar projectsbecause most of the ultrasonic transduc-ers, working in an air medium, have astandard resonant frequency of 40 kHz.To lower the frequency from 58.8 to 40.0kHz requires a simple delay of 4 msec us-ing nop and brn instructions.

The constant value in the counterNumber determines the burst dura-tion. With one 8-bit counter, the burstduration can range from 0.1 to 3.2 msec.If a longer burst is necessary, you can add

one or two more counters. If you choosea duration of 1 msec, as in this case, thevalue to put into the counter is

How you program the burst, repetitionrate depends on the timer structure of themC. For mCs with 16-bit programmabletimers, the best way is to use either timer-overflow or output-compare functions.For mCs with multifunction timers, onlythe first eight timer stages are usable.Thus, timer overflow occurs every 0.51

msec, which is too short for a repetitionperiod. So, you can use either real-timeinterrupt or, as in this case, organize apacemaker based on the timer-overflow-interrupt. This design generates a burstevery time the counter T rolls over from$FF to $00 with a repetition period of 131msec. You can download the accompa-nying programs from EDNs Web site,www.ednmag.com. Click on SearchDatabases and then enter the SoftwareCenter to download the files for DesignIdea #2480. (DI #2480)

VDD

RESET

OSC1

OSC2 VSS

TR1

TR2

MC68HC705KJ1

100k

6

1

2

3

9

8

A6

A74 MHz

1.5 mF

5V

7

F igure 1

mmC generates a frequency burstAbel Raynus, Armatron International Inc, Melrose, MA

The easiest way to generate bursts for pulse sonar applications is to use a single mmC and do thewhole job in software.



.80SEC 12.5

SEC 1000PERIOD OF HALF

NDURATIO BURSTNUMBER

=

==

m

m


To: Design Ideas Editor, EDN Magazine275 Washington St, Newton, MA 02458

I hereby submit my Design Ideas entry.

Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title

Social Security Number(US authors only)

Entry blank must accompany all entries. (A separate entryblank for each author must accompany every entry.) Designentered must be submitted exclusively to EDN, must not bepatented, and must have no patent pending. Design mustbe original with author(s), must not have been previouslypublished (limited-distribution house organs excepted), andmust have been constructed and tested. Fully annotate allcircuit diagrams. Please submit text and listings by e-mailto [email protected] or send a disk.

Exclusive publishing rights remain with CahnersPublishing Co unless entry is returned to author, or editorgives written permission for publication elsewhere.

In submitting my entry, I agree to abide by the rules of theDesign Ideas Program.

Signed

Date

Your vote determines this issues winner. Vote now, by cir-cling the appropriate number on the reader inquiry card.

Design Idea Entry Blank

ideasdesign

Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award forthe winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,selected among biweekly winners by vote of editors.

Circle 8 or visit www.ednmag.com/infoaccess.asp

Occasionally, you have access to atransformer for powering adc circuit, but its output volt-age is much higher than that required forthe dc voltage. The full-wave-rectifiedand filtered output of an ac input voltageV

X, is V

DC41.414V

X22V

F, where V

Fis

the forward drop in the rectifier (ap-proximately 0.7V). For example, if yourequire 12V dc to power a small coolingfan drawing 100 mA and the ac voltage is18V, a full-wave rectifier and filter resultsin a 24V-dc output. Although you canregulate the voltage down to 12V dc byusing a simple three-terminal regulator(such a mA7812), the result is wastedpower of approximately 1.3W. This wastemeans that you must provide for heat re-moval, somewhat defeating the purposeof including the cooling fan. If you use atypical 1002100-mm, 12V-dc fan ratedat 0.45A, the typical heat loss is approxi-mately 2.5W, increasing to 5W at fullload. In many applications, this level ofloss is unacceptable, so youd have to usean extra transformer secondary, a dc/dcconverter, or a switching regulator. Thecircuit in Figure 1 uses a MOSFET switch

and diode to effectively draw currentfrom the transformer when the voltageis close to the desired level of 12V dc.

The full-wave bridge, D2, rectifies the

18V-ac signal. The diode, D1, and C

1pro-

vide a gate bias voltage of approximately24V dc. This voltage drives the gate of Q

1

through R1, shunted by D

4, which main-

tains the gate voltage at a maximum of12V relative to the source, even duringtransient conditions. As the bridge-recti-fier output increases from 0V to the peakof approximately 24V each half-cycle, thebias voltage holds the MOSFET on untilthe input voltage reaches the breakdownvoltage of D

3(12V) plus the V

BE(ON)of Q

2,

or approximately 12.7V. At that point, Q2

turns on, turning Q1

off. The output fil-ter capacitor, C

2, charges through D

5. As

the rectifier output voltage decreases

from 24 to 0V, Q2

again turns off at ap-proximately 12.7V, allowing Q

1to turn

on and provide another pulse of currentto charge C

2. C

2provides power for the

load between the pulses, which occur at240 Hz with a 60-Hz input. Thus, powerdrain from the transformer occurs inshort pulses, much in the manner of atypical bridge-rectifier/output-filter ar-rangement but at double the frequency.If you want to turn the fan off with a log-ic signal, you can add R

4and D

6. When

you apply a logic-high signal to the input,Q

2conducts, turning the MOSFET off.

(DI #2484)

MOSFET switch provides efficient ac/dc conversionSpehro Pephany, Trexon Inc, Toronto, ON, Canada

C122 mF/35V

C21000 mF/16V

+

+

18V ACSECONDARY

D2WO4M

D11N4004

D61N4148

D31N5242B

R14.7k

R210k

R44.7k

R310k

D41N5242B

D51N4004

Q1STD12NE06

Q22N4401

OPTIONAL SHUTDOWN CIRCUIT

12V FANA

T1

+

2

F igure 1

Using a MOSFET circuit, you can efficiently convert the too-high voltage of a leftover transformer toa lower dc level.

www.ednmag.com February 17, 2000 | edn 149

ideasdesign

MOSFET switch provides efficient ac/dc conversion..........................................149

Passive circuit monitors AES data............150

mC multiplexes DIP switches to I/O port......................................................150

Switched-capacitor IC controls feedback loop ..............................................154

Simple circuit disconnects load ................158

Follow the debouncing flip-flops..............160

Inductorless converter provides high efficiency ..............................................162



The circuit in Figure 1 efficientlymonitors common digital-audio signals. One format forsuch signals is the Audio Engineering So-ciety (AES) 44.1- or 48-kHz standard.Typically, the data consists of a serial datastream with a data rate of approximate-ly 1 Mbps. A lower frequency pulse in-terspersed in the data stream synchro-nizes data frames every 16 to 20 data bits.The amplitude of the data and sync puls-es is 3 to 12V p-p, with one cycle of anac wave representing each bit. The signalsare on a two-wire cable that you can iso-late from ground by using signal trans-formers or capacitors. Several other data-transmission standards use a similar dataformat. An oscilloscope does not reliablytrigger on such a waveform; thus, trou-bleshooting and signal tracing such sys-tems is difficult. The circuit in Figure 1is passive and small and uses no powersupplies. You can keep it in a toolbox,ready for instant use.

The two diodes and associated capac-itors form a voltage doubler to provide abias voltage of approximately 22 to210V. The 2-mA LED connects betweenone of the signal lines and this bias volt-age. Whenever the signal-line voltage ex-ceeds approximately 1.5V, the LED turnson. At a data rate of nearly 1 MHz, theLED appears to continuously glow whengood data is present. The LEDs intensi-ty is proportional to the peak-to-peak

voltage level, so you can easily observelow or high voltage levels. Intermittentlevels, crosstalk, or interference on thesignal causes the LED to flicker. The LEDcircuit is differential and measures thevoltage levels between the two signallines. Common-mode ground noise orhum do not affect the LEDs display. Thevoltage doubler is an efficient way to in-crease the sensitivity of the LED withoutan additional power supply.

The two coupling capacitors samplethe high-frequency data waveform butreject any low-frequency common-modenoise or hum. You can display the datawaveform on an oscilloscope to more

closely inspect the wave shape. The 15-kV resistor and 100-pF capacitor form asimple but effective filter to detect thesync bit in the data stream. You feed thissync bit to the external sync input of theoscilloscope, resulting in a stable displayof the data frame. The coupling capaci-tors avoid creating a ground loop be-tween the signal lines and the grounded,shielded input of the oscilloscope. Youcan readily monitor data amplitude,waveshape, and activity of individual bitswith the oscilloscope. (DI #2482)

Passive circuit monitors AES dataWayne Sward, Bountiful, UT


1N914

1N914

2

3

1

2

3

1

THREE-PINAUDIO

CONNECTORS

1.2k

RED2 mA

270 1 nF

1 nF

1 nF

10 nF1k 2.2k

15k

100 pF

BNC TO SCOPE TRIGGER

BNC TO SCOPE CHANNEL A

F igure 1

A passive circuit gives a good indication of data activity on digital-audio lines.

At times, a mC must read a largenumber of DIP switches, such as forsystem identification, bus-addresssetup, manual configuration, or otherpurposes. However, the available numberof I/O lines is sometimes not enough to

assign a switch to each one. You can usemultiplexer ICs to share one I/O portwith multiple switches, but they compli-cate the circuit, dissipate additional pow-er, and consume precious board real es-tate. Figure 1 shows a method of multi-

plexing 32 DIP switches using only 12 I/Opins and eight pullup resistors. Four 8-bitDIP switches connect in parallel to a sin-gle 8-bit I/O port. A pullup resistor oneach port pin defaults the input to a highstate; a switch closure pulls the input to

mmC multiplexes DIP switches to I/O portGregory Willson, ACS Defense Inc, Warrenton, VA


ideasdesign


ideasdesign

a low state. The key to multiplexing theDIP switches is to ground each set ofeight switches in turn using output pinsfrom a second I/O port.

To deselect a set of switches, the con-trolling-port pin acts as an input, ren-dering it a high-impedance port. In thisway, 12 I/O pins can read 32 switches,and 16 I/O pins can read 64 switches. Se-lect the values of the pullup resistors tolimit the total current into the control-ling-port pin to less than the maximumsink current. Some mCs, such as the Mi-crochip PIC16C6x family, provide theability to enable weak internal pullupson I/O port pins. By using this feature,you can eliminate the eight external pull-up resistors. The code fragment in List-ing 1 illustrates reading the four 8-bitDIP switches and storing the results, us-ing a Microchip PIC16C63 mC. You candownload Listing 1 from EDNs Website, www.ednmag.com. Click on SearchDatabases and then enter the SoftwareDesign Center to download the file forDesign Idea #2483. (DI #2483)

RA0 RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

RA1

RA2

RA3

VDD

VSS

IC1PIC16C63

R1 TO R84.7k

21

22

23

24

25

26

27

28

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

2

3

4

5

20

8

5V

5V

C110 nF

SWITCH_INPUT (7 TO 0)

0

1

2

3

4

5

6

7

F igure 1

Using only 12 I/O pins, a mmC can read 32 DIPswitches. LISTING 1MULTIPLEXING DIP SWITCHES TO SINGLE I/O PORT



ideasdesign

You can implement a simple controlloop with a constant setpoint over awide range of control by using aswitched-capacitor filter. The circuit con-trols motor speed over 1 to 200 Hz or 60to 12,000 rpm. In Figure 1, a NationalLMF40CIWM four-pole lowpass filter isthe heart of the design. This filter has acutoff frequency defined by the clock di-vided by 50. Consider this filter as a dif-ference amplifier that compares the dif-ference between two frequencies. Therelationship between the clock divided by50 and the 500-count encoder divided by2 is such that when the clock rate is 1000times the revolutions per second of themotor, the signal frequency from the en-coder is at approximately the midpoint ofthe filter response. This midpoint is the

point of zero error and is approximately2V p-p. The rectified output serves as thedc setpoint voltage for the control loop.If the motor speed increases, the voltagedecreases, and if the motor slows down,the voltage increases. As simple as themethod is, it can drive a motor-controlchip and provide good speed regulation.

You can use the method to control oth-er servo loops that provide a feedback fre-quency within the range of the filter. Thebig advantage of this scheme is that thesetpoint remains constant with a range ofspeed settings. Another advantage is thatthe clock provides direct speed calibra-tion thanks to the 1000-to-1 relationshipbetween the clock and the rotationalspeed of the motor. Figure 2 shows somecircuit details for enhanced operation. To

cover the higher speed range, you need anadditional divide by 10 to stay within thefrequency range of the filter. An exampleis given for 6- and 60-Hz rotationalspeeds. Conventional op-amp circuitsbuffer and rectify the output of the filter.The application uses one of many full-wave op-amp-rectifier circuits that followa buffer with a gain of 2. After rectifica-tion, the 75-kV resistors and 0.1-mF ca-pacitor provide some filtering and time-constant conditioning.You set the gain ofop amp 1 so its output dc voltage is 2.5Vat the operating point. Op amp 2 offsetsthis voltage and moves the operatingpoint to 0V when no speed error is pres-ent. The offset-adjust trimmer allows forminor variations and calibrates the actu-al rotational speed to the clock signal. Op

Switched-capacitor IC controls feedback loopDave Sargent, IBM Research, San Jose, CA

500-COUNT PER REVOLUTIONMOTOR-SHAFT ENCODER

5 kHz AT 600 RPM (10-RPS) ROTATION SPEED

DIVIDE BY 2

7474

10002RPS CLOCK(FOR 10 RPS, USE 100-kHz CLOCK.)

FILIN

LVSHF

CLKIN

AGND

14

5

1

10

CLOCK450 2 FCO

FILOUT

CLKR

V+

V1

5V

15V

8

3

LMF40CIWMFOUR-POLE LOWPASS FILTER

5V P-P

2V P-P

SLOWER

OPERATING POINT (2.5 kHz)

FASTER

FILTER CUTOFF AT CLOCK/50(2 kHz WITH A 100-kHz CLOCK)

(2.5 kHz)

7

12

CONTROL OPERATING POINTAT 2V P-P

(RECTIFIED SIGNAL IS THE DC CONTROL VOLTAGE.)

F igure 1

A lowpass filter is the heart of a wide-range control loop.


ideasdesign

INDEX OUTOPTICAL

ENCODER

ENCODER CLOCK 500 PER REVOLUTION

DIVIDE BY 10

MC14017

DIVIDE BY 2

74HC74 MC34084

RANGE

30.1

31

BUFFER AND OP-AMP FULL-WAVE

RECTIFIER CIRCUITS

MOTORMOTORDRIVE

CONTROL, DIRECTION,ACCELERATION, BRAKING

START/STOP START/STOP

CONTROLSIGNAL

FROM CONTROL CIRCUITSAND DRIVE CIRCUITS

FILIN

LVSHFCLKIN

AGND

LOWPASS FILTER

V+

V2

25V

FILOUT

CLKR

LMF 40CIWM503 CLOCK

12

7

8

3

14

5

1

10

5V

5V

SPEED CLOCK

+

+

+

+

+

2

2

2

2

2

FROM START/STOPCONTROL CIRCUITS

STOPSWITCH

OP AMP 5

OP AMP 4

OP AMP 3

OP AMP 2

OP AMP 1

CLAMPDIODE4.3V

6

6

2

2

3

3

62

3

INTEGRAL CONTROL

10k 10k0.1 mF

0.1 mF

SELECT RESISTORS FORA NOMINAL 2.5V-DC OPERATING POINT

200k

10k

2k

2k2k

2

36

2

36

LOOP-GAIN SET

PROPORTIONALCONTROL

10k

3.3k

2kSPEEDTRIM

5.1k

75k

75k

CLOCK AT 10003RPS FOR 31 RANGECLOCK AT 10003RPS FOR 30.1 RANGE

EXAMPLES:31 RANGECLOCK=60 kHz.MOTOR SPEED=60 RPS (3600 RPM).LMF40 CUTOFF F0=1200 Hz.ENCODER DIVIDED BY 20=1500 Hz.LMF40 OUTPUT=2V P-P NOMINAL.

30.1 RANGECLOCK=60 kHz.MOTOR SPEED=6 RPS (360 RPM).LMF40 CUTOFF F0=1200 Hz.ENCODER DIVIDED BY 2=1500 Hz.LMF40 OUTPUT=2V P-P NOMINAL.

5V P-P

2V P-P

FILTER CUTOFF AT CLOCK/50(1200 Hz)

SLOWER

FASTER

OPERATING POINT(1500 Hz)

NOTES:ALL OP AMPS USE 612V POWER SUPPLIES.ALL OP AMPS ARE MC34084.

INTEGRATOR

0.22 mF

SET SPEED TRIMFOR NOMINAL 0V OUT AT OPERATING SPEED

APPROXIMATELY 1.25V

F igure 2

A wide-range control circuit uses two ranges for maximum resolution.

amp 3 provides gain for the proportion-al signal.

You can use a fixed resistor in place ofthe 200-kV trimmer. Op amp 4 is an in-tegrator circuit that provides the classicalintegral control for the loop. The inte-grator makes up for errors in the follow-ing control circuits and motor charac-teristics throughout the control range.The integrator control-point outputvoltage therefore changes at different

speed settings. Buffer op amp 5 sums theproportional and integral signals at itsinput. A clamp diode limits the positivedrive voltage and prevents any negativeexcursions from driving the loop to alatch-up condition. In an application, theclamping limits the output to 4.3A, be-cause the motor-control circuit has adrive characteristic of 1A per volt. Whenthe motor stops, the FET stop switchclamps the control signal to zero. Addi-

tional circuits control acceleration rate,braking rate, and direction. The speed ac-curacy for the system is a nominal0.002% throughout the range. The speedclock comes from a DDS chip, and all theabove functions are under control of aPC or front-panel switch settings. (DI#2486)



ideasdesign

Placing a load-disconnect circuiton the output of a boot-strapped step-up regulator al-lows the regulator to start with load cur-rents much higher than would otherwisebe possible (Figure 1). During shut-down, the disconnect completely isolatesthe battery from the load. The circuitboosts a single NiMH-cell output to 3.3Vand delivers output currents to 600 mA.Step-up regulators are excellent forportable applications because they ex-hibit high efficiency, low supply current(120 mA operating, 20 mA in shutdown),and ample current once started. Many,however, cannot start with maximumload from low supply voltages, such asthose from single-cell batteries. Thisproblem arises because most low-voltageCMOS boost regulators derive powerfrom their own outputs, which equal V

IN

minus a diode drop at start-up. Low val-ues of input voltage dont allow theswitching transistor to become fully en-hanced at start-up, so the transistor pres-ents a high impedance that limits thepeak inductor current.As a result, the cir-cuit cannot produce enough current tosimultaneously supply the load andcharge the output capacitor.

To get around this problem and ensurereliable start-ups, most regulator ICs in-

corporate an undervoltage lockout(UVLO). IC

1, for example, is a synchro-

Simple circuit disconnects loadLarry Suppan, Maxim Integrated Products, Sunnyvale, CA

C423220 mF

C50.22 mF

C1100 mFL1

4.7 mH

C20.22 mF

R510

+

Q22N3904

Q1NDS 8434

D1MBR0520L

CLK/SEL

ON

AIN

POKIN

REF

PGND GND

FB

AO

POK

OUT

POUT

LXP, LXN

IC1MAX1703

1M

1M

10, 12 5

R4100k

C30.22 mF

R3100k

R2100k

R1166k

1

3

6

16

9

VOUT3.3V

VIN

14, 11

13

4

8

7

2

NOTE:HEAVY LINES INDICATE HIGH-CURRENT PATHS.

F igure 1

The addition of a couple of transistors enables a switching regulator to start with full load and lowinput voltages.

2

1.8

1.6

1.4

1.2

1

0.8

0.60.01 0.1 1 10 100 1000

LOAD CURRENT (mA)

STAR

T-U

P VO

LTAG

E (V

)

WITHOUT LOAD SWITCH

WITH LOAD SWITCH

(a)

F igure 2

The load-disconnect switch in Figure 1 allows the regulator to start up with heavy loads and low input voltages (a). A slight modification of the circuitin Figure 1 provides 5V-output operation (b).

2

1.8

1.6

1.4

1.2

1

0.8

0.60.01 0.1 1 10 100 1000

LOAD CURRENT (mA)

STAR

T-U

P VO

LTAG

E (V

)

WITHOUT LOAD SWITCH

WITH LOAD SWITCH

(b)


ideasdesign

nous boost converter whose boot-strapped operation cannot start until itsoutput voltage exceeds the internalUVLO threshold of 2.3V. You can over-come this start-up limitation with an ex-ternal power MOSFET, Q

1, operating as

a load-disconnect switch, and by usingthe power-OK (POK) comparator builtinto many low-voltage switching regula-tors. R

3and R

4set the POK threshold at

2.5V, allowing VIN

to rise above the UVLOthreshold. Q

2 inverts the POK output be-

fore driving Q1. Q

1disconnects the load,

allowing VOUT

to rise to a level (aboveUVLO) that ensures full enhancement ofQ

1when it turns on. As a result, the cir-

cuit can start under full load with inputvoltages as low as 0.8V (Figure 2a). Be-cause the circuit takes the regulator feed-back before this switch, the MOSFET youchoose for a given application dependson the load current and minimum ac-ceptable level of load regulation. TheMOSFET shown is a low-threshold de-

vice. Connecting the FB terminal (Pin 2)to ground and removing R

1and R

2pro-

duces a 5V regulated output, whose per-formance is similar to that of the 3.3Vversion (Figure 2b). (DI #2487)


During a recent development ef-fort, we could not find literature de-tailing how to debounce an spst mo-mentary switch using only logic (nocapacitors, Schmitt triggers, or othercomponents). Our application placed thespst switches several feet from the logicboard, and both noisy switches and linetransients caused false triggers. Manymethods simulate a debounce by check-ing the state of the switch on clock edgesand summing the checks over time, butour application required no transitionsduring the qualification time before ac-knowledgment of a keypress. Thus, the switchescan work effective-ly in noisy environ-ments over reasonablylong distances. Figure 1 il-lustrates a means of de-bouncing a momentaryswitch for both the makeand the break operations.Designers often use pro-grammable logic to de-bounce momentary switch-es used in keypads, in key-boards, or as configurationinputs. Flip-flops are usu-ally precious commoditiesin programmable logic,whereas logic gates areavailable in greater abun-

dance. The design in Figure 1 minimizesthe use of flip-flops.

The circuitry monitors the state of theSwitch input. Once the circuit detects atransition, a qualifying time of two De-bounce_Clock periods begins. If at anytime during the qualifying time theSwitch input returns to its original state,indicating switch bounce or an electricaltransient, the circuitry returns to its start-ing state and begins looking for anothertransition. The Switch input must becompletely stable for two positive tran-sitions of the Debounce_Clock input be-

fore the Switch_Debounced output willchange. A frequency of approximately 15Hz (or a period of 66 msec) for the De-bounce_Clock input works well, even forlow-cost,noisyswitches.You can deletethe reset logic if you are unconcernedwith the power-on state of theSwitch_Debounced output. Followingpower-on, the output will be correct af-ter two clock periods. (DI #2481)

RESET

SWITCH

DEBOUNCE_CLOCK

INPUT

INPUT

INPUT

PRN

D Q

CLRN

A

PRND Q

CLRN

B

A

DFF

NAND3

NAND3

NOT

NOT

NOT

NOT

OR2

OR2

B

SWITCH_DEBOUNCED

SWITCH_DEBOUNCED

OUTPUT

OUTPUT

F igure 1

Follow the debouncing flip-flopsRay Scott and John Stanley, Airport Systems International, Overland Park, KS

A debouncing circuit using programmable logic makes frugal use of flip-flops.



ideasdesign

Two common methods exist for gen-erating a regulated dc output voltagethat is lower than the input voltage.The first approach is to use a low-dropout (LDO) regulator. LDO regula-tors are small, easy to use, and in-expensive, but all the outputcurrent must also flow through the input;hence, they exhibit low efficiency. Thesecond approach is to use an inductor-based switching regulator. Inductor-based switchers can be efficient,but they tend to be more complex,costly, and area-consuming than theirLDO-regulator counterparts. A third op-tion retains the simplicity and size of anLDO regulator but enjoys the high effi-ciency usually reserved for inductor-based circuits. The circuit in Figure 1 usesswitched-capacitor techniques to achievehigh-efficiency step-down conversionwithout an inductor.

The circuit produces a regulated 2Voutput with as much as 100 mA of load-current capability. IC

1, an LTC1503-2, has

an input range of 2.4 to 6V,allowing the IC to take pow-er from either a single Li-ion cell or a three-cellNiMH battery. IC

1uses

fractional-conversion tech-niques to achieve efficien-cies typically more than25% higher than that of anLDO regulator (Figure 2).

Internal control circuitry ensuresthat the device operates with theoptimal step-down ratio as theinput voltage and load conditionsvary.You need only four small ce-ramic capacitors to make a com-plete step-down supply. Quies-cent current of 25 mA typical andthe small MSOP-8 package makethe circuit ideal for handheld de-vices. (DI #2485)

Inductorless converter provides high efficiencySam Nork, Linear Technology Corp, Milpitas, CA

LTC1503-2

VIN VOUT

3

C11

C1+ C2+

C21

ONE-CELLLi-ION

ORTHREE-CELL

NiMH

1

2

4

5

6

7

8

VOUT2V/100 mA

10 mF10 mF

1 mF1 mF

SHDN/SS GND

IC1

F igure 1

LTC1503-2

"IDEAL" LOW-DROPOUT

REGULATOR

VOUT=2V IOUT=100 mA

100

80

60

40

202 3 4 5 6

VIN

EFFICIENCY (%)

F igure 2

Eschew bulky inductors, using switched-capacitor step-downconversion.

Switched-capacitor conversion yields higher efficiencythan LDO regulators.


Circle 6 or visit www.ednmag.com/infoaccess.asp Circle 7 or visit www.ednmag.com/infoaccess.asp

www.ednmag.com March 2, 2000 | edn 115

ideasdesign

Abit-error-rate (BER) tester is a ba-sic tool for digital-communicationsmeasurements. Although manycommercial BER testers are available, youcan easily design and build an inexpen-sive version. The scheme in Figure 1 hasperformance similar to that of acommercial tester but requires youto perform a manual calculation basedon displayed data. The tester displays re-ceived bits and received erroneous bits,and you must calculate the BER data us-ing a handheld calculator, for example.

You can build the tester in Figure 1from a piece of programmable logic, suchas an FPGA or a CPLD, and two countermodules. You can buy the counter mod-ules in kit form or in built form from nu-merous suppliers. The counters are avail-able in LCD or LED-display formats withfour or more digits. The counter modulesmust have overflow indicators, and theymust allow pulse widths that are as nar-row as half the data-clock period.

Figure 2 shows the core of the error de-tector. This detector uses the samepseudorandom-bit-sequence (PRBS)

generator as the transmitter does butadds a trick. When the demodulator un-der test is not in lock, the shift registerloads the receive data, and no error counttakes place. In every demodulator, exceptfor special burst-mode units, the BER de-

creases to some nominal rate before youdeclare the system locked. Thus, theshift register is self-synchronized to theincoming sequence with great probabil-ity. When the demodulator is in lock, theLock signal switches the multiplexer out-

BITDIVIDER

ERRORDIVIDER

ERRORDETECTOR

KEYBOARDCONTROLLER

MONOSTABLE

BIT_CNT

BIT_RST

ERR_CNT

ERR_RST

BIT COUNTER

ERROR COUNTER

ERROR

STARTSTOP

RESET

RXC

RXDLOCK

ERR_OFL

COUNT_ENABLE

COUNT

BIT_OFL

C_ENABLE

C_RST

F igure 1

Simple BER meter is easy to buildLuis Miguel Brugarolas, Sire Sistemas y Redes Telmticas, Tres Cantos, Madrid, Spain

With some programmable logic and two counter modules, you can design and build a simple bit-error-rate tester.

Simple BER meter is easy to build ..........115

Software avoids interrupt overhead........116

Delay line eases Spice dead-time generation......................................................118

Comparison macro for PICprocessors......................................................122

Bridging enhances filter close-inselectivity........................................................122

Notch filter is insensitive to component tolerances ..........................126


SHIFTREGISTER

RXDATA

RXLOCK

PRBSERRORCLK QN

QM

0

1

F igure 2

In the error-detector core, the Lock signal controls whether the shift register loads with receiveddata or the locally generated pseudorandom bit sequence (PRBS).

116 edn | March 2, 2000 www.ednmag.com

ideasdesign

put so that locally generated data, whichshould be the same data as the transmit-ted data, shifts into the register while themeasurement is running. Any divergencebetween the received data and the local-ly generated data constitutes a bit error.As long as the counter counts pulses, theerror signal must combine with the clockin an RZ format so that the tester doesnot count two consecutive errors as onlyone.

An error that occurs just before the de-modulator is in lock causes incorrect ini-tialization of the shift register, and the lo-cal and received sequences is highlyuncorrelated. Thus, the BER in this caseis close to 0.5. You can easily detect thiserroneous condition and restart themeasurement.

The architecture in Figure 1 allows youto divide the number of errors and bits inthe error-divider and bit-divider blocks.You can divide errors by 1, 10, 100 and1000 and divide bits by 104, 105, 106, and107. This division feature allows the testerto measure of a range of BERs from poorones for which the tester must divide theerror count to a low value to situationsthat require bit division or that entaillong measurement periods. Two switch-es for each block can control the divisionrate in a simple way. To avoid mistakes,division control should also control adecimal point in the display, and an in-dication label under the displays shouldshow the multiplication factor for the ac-tual configuration.

Another feature is related to the over-

flow.When either counter unit overflows,the scheme in Figure 1 immediately stopsthe error count using the BIT_OFL andERR_OFL flags so that the tester does notdisplay erroneous data when taking un-attended measurements or when takingmeasurements for long periods. Whenactive, the BIT_OFL and ERR_OFL flagsturn off the COUNT_ENABLE signal.

The Start, Stop, and Reset keys controlthe unit. They drive a finite state ma-chine, which produces the variablesC_ENABLE and C_RESET. The first vari-able controls the bit and error count, andthe second controls the counter reset. (DI#2488)

You can service peripheral ICs con-nected to a mC by polling or via in-terrupts. The polling method can betime-consuming, so interrupt handling isoften preferable because the mC has totake care of the peripheral only on re-quest. However, each separate interrupt

causes the mC to stop normal programexecution, save its current state on thesystem stack, and vector to the interruptsprocessing function. The first instruc-tions in the interrupt function normallypush some or all registers used onto thestack.

Peripherals, such as the 16550 UART,that have more than one interruptsource, may require that the mC processmore than one request at a time. Fortu-nately, you can write software that allowsthe mC to process more than one requestin one interrupt cycle. Thus, the interrupt

Software avoids interrupt overheadHans-Herbert Kirste, WAGO Kontakttechnik GmbH, Minden, Germany

LISTING 1STANDARD INTERRUPT-HANDLING SOFTWARE LISTING 2MORE EFFICIENT INTERRUPT-HANDLING SOFTWARE


Generating complementary clocksignals in a Spice simulation is aneasy task. However, this task getsmuch harder if you need to introducesome dead time into the signals. This dif-ficulty is especially true when youre deal-ing with a variable-pulse-width-modu-lated switching cycle. In fact, you need to

insert a dead-time interval between theswitching of any two power devices in se-ries, such as bridge or half-bridge designsthat use MOSFETs and switch-modepower supplies and that implement syn-chronous rectification. The dead timeprevents any cross-conduction, or shoot-through, between both switches and

helps to reduce theassociated losses.

The circuit inFigure 1a over-comes this typical

Spice problem. The input clock drivestwo delay lines that feature the same spec-ifications. When the clock goes high, oneinput to X2s AND gate is also high. How-ever, because of the delay line, the otherinput stays low for the given dead time.When both inputs are high, the output isa logic one (Figure 1b).

When you generate models in a pro-prietary syntax, the translation process toanother platform is usually painful. How-ever, thanks to common Spice3 primi-tives, such as the delay line, T, the trans-


ideasdesign

UTD

UTD

CLK

X3INV

X1UTD

X2AND2

X4UTD

X6AND2

2

4 5

Q

QB

F igure 1

Delay line eases Spice dead-time generationChristophe Basso, On Semiconductor, Toulouse, Cedex, France

Two AND gates and two delay lines generate a dead-time element inSpice (a). When both inputs are high, the output is a logic one (b).

LISTING 1HALF-BRIDGE DRIVER IN ISSPICE4

overhead occurs only once. The result isimproved system performance.

Listing 1 is an example of standard in-terrupt-handling software. Standardpractice involves vectoring, pushing, andpopping registers for each interrupt re-quest. A more sophisticated function in

Listing 2 tries to handle as many inter-rupt requests as the peripheral requires.This function processes multiple reads tothe identification register, and theprocess repeats until the mC has servicedall sources. You can download both list-ings from EDNs Web site, www.

ednmag.com. Click on Search Databas-esand then enter the Software Center todownload the file for Design Idea #2489.(DI #2489)


(a)

(b)


ideasdesign

lation of this generator is easy to imple-ment. The netlists in listings 1 and 2 im-plement a half-bridge driver with a float-ing upper output in IsSpice4 (Intusoft)and Pspice (OrCAD), respectively. TheBL (Listing 1) and EBL (Listing 2) inlineequations implement the AND gates ofFigure 1a, which saves you from using asubcircuit arrangement. Typical applica-tions include half-bridge drivers and syn-chronous rectifiers. You can easily tailorany output polarity by reversing the cor-responding Spice element. For instance,if you want to reverse the upper genera-tor, BU1, in Listing 1, simply replace theline V5(V(CLK).800M) &(V(TD1).800M) ? {VHIGH} : {VLOW}with V5(V(CLK).800M) & (V(TD1).800M) ? {VLOW} : {VHIGH}.

Figure 2a portrays a typical applica-tion of the dead-time generator in a sim-plified half-bridge driver, and Figure 2bshows the corresponding IsSpice4 wave-forms. You can download both listingsfrom EDNs Web site, www.ednmag.com.Click on Search Databasesand then en-ter the Software Center to download thefile for Design Idea #2490. (DI #2490)

22MTP10N10E

23MTP10N10E

7

QUG

S

GQL

DEAD-TIMEGENERATOR

CLOCK

1

+

VC

+VCC40V

8

+

IIN

DT=350 nSECVHIGH=10VLOW=100 mVRS=10

RGL12

RGU12

VGL

g

g

6

5 4RLOAD10

VGU

VOUT

F igure 2

A typical application for the Spice dead-time generator is for simulating the operation of a half-bridge driver (a). IsSpice4 waveforms show a dead time of 350 nsec (b).


LISTING 2HALF-BRIDGE DRIVER IN PSPICE

(a)

(b)


ideasdesign

If you ever get tired oftrying to remember thesubtleties of the carrystatus bit every time youwant to use the subtract in-struction to perform a com-parison, the macro in List-ing 1 can help. (You candownload a copy of the list-ing from EDNs Web site,www.ednmag.com. Click onSearch Databases andthen enter the SoftwareCenter to download the filefor Design Idea #2493.) Themacro contains all of thenuances, once and forever.The macro reads like a sen-tence: branch to target ifram-register is [comparisoncondition] a literal value.The comparison conditionsavailable are equal-to,not-equal-to,below,andabove-or-equal. Thewords below,above, andothers adhere to the Intel/Microsoft as-sembly-language convention of referringto unsignedcomparisons for which thebyte value can range only from 0x00(decimal zero) to 0xFF (decimal 255).

Although you can use this macro forequaland not-equalcomparisons, itsreal power comes in examining a value in

edn design ideas 2000

Documents

output duty cycle

lowpower pwm circuit

low output levels

andthe output waveform

output of ic1ais high

output of schmitt inverter

whenthe output of ic1ais

duty cycle variable