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readerS SOLVe deSIGN PrOBLeMS

EditEd By Martin rowEand Fran GranvillE

designideas

[www.edn.com] July 28, 2011 | EDN 51

Nonlinear systems often need tobecome linear to be useful, and the

circuit inFigure 1 provides a nonlinearsawtooth pulse for a PWM (pulse-widthmodulator) that can compensate for non-linearities in sensors, controllers, or sys-tems. The circuit outputs a linear saw-tooth pulse, a quadratic parabolic pulse,and a cubic parabolic pulse of equal and

constant width following an external trig-ger pulse. All pulses have equal peakamplitudes.

The circuit incorporates a cascade ofthree synchronously switched integra-tors. IC

3s S

2D

2switch switches the input

of integrator IC2D

, the first in the chain,to the source of reference voltage V

REF.

You need two integrators employing IC2D

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To see all ofEDNs DesignIdeas, visit www.edn.com/designideas.

PRE

CLR

Q

D QPRE

CLR

Q

D QIC6SN74-AHC74

IC6SN74-AHC74

TRIGGERINPUT

GND

VDD

VSS

0V

VIN

TRIMNC

GND

GND

GND

VOUT

VREF

COMPIC

1

ADR433

IC3

ADG1213

IC5

ADCMP-

609

RCOMP

82k

CCOMP

10 nF

100 nF

100 nF

330

3

2

7

14

56

8

NC

5V

S1A

D1

IN1

IN2

D2

S2A

S1B

S2B

VDD

VDD

VSS

S2

S1

D2

D1

IN2

IN1

S3

S4

D3

D4

IN3

IN4

15V

RB

20k

0.1%

22 nF

IC2D

ADA4062

IC2C

ADA4062

IC2A

ADA4062

V+

100 nF

RIL

RIQ

RD1

2k

0.05%

RD2

3k

0.05%

CIL

CIQ

RINV1

RINV2

VOUTL

VOUTC

VOUTQ

RIC

CIC

OUTPUTS

V

15V

INTEGRATE

IC4

ADG1236

t2

t3

t

IC2B

ADA4062

NOTE: RIL

=RIC

=RINV1

=RINV2

.

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designideas

52 EDN | July 28, 2011 [www.edn.com]

and IC2C

to generate a quadratic para-bolic pulse. The third integrator, usingIC

2B, lets you simultaneously generate

a cubic parabolic pulse. Each integra-tor has a series input switch and a resetswitch that connects in parallel with arespective integrating capacitor.

The S1A

D1

switch in IC4

is a resetswitch for integrator IC

2D. The comple-

mentary S1B

D1

switch serves as a seriesinput switch for integrator IC

2C. Similarly,

the S2A

D2switch is a reset switch for inte-

grator IC2C

. The S2B

D2

switch is a seriesinput switch for integrator IC

2C. The

positions of all switches are at logic high

at all control inputs: IN1 to IN4 of IC3 andIN1

and IN2

of IC4.

Integrators IC2D

and IC2C

also haveinput-grounding switches in IC

3, S

1D

1,

and S3D

3, respectively. The grounding

switches ensure that error due to leakage

currents of the series switches is approxi-mately 50% less than that of a design notusing the grounding switches.

The Integrate logic signal controlsall series switches. When the signalis high, it turns on all the reset andgrounding switches. Thus, integratorsIC

2B, IC

2C, and IC

2Dare either integrat-

ing their respective analog input signalsor resetting to a 0V output. The input ofintegrator IC

2Dswitches to the output

of precision voltage-reference cell IC2A

.Thus, signal V

OUTLbecomes a negative

sawtooth pulse. The pulse varies withinits duration, T

1, as:

VOUTL

(t)VOUTLPEAK

tT1

.

Inverter IC2A

inverts this pulse. IC2A

has a voltage gain of negative one becausepositive pulses are more common.Integrator IC

2Bintegrates sawtooth pulse

VOUTL

; IC2B

therefore outputs a quadraticparabolic pulse:

VOUTQ

(t)VOUTQPEAK

tT1

.( )2

The equation describes a pulse thatintegrator IC

2Bsimultaneously integrates,

producing a cubic parabolic pulse:

VOUTC

(t)VOUTCPEAK

t

T1.

( )

3

VOUTLPEAK

, VOUTQPEAK

, and VOUTCPEAK

arenegative or positive voltage peaks at theoutputs of their respective integrators.T

1is the width of the Integrate pulse.

Theoretically, to achieve VREF=V

OUTLPEAK

=VOUTQPEAK

=VOUTCPEAK

, you must stag-ger the integrating time constants ofthe respective integrators as 1-to-1/2-to-1/3, respectively. In this case, however,V

REF

=3V, whereas VOUTLPEAK

=VOUTQPEAK

=

VOUTCPEAK

=5V.You must multiply the 1 in the stag-

gering ratio by 3/5. Considering the timeconstant of integrator IC

2C, you get a stag-

ger ratio of 6/5-to-1-to-2/3. For the equalvalues of integrating resistors R

IL=R

IQ=R

IC,

this staggering holds true for the valuesof respective integrating capacitors. Thecircuit uses a high-quality, SMD (surface-mount-device) ceramic capacitor, C

IQ,

with a value of 2.3692 nF. To achievethe necessary precision staggering, C

IL

comprises 2.4016-nF, 343-pF, and 79-pFcapacitors in parallel. C

ICis a parallel com-

bination of 1067 pF and 499 pF.A rising edge at the trigger input forces

the Integrate signal low, which turns off thereset and grounding switches and turns onthe series switches. The integration lastsuntil V

OUTQPEAK=5V, forcing the output of

IC5low, which in turn sets Integrate high.

Thus, the series switches are off, and thereset and grounding switches are on. Thecircuit remains in this steady state untilthe next rising edge at the trigger input.

The Analog Devices (www.analog.com)ADG1213 and ADG1236 switches workwell in this design because of their chargeinjection of 1 pC or less.Figure 2 showsthe circuits high precision, depicting linearand quadratic-parabolic-pulse shapes.EDN

In most cases, you measure currentby converting it into a propor-

tional voltage and then measuring thevoltage. Figure 1 shows two typicalmethods of making the conversion. Inone method, you insert a probing resistor,R

P, in series with the current path and

use differential amplifier IC1

to measurethe resulting voltage drop (Figure 1a).A second method is a widely knownoperational amplifier current-to-voltage

converter in which inverted IC1s output

sinks the incoming current through thefeedback resistor (Figure 1b).

In the first method, the same currentthat flows into one node flows from thesecond node, but a significant voltagedrop occurs across probing resistor R

P.

In the second method, the voltage dropis on the order of tens of microvolts tomillivolts, depending on IC

1s quality,

but the measured current flows only

into the sensing node with no returnto the circuit. You can measure onlycurrents flowing to ground.

The circuit inFigure 2 operates in

a somewhat similar manner to the oneinFigure 1b in that an op amps outputsinks the incoming measured current.However, the other op amps outputsources an equal outgoing current backto the circuit under test.

In Figure 2, input current I flowsthrough R

1into the output of IC

2, which

reduces its voltage by the amount of IR1

relative to the input node. That voltageequals the voltage mean of the op ampsoutputs, which R

3and R

4set at the op

amps inverting inputs. Consequently,

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designideas

54 EDN | July 28, 2011 [www.edn.com]

the output of IC1

must rise to a voltageof IR

2relative to the inverting inputs

and the equal-voltage noninvertinginput node of IC

2. IC

1sources this cur-

rent, which returns through R2

to thecircuit under test. R

1

=R2

, so the outputcurrent is the same as the input current.Because the op amps outputs maintain

their inputs at equal voltages, the circuitunder test has virtually no resistance.

The circuit in Figure 2 has theadvantages but not the drawbacks ofthose in Figure 1. The current thatflows into the first node flows fromthe other node, and the voltage dropis almost zero; the maximum is twice

the input offset voltages. You can usethis circuit in a circuit under test with-out changing the voltage and currentflows.EDN

IC1

IC2

R10.5k

R31k

R41k

R20.5k

VO=I(R1+R2)

I

I

VI=0

R1=R

2

R3=R

4

IC1

R1

RP

R2

R4

R3

VO=kVI

R1=R2R3=R4

I

I

VI=IRP>0

(a)

Testing power supplies or dis-charging batteries usually requires

a constant-current load. Sometimes,however, you must study the behaviorwhen the load is a resistor. Using a high-power potentiometer is an expensiveapproach that might not be worth thecost. The circuit inFigure 1, which per-forms like a high-power resistor that con-nects between P

1and P

2, provides an

alternative approach.To understand how the circuit works,

assume that the op amp is ideal and thatthe total resistance of R

2and R

3exceeds

that of a high-power resistor (notshown). R2

and R3

form a divider thatproduces an output voltage, accordingto the following equation:

VREFV

IN

R2

R2R

3

.

The operational amplifier maintains avoltage, such that R

1s voltage equals the

reference voltage, that causes the currentthrough R

1to be:

IR1

VR1

R1

VREF

R1

,

Substituting the first equation in the sec-ond equation yields:

IR1

VIN

R1.V

IN

R2

R2R

3

R1(R2R3)

R2

If you neglect the current through R2and

R3, then R

1s current equals the input cur-

rent, as the following equation describes:

.IINVIN R1(R2R3)

R2

This equation shows a linear relationshipbetween the input current and the inputvoltage. Thus, the circuit between P

1and

P2

acts as a resistor. The equation thenbecomes:

.R R1 R2IIN

VIN

R2R

3R

1k

where k=(R2+R

3)/R

2is a factor greater

than 1, which multiplies R1. Making

either R2

or R3variable lets the circuit

function as a variable resistor. The costof a suitable transistor and R

1, along

with the rest of the components, issmaller than that of a variable poten-tiometer that can dissipate the sameamount of power.

The circuit has some limitations, how-ever. First, it can accept input voltages

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VREF

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R2

R1

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P1

P2

IR1

IIN

VIN

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(b)

VI=0

I

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[www.edn.com] July 28, 2011 | EDN 55

You must minimize noise whenmeasuring ripple in power rails

because the ripples amplitude can below. Oscilloscope probes are essentialmeasurement tools, but they can intro-duce noise and errors. Ground leads,such as those that attach to standardoscilloscope probes, can add noise thatsnot present in your circuit to an oscil-loscopes trace. The wire loop acts as anantenna that picks up stray magneticfields. The larger the loop area, themore noise it picks up. To prove this

theory, connect the oscilloscope groundlead to the probe tip and move itaround. The oscilloscope will show thenoise increasing and decreasing withthe ground-lead movement. You can usean oscilloscope probe with its groundlead and sockets to build a simple inter-connect board (Figure 1).

Start by removing the probes cover,which reveals the probe tip. There is ashort distance between the tip and theground ring. You need one of two sockets:a right-angle, or horizontal, socket or a

vertical socket, similar to those inFigure1. Solder the center leg of the socket tothe output of the power supply and solderthe other leg to the power-supply return.Connect a 0.1-F surface-mount, stackedceramic capacitor between the two sock-ets. This step limits the probe bandwidthto approximately 5 MHz, which furtherreduces high-frequency noise and letsthe lower-frequency ripple pass through.Figure 2 shows the completed intercon-nect board, andFigure 3 shows a sche-matic of the board. Insert the probe tipinto the socket to measure ripple. Youwill get a ripple measurement withoutspikes or other noise.

You should use a multilayer stackedceramic capacitor because its betterat decoupling high-frequency noise.Electrolytic, paper, and plastic-filmcapacitors comprise two sheets of metalfoil. A sheet of dielectric separates themetal-foil sheets, and these three com-

ponents form a roll. Such a structure hasself-inductance; thus, the capacitor actsmore like an inductor than a capacitorat frequencies higher than a few mega-hertz.Figure 4 shows the impedance tothe power supply for various stacked-ceramic-capacitor values.EDN

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J2

C10.1 F

1000 pF100 pF

2.2 F

0.1 F

0.01 F

0.001 0.01 0.1 1 10 100 1k 10k

0.001

0.01

0.1

1

10

100

1k

10k

100k

1M

IMPEDANCE ()

FREQUENCY (MHz)

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of only one polarity, which might limitits use in some applications. Second, theminimum resistor value is the value of R

1

plus the transistors minimum on-resis-tance. Other factors such as op-amp offset,

the values of R2and R

3, and input voltage

influence the circuits linearity, but thecircuit still achieves high performancewith low-cost components. Dependingon the op amps input range, the circuit

requires an external dual power supply.Figure 2 shows a prototype of the testedand built circuit using a potentiometer forchanging the equivalent resistance andno heat sink on the power transistor.EDN