ee 466/586 vlsi design - eecs.wsu.edudaehyun/teaching/2019_ee466/lecture_notes/lecture_13.pdflogic...
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Lecture 13 More on Gates
CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device
sizes; ratio less Always a path to Vdd or Gnd in steady state; low
output impedance Extremely high input resistance; nearly zero steady-
state input current No direct path between power and ground; no static
power dissipation Propagation delay function of load capacitance and
resistance of transistors N fan-in gates need 2N transistors
Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
FVSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
Ratioed Logic VDD
VSS
PDNIn1In2In3
F
RLLoadResistive
N transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
Active Loads VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
F
VSS
PDN
DepletionLoad
PMOSLoad
depletion load NMOS pseudo-NMOS
VT < 0
Pseudo-NMOS VDD
A B C D
FCL
VOH = VDD (similar to complementary CMOS)
kn VDD VTn–( )VOLVOL
2
2-------------–
kp
2------ VDD VTp–( )
2=
VOL VDD VT–( ) 1 1kpkn------–– (assuming that VT VTn VTp )= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
Pseudo-NMOS VTC
0.0 0.5 1.0 1.5 2.0 2.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
V in [V]
V o u
t [V
]
W/L p = 4
W/L p = 2
W/L p = 1
W/L p = 0.25
W/L p = 0.5
Performance of pseudo-NMOS Inverter
Size VOL(V) Static Power Dissipation
tplh
4 0.693 564 μw 14 ps
2 0.273 298 μw 56 ps
1 0.133 160 μw 123 ps
0.5 0.064 80 μw 268 ps
0.25 0.031 41 μw 569 ps
Improved Loads
A B C D
F
CL
M1M2 M1 >> M2Enable
VDD
Adaptive Load
Improved Loads (2) V DD
V SS
PDN1
Out
V DD
V SS
PDN2
Out
A A B B
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
DCVSL Example
B
A A
B B B
Out
Out
XOR-NXOR gate