ee 560 chip input and output (i/0) circuits -...
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![Page 1: EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS - Karadimoveducypedia.karadimov.info/library/EE560_IO_Ckts.pdf · 2002. 10. 7. · kenneth r. laker, university of pennsylvania 2-> esd](https://reader035.vdocument.in/reader035/viewer/2022081623/613e516259df6428461673b4/html5/thumbnails/1.jpg)
EE 560 CHIP INPUT AND OUTPUT (I/0)CIRCUITS
1
Kenneth R. Laker, University of Pennsylvania
![Page 2: EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS - Karadimoveducypedia.karadimov.info/library/EE560_IO_Ckts.pdf · 2002. 10. 7. · kenneth r. laker, university of pennsylvania 2-> esd](https://reader035.vdocument.in/reader035/viewer/2022081623/613e516259df6428461673b4/html5/thumbnails/2.jpg)
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-> ESD PROTECTION CIRCUITS (INPUT PADS)-> ON-CHIP CLOCK GENERATION & DISTRIBUTION-> OUTPUT PADS-> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE-> SUPER BUFFER CIRCUIT DESIGN-> LATCH-UP PHENOMENON
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3
ESD PROTECTION
1 MΩ
100 pF
1.5 kΩ
DUT+−V
esd
HUMAN BODY MODEL MACHINE MODEL
1 MΩ
200 pFDUT+
−Vesd
ESD TESTERS: LUMPED ELEMENT MODELC
S
CC
DUT+
-V
LS
RS C
t
I Component HBM MMC
C (pF) 100 200
RS (Ω) 1500 25
LS (µΗ) 5 2.5
CS (pF) 1 0
Ct (pF) 10 10
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VDD
input pin
to circuits on dieV
A
-0.7 V < VA < V
DD + 0.7 V
PROTECTIONNETWORK (PN)
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5
VDD
PNA
E
XINPUT SERIES TRANSMISSION GATE CIRCUIT
TGA
E
X
A -> EXTERNAL (OFF-CHIP) input signalE -> INTERNAL (ON-CHIP) enable signalX -> INTERNAL (ON-CHIP) output signal
X = A, when E = 0X = HIGH-IMPEDANCE STATE when E = 1
NOTE: ANY UNUSED INPUT TERMINALS SHOULD BE TIED TOV
DD OR GND USING PULL-UP OR PULL-DOWN RESISTORS
RATHER THAN FLOAT
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VDD
PNA XA X
INVERTING INPUT CIRCUIT
VOL
= 0.8 V
NMH
NML
VOH
= 2.0 V
TTL
Vin
= A
CMOS
VIH
VIL
Vth
Vout
= X
VOH
= VDD
Vth
VOL
= 0
Vout
= V
in
VIL V
IH2.0
Vin
= A
0.8
LEVEL SHIFTING FROM TTL TO CMOS
DESIGN FOR Vth
= 1.4 V
X = A
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Vout
= X
VOH
= VDD
Vth
VOL
= 0V
IL VIH
2.0V
in = A
0.8
PM-NM
PH-NL
PL-NH
PM-NM => nominal processingPH-NL => strong pMOS, weak nMOS process cornerPL-NH => weak pMOS, strong nMOS process corner
VARIATIONS IN LEVEL SHIFT VTC DUE TO PRCESS VARIATIONS
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VDD
PNA
XA XTTL
X = A
NON-INVERTING TTL LEVEL-SHIFTING CIRCUIT
Kenneth R. Laker, University of Pennsylvania
8
Schmitt Trigger
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Kenneth R. Laker, University of Pennsylvania
9OUTPUT CIRCUITS AND L(di/dt) NOISE
Z
CK
D
CKV
DD
D
ZCK
VDD
Z
D
CK
TRISTABLE OUTPUT CIRCUIT
Z = D for CK = 1Z = HIGH IMP for CK = 0
12 transistors
6 transistors
LargeW/L
LargeW/L
LARGE W/L-> Sufficent current sink, source-> Reduce delay times
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Kenneth R. Laker, University of Pennsylvania
10LARGE W/L-> Sufficent current sink, source-> Reduce delay times
=> LARGE di/dt
L (di/dt) VOLTAGE DROP ACROSS BONDING WIRECONNECTING PAD TO PACKAGE PIN
t
VOH
VOL
Vin
, Vout
T/2 T
t
nMOSON
nMOSON
pMOSON
iC
0 tst
s/2
Imax
iC(t)
t
Imaxts2
≈ CloadVDD
Imax ≈ 2CloadVDD
ts
didt
max
≥ Imaxts/ 2
= 2 Imaxts
≥ 4 CloadVDD
ts( )2
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Kenneth R. Laker, University of Pennsylvania
11
LET Cload
= 100 pF, L = 2 nH, VDD
= 5 V and ts = 5 ns
HIGH-END MICROPROCESSOR CHIPS WITH 32 BITS OR 64BIT DATA BUS LINES - ALL OTPUT DRIVERS SWITCHING ATTHE SAME TIME!
didt
max
≥ 4CloadVDD
ts( )2
didt
max
≥4 100x10−12( ) 5( )
5x10−9( )2 = 80mAns
didt
max
≥ 160mVL
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VDD
D
ZCK
ST
PRECHARGES INVERTER OUTPUT “Z” TO VDD
/2 WHEN ST = 1AND CK = 0 (JUST PRIOR TO CK -> 1)
REDUCE L(di/dt) NOISE
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Kenneth R. Laker, University of Pennsylvania
13BIDRECTIONAL BUFFER CIRCUIT WITH TTL INPUTCAPABILITY
Z
E
D
E
TS
TTLDI
VDD
D
ZE
VDD
PN
DI
Level Shift
Reduce di/dt Noise
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Kenneth R. Laker, University of Pennsylvania
14ON-CHIP CLOCK GENERATION AND DISTRIBUTION
CK
CK
RING OSCILLATOR
SIMPLE ON-CHIP CLOCK CIRCUIT
CK FREQUENCY-> PROCESS DEPENDENT-> UNSTABLE
Rbias
CrystalC
1 C2
PIERCE CRYSTAL OSCILLATOR CIRCUIT
-> GOOD FREQUENCY STABILITY
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Kenneth R. Laker, University of Pennsylvania
15TWO-PHASE CLOCKING SCHEMES
phi1
phi2
Tc
clk phi1
phi2
CLOCKDECODER
PRIMARYCLOCKS FROM
XTALCONTROLLEDOSCILLATOR
CK1CK2CK3CK4
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16
CLOCKGEN
GENERAL LAYOUT OF H-TREE CLOCK DISTRIBUTIONNETWORK FOR UNIFORM CLOCK DISTRIBUTION
C AD Techniques to automate the generation of optimum clock distributionnetworks.
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17
SUPERBUFFER
CLOAD
PROBLEM: GIVEN the task of driving a large capacitive load CLOAD
,how can a SUPER BUFFER comprised of chain of N inverters be scaledto minimize the buffer’s delay time?
Cg
1 a2 a3a1
Cd aC
daC
g a2Cg
a2Cd
a3Cg
a3Cd
CLOAD
N = 3
N -> number of inverter stagesa -> optimal stage scale factor
Equiv INV
let CLOAD
= a4 Cg
In General:C
LOAD = aN+1 C
g
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Cg
1 a2 a3a1
Cd aC
daC
g a2Cg
a2Cd
a3Cg
a3Cd
CLOAD
N = 3N -> number of inverter stagesa -> optimal stage scale factor
Equiv INV
td
let CLOAD
= a4 Cg
In General:C
LOAD = aN+1 C
g
Kenneth R. Laker, University of Pennsylvania
18
CONSIDER N stages and CLOAD
= aN+1 Cg
ALL INVERTERS HAVE SAME DELAY
td t
dt
d
τ0 is per gate delay for Equiv INV in ring
oscillator circuit with load capacitance = Cg + C
d.
Choose N and a to MINIMIZE ttotal
where CLOAD
= aN+1 Cg =>
t total = N+1( )τ0Cd + aCg
Cd + Cg
N+1=ln CLOAD/Cg( )
ln a( )
td = τ0Cd + aCg
Cd + Cg
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=>
TO MINIMIZE ttotal
:
= 0
For the SPECIAL CASE Cd = 0 => ln (a
opt) = 1 or a
opt = e1 = 2.718
N+1=ln CLOAD/Cg( )
ln a( )
t total = N+1( )τ0Cd + aCg
Cd + Cg t total =ln CLOAD/Cg( )
ln a( )τ0
Cd + aCg
Cd + Cg
dttotalda
= τ0 lnCLOAD
Cg
− 1/a
ln a( )( )2
Cd + aCg
Cd + Cg
+
1ln a( )
Cg
Cd + Cg
= 0
aopt ln aopt( ) −1[ ] = CdCg
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EXAMPLE: For Cd = 0.5 fF, C
g = 10 fF, determine a
opt and N for
CLOAD
= 50 pF.
aopt
[ln(aopt
) - 1] = 0.5 => aopt
= 3.18
N = [ln(CLOAD
/Cg)/ln(a)] - 1
= [ln(50 x 10-12/1 x 10-14)/ln(3.18)] - 1 = [ln(5000)/ln(3.18)] - 1 = 6.36
The SUPER BUFFER DESIGN which MINIMIZES ttotal
for CLOAD
= 50 pF isN = 7 Equiv INV stagesa
opt = 3.18
N+1=ln CLOAD/Cg( )
ln a( )
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21PLL CLOCKING SCHEMES
dclk
= dout-reg
+ dpad
clk
clk pad
output pad
R
C
dclk
= dclk-buf
+ dRC
+dout-reg
+ dpadclk
dclk
data out
chip
clk
clk pad
R
C
clkd
clk
data out
chipPLL
output pad
WHY USE PLL IN SYSTEM CLOCKS?
+ To syncronize the internal clock of a chip to an external clock.
+ To operate an internal clock at a higher rate than the external clock input.
PhaseDetector Filter VCOclk
÷ n
output - clk
clk-out clk-out
clk-out clk-out
buffer
outputregister
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22clk
clk pad
output pad
R
C
chipPLL
÷ 4
clkclk-out
clockPLL PLL
clock
system clk
bus (high speed - tristate)
Generates an internal fclk-out = 4 × fclksynchronized to clk
sychronizes the out-put enables of two chips
dclk
= dout-reg
+ dpad
chipchip1 chip2
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Rwell
n+ p+ p+n+
VDDV
out
n+p+
n-wellp-sub
Vin
NPNPNPR
sub
LATCHUP IN CMOS CIRCUITS
Rsub
Rwell
VDD
IE2
VB-npn
IRsub
IRwell
I
VB-pnp
IE1
I
Q1 (PNP)
Q2 (NPN)
+
−
V
V
I
0
2.0 mA
VH = 1.5 V
trigger pointIH
slope = 1/RT
VDD
VH
IHR
T
SCR EQIVCKT inLatch-up
latch-up susceptabilityα 1/[NSUB (spacing)2]
Rwell
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24
LATCH-UP CONDITION
Rsub
Rwell
VDD
IE2
VB-npn
IRsub
IRwell
I
VB-pnp
IE1
I
Q1 (PNP)
Q2 (NPN)
+
−
V
At the on-set of latch-up
V
I
0
2.0 mA
VH = 1.5 V
trigger pointIH
slope = 1/RT
VDD
VH
IHR
T
SCR EQIVCKT inLatch-up
I > IH = (V
DD - V
H)/R
T
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Latchup Prevention LAYOUT Guidelines:
A. Latchup resistant CMOS processes (thin epi layer on highly doped substrate).
B. Layout n and p channel transistors such that all nMOS transistors are placedclose to GND and V
DD. Physically separate n and p transistors (i.e. with the
bonding pad).
C. Use p+ guard rings connected to GND around nMOS transistors and n+quardrings connected to V
DD around the pMOS transistors to reduce R
well and R
sub and
to weaken BJTs.
D. Place sub, well contacts close to the nMOS, pMOS source connections tosupply rails (i.e. GND for nMOS, V
DD for pMOS).
CONSERVATIVE RULE: One sub contact per source connection to a supply
LESS CONSERVATIVE: One sub contact per 5-10 devices.
Reduce αnpn
, αpnp
; Reduce Rsub
, Rwell
make small
make largeLATCH-UP PREVENTION
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VDD
GND
n+
nMOS pMOS
p+
p+ guardring toGND
n+ guardring to V
DD
OUTBONDPAD
p-tub edge spacedfar from p+
sources to VDD
I/O CELL LAYOUT USING LATCH-UP GUIDELINES