EE1003 – Project Assignment 3

Electrical and Electronic Engineering

University College Cork

Lecturer: Mr. Alan Morrison

Date: 10/12/2010

Group F:

Group Leader: Shane O’Regan 110344045

Denis O’Riordan 110363499

Stuart O’Grady 110315445

Tadhg Lambe 110307291

Group F EE1003 Assignment 2

Abstract

This Assignment is part of the first year project in EE1003 in Electrical and Electronic Engineering. The purpose of this assignment was to design a single countdown timer with seven segment displays that produces an audible tone when it reaches 00:00.

For this assignment research was conducted in order to determine how to make a digital clock using truncated sequence counters. The circuit was then designed, built and demonstrated in the lab.

A number of important skills were obtained and useful information was recorded. The 555 timer used in the programmable gym timer, must be contained in an astable circuit. This produced a 1 second pulse, which was fed to the digital clock. Important information on the function of decoders, binary counters and LED displays was obtained. A deeper understanding of logic and Boolean algebra was gained through equations and calculations.

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Group F EE1003 Assignment 2

Table of Contents

Abstract...................................................................................................................................... 2

Introduction.............................................................................................................................. 4

1. Research........................................................................................................................... 51.1 555 Timers.................................................................................................................................... 51.2 Asynchronous counter.........................................................................................................101.3 Crystal oscillator..................................................................................................................... 111.4 Astable circuit calculations................................................................................................11

2 Design and Implementation......................................................................................... 122.1 555 Timer Design.................................................................................................................... 122.2 How to drive a 7-Segment Display..................................................................................152.3. Programming the counters...............................................................................................162.4. Counting.................................................................................................................................... 172.5. Implementing the audio tone when the count reaches 00:00.............................19

3. Conclusion........................................................................................................................ 20

5. References......................................................................................................................... 21

6. Work Distribution............................................................................................................ 21Tadhg Lambe................................................................................................................................... 21Denis O’Riordan............................................................................................................................. 22Stuart O’Grady................................................................................................................................ 22Shane O’Regan............................................................................................................................... 23

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Group F EE1003 Assignment 2

Table Of Figures

1.1 Typical 555 Timer chip

1.2 555 timer pin layout

1.3 555 internal circuit diagram

1.4

1.5

1.6

1.7

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Group F EE1003 Assignment 2

Introduction

This project assignment is a group approach to designing a single countdown timer with seven segment displays and an audible tone when the time reaches 00:00. This report contains the reseach and design that went into creating a digital clock, which can count backwards as well as forwards.

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Group F EE1003 Assignment 2

1. Research

1.1 555 TimersIntroduction

The 555 timer IC is a chip used in a wide variety of circuits as a simple timer and is found in a number of electrical devices such as alarms, early pc joysticks etc. The chip was given its name as early designs contained three 5kΩ resistors. 555 timers were created in 1970 by Hans R. Camenzind. The 555 timer is an 8 pin IC chip which is cheap is to manufacture, simple to use and is very stable. The most popular 555 timer is the NE555 timer and there a number of variations of this chip such as the 556 and 558 timers. Low power versions are also available for example the 7557 timer or the TLC555. These chips are not commonly used as their maximum output current is too low for typical electrical circuits. 555 timers usually function efficiently between 4.5 volts & 15 volts.

Fig 1.1 - Typical 555 Timer chip

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Group F EE1003 Assignment 2

Each pin in a 555 timer is connected to a circuit which usually consists of 20 transistors, 2 diodes and 15 resistors. 555 timers have three different operating modes which can be chosen by the user and each has different properties. These modes are known as Astable, Monostable & Bistable modes respectively. The output of a 555 timer can be organized into two levels:

Low - This occurs when the output is 0V and this mode is known as ‘Logic 0’

High - This occurs when the output is greater than 0V e.g. 5V, this mode is known as ‘Logic 1’

Pin Configuration (555 Timer)

Shown below in Fig 1.2 is the pin arrangement of a typical 555 timer IC. Each pin is numbered and their function is described below.

Fig 1.2 – 555 timer pin layout

Pin 1 (Ground)

This pin is connected to 0V powers supply aka Ground.

Pin 2 (Trigger)

When < 1/3 Vs (active low) at pin2 the output will be active high. Pin 2 takes a low input and changes it into one that is active high. Pin 6 is dependent on pin 2’s

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Group F EE1003 Assignment 2

state, so ultimately pin 2 has control over the function of pin 6. For example if pin 2’s input is low and pin 6’s input is high, then the output will be active low.

Pin 3 (Output)

This pin is the output of the 555 timer and can be connected to other devices e.g. other IC chips, loudspeakers etc.

Pin 4 (Reset)

When a voltage less than 0.7 is passed through the reset pin all other inputs are overwritten and the output is changed to active low.

Pin 5 (Control)

This pin is used to control the input voltage of the threshold. The threshold is set to 2/3 Vs. This input can be used to change the timing of the 555 timer. It is usually connected to ground (0V).

Pin 6 (Threshold)

When > 2/3 Vs (active high) at pin 6, the output will be active low, this is provided that the trigger input is greater than 1/3 of the input voltage (Vs).

Pin 7 (Discharge)

This pin coupled with the threshold is used to set up the timing aspect of the 555 timer. It is usually connected to a timing capacitor and discharges it in astable and monostable circuits. Pin 7 may also be connected to a number of resistors, depending on the application.

Pin 8 (Supply)

This pin is connected to the positive terminal of a power supply. The power supply can produce any voltage between 4.5 V and 15 V, but usually a voltage of 5V is produced so that the 555 timer can run efficiently.

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Group F EE1003 Assignment 2

Fig 1.3 – 555 internal circuit diagram

Operating Modes

Astable

In an astable circuit, the output is constantly changing between active high and low. This creates a square shaped wave form. The output is never stable as it is continually fluctuating. The duration of the high and low states may be different, depending on a number of factors. The time period of the waveform produced is the time taken for one complete cycle (Tm + Ts). The frequency (cycles per second) is usually measured.

Fig 1.4 - Square Waveform of an Astable circuit

Astable circuits have a number of functions. They create a waveform which is used a ‘clock’ pulse and this provides the clock signal for counters in an electrical circuit. Low frequency Astable circuits are normally used to make LED

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Group F EE1003 Assignment 2

lights flash at certain intervals or in certain situations a metronome can be created from a loudspeaker. Higher frequency (audio frequency) Astable circuits are used to produce a sound from a loudspeaker or buzzer.

Fig 1.5 - Astable Circuit

Monostable

These circuits produce one pulse which lasts for a certain amount of time. This pulse is usually created in response to the trigger input. The output of this circuit remains in an active low state, until another trigger input is produced i.e. from a button being pushed.

Fig 1.6 - Monostable Waveform

Monostable circuits have one stable state (active low) and are useful for a number of applications e.g. making a buzzer sound or a LED light for a certain period of time. By adding capacitors, a

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Group F EE1003 Assignment 2

monostable circuit can be arranged to be activated by a change in input signal or when the device is switched on.

Fig 1.7 - Monostable Circuit

Bistable

These circuits have two stable states, active high and active low. Bistable circuits are also known as ‘flip flops’. They have two inputs (pin 2 and 4) which create the bistable circuits output. Pin 2 (Trigger) makes the output high, while pin 4 (Reset) creates an low output. Bistable circuits are primarily used as memory units as they are perfect for storing and saving information for later use. When the chip is in this configuration, the trigger is grounded. No capacitors are required in a bistable circuit and Pin 5 and 7 are left disconnected (floating).

Fig 1.8 - Bistable Waveform

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Group F EE1003 Assignment 2

Fig 1.9 – Bistable configured circuit

1.2 Asynchronous counter Asynchronous counter can have 2n-1 possible counting states. However it is also possible to use the basic asynchronous counter to construct special counters with counting states less than their maximum output number. This is achieved by forcing the counter to reset itself to zero at a pre-determined value producing a type of asynchronous counter that has truncated sequences.

Asynchronous counters as the name indicates are not triggered simultaneously. The multiple flip-flops that are connected together to form a counter circuit do not receive the triggering clock signal simultaneously. The flip-flop that represents the least significant count bit of the n-bit counter is connected to the clock signal, the remaining flip-flops receive their clock signals form the outputs of the preceding flip-flops connected in the counter circuit. The clock signal thus ripples through successive flip-flops.

Synchronous counters on the other hand have all the clock inputs of the multiple flip-flops connected to a common clock signal. All the flip-flops in a Synchronous counter receive clock signals simultaneously.

1.3 Crystal oscillator

A crystal oscillator is an electronic oscillator circuit that uses the mechanical resonance of a vibrating crystal of piezoelectric material to create an electrical signal that has a very precise frequency. This frequency is commonly used to keep track of time. It can be used to provide a stable clock signal for digital integrated circuits.

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Group F EE1003 Assignment 2

1.4 Astable circuit calculations

An astable circuit produces a 'square wave', this is a digital waveform with sharp transitions between low (0V) and high (+Vs). Note that the durations of the low and high states may be different. The circuit is called an astable because it is not stable in any state: the output is continually changing between 'low' and 'high'.

The time period (T) of the square wave is the time for one complete cycle, but it is usually better to consider frequency (f) which is the number of cycles per second.

T = 0.69 × (R1 + 2R2) × C1 and f = 1.4

(R1 + 2R2) × C1

Fig 1.10 – Equation used to calculate total time of one pulse and the frequency generated

T = time period in seconds (s) f = frequency in hertz (Hz) R1 = resistance in ohms (Ω) R2 = resistance in ohms (Ω) C1 = capacitance in farads (F)

Duty cycle

The duty cycle of an astable circuit is the proportion of the complete cycle for which the output is high (the mark time). It is usually given as a percentage.

For a standard 555/556 astable circuit the mark time (Tm) must be greater than the space time (Ts), so the duty cycle must be at least 50%:

Duty cycle = Tm = R1 + R2

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Group F EE1003 Assignment 2

Tm + Ts R1 + 2R2

Fig 1.10 – Equation used to calculate duty cycle

2 Design and Implementation

2.1 555 Timer Design

The 555 timer created for use in the programmable gym timer, is created by using a basic LM555 integrated chip, capacitors, and a number of resistors. Using a breadboard & multisim, a 555 timer circuit was designed and its function was observed. The capacitors & resistors needed to produce a constant 1 sec interval were selected by using the formula used to calculate duty cycle (see eqn. 1). This timer created a continuous 1 second pulse which the clock used to count forward and backwards. The astable 555 timer is perfect for clocking digital circuits.

Calculations

Conditions

T1 = 0.693(R1+R2)C

T2 = 0.693(R2)C

T = 0.693(R1+2R2)C

F =1/T = 1.44/(R1+2R2)C = 1Hz

C = 100µF [100(E-6)F]

Duty Cycle = T1/T = 60%

1.443001443/(R1+2R2)C = 1

1.443001443 = (R1+2R2)C

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Group F EE1003 Assignment 2

1.443001443 = (R1+2R2)(100µF)

14430.01443 = R1+2R2

R1 = 14430.01443 – 2R2

Duty Cycle = 60% = R1+R2/R1+2R2

60R1+120R2 = 100R1+100R2

R1=1/2R2

R1 = 14430.01443 – 2R2

1/2R2 = 14430.01443 – 2R2

2.5R2 = 14430.01443

R2 = 5772.00572Ω

R2 = 5.772 kΩ

R1 = 1/2R2

R1 = ½(5772.00572)

R1 = 2886.00286Ω

R2 = 2.886 kΩ

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Group F EE1003 Assignment 2

Fig 2.1 – 555 timer circuit created using multisim

2.2 How to drive a 7-Segment Display.

First in order to use a seven segment display you need a display driver. The display driver used in this project is the 7447 integrated circuit fig 2.2.1.

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Group F EE1003 Assignment 2

Fig: 2.2.1 7447 pin layout

The display has seven active low outputs (a-g), 4 data inputs (A-D), and display test and blanking inputs. The 7447 is then driven by a 74192 decade counter Fig 2.2.2. Whose ouputs (QA – QD) are connected to the inputs A-D on the 7447

Fig:2.2.2 74192 Decade counter pin layout

The 74192 takes inputs from inputA – inputD, when ‘preset’ is set to low. The current value in the counter is set to zero when reset is set to high. The 74192 counts up when the clock is connected to ‘up clock’ and a high is conected to ‘down clock. The 74192 counts down when a clock is connected to the down

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Group F EE1003 Assignment 2

clock’ and a high is connected to ‘up clock’. It is also possible to cascaded several 74192s together by connecting the the borrow and carry outputs to the clock inputs on the next 74192.

2.3. Programming the counters.In order to progran the 74192s when not counting the desired input in

BCD (binary coded decimal) has to be provided on the inputs ‘DATA A - DATA D’, while the preset input is connected to a low signal. There are a few methods for accomplishing this.

1. Switches can be used to set the data inputs on the 74192s. Four switches would be used. The input of the switch would be connected to Vcc and the output would be connected to ground through a resistor, and the counter. There would be four switches for the four bits required. The preset input on the counter would be brought to ground in order to set the values in the counter from the switches. This solution would be simple for designing the circuit, however it would not be ideal for the user as they would have to know the BCD values.

2. Another method would be to use an encoder such as the 74147 10-Line Decimal to 4-Line BCD Priority Encoder (Fig 2.3.1). There would be nine switches for the nine inputs on the encoder. These switches can then be arranges in the form of a keypad for easy use. The encoder operates by producing the appropiate output when a input is recieved. The outputs of the encoder would then be connected to the data inputs on the counters. There would then be four switches, one per counter that would then be used to set the preset pin on the counters to ground when programming the individual counters. Alternatively further logic could be used to set the counters one after another automatically when a input to the encoder is recieved. This approach would benifit the user as it would make it easier to input the values.

Fig: 2.3.1 74147 BCD encoder.

2.4. Counting2.4.1 Switching between counting up and counting down

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Group F EE1003 Assignment 2

The 74192 decade counter can count both up and down by providing the correct inputs on the ‘Count Up’ and Count Down’ pins. In order to count up the clock needs to be connected to the count up pin on the 74192 and the count down pin needs to be connected to Vcc. In order to count down the clock needs to be connected to the count down pin, and Vcc needs to be connected to the count up pin. This can be implemented using two NAND gates, two AND gates and a switch. Fig 2.4.1.1 is the circuit diagram of the circuit needed.

Truth Table of the Function.

Switch

Clock Count Up

Count Down

0 0 1 00 1 1 11 0 0 11 1 1 0

Fig:2.4.1.1 Circuit diagram of switching between counting up and down

2.4.2 Counting in minutes and seconds.

In the design four 74192 decade counters, and four 7447 7-segment display drivers are used to drive four 7-segment displays. In order to display the time in minutes and seconds with the maximum of ‘59:59’ fifty nine minutes and fifty nine seconds the following has to be performed:

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Group F EE1003 Assignment 2

1. While counting up when the outputs of the second or the fourth 74192 reach the value of ‘6’ or 0110 in binary coded decimal (BCD) the reset on the corresponding 74192 is set to high. Also a clock output needs to be sent from the second 74192 to the third 74192 when the value of 6 is reached in the outputs of the second 74192. This can be performed by anding ‘output OB’ and ‘output OC’ and putting the result into the reset pin and the up clock input for the third 74192. OB.OC = reset = (up clock on third counter for second counter only)

2. While counting down when the output of the second or the fourth counter reaches ‘9’ or ‘1001’ in BCD, the value of ‘5’ or ‘0101’ in BCD needs to be loaded into the second or fourth counter. This is done by having the value of five (0101) entered into the inputs of the 74192s when counting. Then when the most significant bit in the output OA is high, you put the preset in the corresponding 74192 to low (ground). This can be done by connecting OA inverted from the second and fourth counters to the preset input on the second and fourth counters respectively.

2.5. Implementing the audio tone when the count reaches 00:00When the time displayed in the 7-segment displays reaches 00:00 the

outputs from the counters going to the 7447 display drivers are all low (zero). Therefore if you were to NOR these outputs together you would get a high when they are all zero. You could the connect a piezo buzzer to the output of this NOR gate which would produce an audio output when the displays are at 00:00.

The problem with this is that there is no sixteen input NOR gate in the 7400 series. Instead it would be necessary to use two 7423 Dual Quad input NOR gate chips which would have four quad input NOR gates. The outputs of these NOR gates would then need to be ANDed together. To do this you could use the 7421 Dual Four input AND gates chip. The outputs from the counters would then be put into the NOR gates, the outputs of the NOR gates would be ANDed together and the output of the AND gate would be high when all the inputs are low. The piezo buzzer would then be connected to the output of the AND gate which would produce the needed audio output.

Fig: 2.5.1 Boolean Algebra solution for the function.

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Group F EE1003 Assignment 2

2.6 Block Diagram

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Group F EE1003 Assignment 2

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Group F EE1003 Assignment 2

3. Conclusion

In this report we have all researched the various components required for the power supply for our gym timer. We have researched the power requirements, voltage levels, battery power vs. mains power supply, voltage regulators, transformers, rectifiers and smoothing capacitors.

We have also designed and simulated the AC and battery power supply circuits on Multisim, which has further enhanced our knowledge on the understanding and verification of requirements of the power supply and voltage levels.

We designed a mains power and battery power circuits in the lab and tested the use of voltage regulators. These again helped increase our practical knowledge and understanding of the circuits involved.

As a team we discussed the benefits and disadvantages of battery power and ac power supplies and came to a final discussion that battery power was the most practical to use.

5. References

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Group F EE1003 Assignment 2

http://www.national.com/mpf/LM/LM340.html#Overviewhttp://www.national.com/mpf/LM/LM317.html#Overviewhttp://en.wikipedia.org/wiki/Electric_powerhttp://www.national.com/ds/LM/LM340.pdfhttp://en.wikipedia.org/wiki/Voltage_regulatorhttp://www.tpub.com/neets/book7/27c.htmhttp://www.kpsec.freeuk.com/powersup.htmhttp://en.wikipedia.org/wiki/Diode_bridgehttp://www.google.ie/images/http://www.datasheetcatalog.com/datasheets_pdf/7/4/0/0/7400.shtml

6. Work Distribution

Shane O’Regan

Formatting and editing of assignment

Introduction

Table of Contents

Table of figures

1.1 555 Timers

1.2 Asynchronous counter

1.4 Astable circuit calculations

Tadhg Lambe

2.2 How to drive a 7-Segment Display.

2.3. Programming the counters.

2.4. Counting

2.5. Implementing the audio tone when the count reaches 00:00

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Group F EE1003 Assignment 2

Denis O’Riordan

1.1 555 Timers

2.1 555 Timer Design

Stuart O’Grady

1.2 Asynchronous counter

1.3 Crystal oscillator

2.1 555 Timer Design

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