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EE105 – Fall 2015 Microelectronic Devices and Circuits

Prof. Ming C. Wu

wu@eecs.berkeley.edu

511 Sutardja Dai Hall (SDH)

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Circuit Symbol for NMOS

Simplified circuit symbol with body connected to source (or when the effect of the body on device operation is unimportant)

4 terminal including Body (Arrow pointing to channel indicating substrate is p-type)

Modified circuit symbol with arrow on source (Arrow indicating direction of current flow)

Note in NMOS 1.  Drain voltage is always more positive than Source voltage 2.  Current always flows from Drain to Source

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I-V Curves of NMOS

Vtn : threshold voltage of NMOS

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Relative Voltage Levels of NMOS

Analog circuit (e.g., linear amplifiers) usually biased in Saturation region

Digital circuit (e.g., inverter) use Triode region as one of the states

Vtn : threshold voltage of NMOS Vtn is usually fixed once a process (technology) is selected

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Drain Current vs Gate Voltage

In Saturation Region

iD =12µnCox

WLvOV

2

=12µnCox

WL

vGS −Vtn( )2

To experimentally determine Vtn :

Measure and plot iD versus vGS

iD =12µnCox

WL

vGS −Vtn( )

Vtn = intercept with horizontal axis

iD

vGSVtn

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Finite Output Resistance due to Channel Length Modulation

When vDS = vOV , the channel pinch of near the Drain. With further increase in vDS, the pinch off point moves slowly towards the source, effectively reducing the channel length from L to L −ΔL (this is called "channel length modulation") :

iD =12µnCox

WL −ΔL

vGS −Vtn( )2

The continual increase of iD with vDS is modeled by

iD =12µnCox

WL

vGS −Vtn( )2 1+λvDS( )

4

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Output Resistance of MOSFET iD =

12µnCox

WL

vGS −Vtn( )2 1+λvDS( )

ro =∂vDS∂iD

#

$%

&

'(vGS=VGS

=∂iD∂vDS

#

$%

&

'(

−1

vGS=VGS

=1

λ12µnCox

WLVGS −Vtn( )2#

$%

&

'(≈

1λID

ro =1λID

where ID =12µnCox

WLVGS −Vtn( )2 is the DC bias current at Drain.

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Simplified circuit symbol with body connected to source (or when the effect of the body on device operation is unimportant)

4 terminal including Body (Arrow pointing away from channel indicating substrate is n-type)

Modified circuit symbol with arrow on source (Arrow indicating direction of current flow)

Note in PMOS 1.  Source voltage is always more positive than Drain voltage 2.  Current always flows from Source to Drain 3.  Source is usually drawn on top so current flows downward

(convention)

Circuit Symbol of PMOS

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PMOS I-V Equations

Saturation Region:

iD =12µpCox

WL

!

"#

$

%& vGS − Vtp( )

2

=12µpCox

WL

!

"#

$

%&vOV

2

Triode Region:

iD = µpCoxWL

vOV vDS −12vDS

2"

#$

%

&'

vOV = vSG − VtpUse same equation as NMOS butadd absolute sign on all voltagessince most voltages are negative:Vtp < 0, vDS < 0, vGS < 0

So either use vSD or vDS

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Relative Voltage Levels of PMOS

Analog circuit (e.g., linear amplifiers) usually biased in Saturation region

Digital circuit (e.g., inverter) use Triode region as one of the states

Vtp : threshold voltage of PMOS Vtp is usually fixed once a process (technology) is selected

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With Gate connected to Drain, it becomes a 2-terminal device.This is called "diode-connected transistor"In this configuration, the transistor is always in "Saturaiton".Its I-V relationship is:

i = ID =12µnCox

WLvOV

2

vGS = vDS = vvOV = vGS −Vtn = v−Vtn

i = 12µnCox

WL

v−Vtn( )2

Diode-Connected Transistor

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Example Circuit (1) Design Problem: Determine RS and RD such that the NMOS is biased at ID = 0.4mAand VD = 0.5V. The NMOS has Vt = 0.7V, µnCox =100µA /V 2,L =1µm and W = 32µm.

Solution:

RD =VDD −VD

ID=

2.5− 0.50.4

= 5kΩ

ID =12µnCox

WLvOV

2 = 0.4mA --> vOV = 0.5V

(channel length modulation can usually be ignored when solving DC bias)vGS =Vt + vOV = 0.7+ 0.5=1.2VVG = 0 (grounded) --> VS = −1.2V

RD =VS −VSSID

=−1.2− (−2.5)

0.4= 3.25kΩ

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Example Circuit (2) The resistor divider is a common bias circuit.

To solve the DC bias condition, it means to solveID,VDS,VGS

The NMOS has Vtn =1V, kn = µnCoxWL=1mA /V 2

First, solve VG =VDDRG2

RG1 + RG2

=10 55+ 5

= 5V

VGS = 5− IDRS = 5− 6ID (with ID in mA)Next, assume the transistor is in saturation:

ID =12knvOV

2 = 0.5 VGS −Vtn( )2= 0.5 5− 6ID −1( )2

18ID2 − 25ID +8 = 0 --> ID = 0.89mA or 0.5mA

If ID = 0.89mA, VGS = −0.34V, NMOS will be cut-off--> not a physical solution.If ID = 0.5mA, VGS = 2V, VOV = 2−1=1VVDS =VDD − ID (RD + RS ) =10− 6 = 4V >VOVSaturation assumption verified !

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Example Circuit (3)

Design Problem: Design the circuit such that ID = 0.5mA and VD = 3V. PMOS has Vtp = −1V, µpCox (W / L) =1mA /V 2.Also find the maximum RD for PMOS to remain in Saturation

Solution:

ID =12kpVOV

2 = 0.5mA --> VOV =1V

VGS = Vtp + VOV =1+1= 2V

VS = 5V --> VG = 3VWe can choose RG1 = 2MΩ and RG2 = 3MΩ

Saturation: VD ≤ 5− VOV = 4V

RD,max =VD,max

I D=

40.5

= 8kΩ